Relevant bibliographies by topics / On-chip memory TCAM

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic 'On-chip memory TCAM'

Author: Grafiati
Published: 5 June 2025
Last updated: 24 June 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'On-chip memory TCAM.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "On-chip memory TCAM"

1

Nguyen, Triet, Kiet Ngo, Nguyen Trinh, Bao Bui, Linh Tran, and Hoang Trang. "Efficient TCAM design based on dual port SRAM on FPGA." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (2021): 104–12. https://doi.org/10.11591/ijeecs.v22.i1.pp104-112.

Full text
Abstract:
Ternary content addressable memory (TCAM) is a memory that allows high speed searching for data. Not only it is acknowledged as associative memory/storage but also TCAM can compare input searching content (key) against a collection of accumulated data and return the matching address which compatible with this input search data. SRAM-based TCAM utilizes and allocates blocks RAM to perform application of TCAM on FPGA hardware. This paper presents a design of 480×104 bit SRAM-based TCAM on altera cyclone IV FPGA. Our design achieved lookup rate over 150 millions input search data and update speed at 75 million rules per second. The architecture is configurable, allowing various performance trade-offs to be exploited for different ruleset characteristics.
APA, Harvard, Vancouver, ISO, and other styles
2

Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen, and Linh Tran. "Algorithmic TCAM on FPGA with data collision approach." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (2021): 89–96. https://doi.org/10.11591/ijeecs.v22.i1.pp89-96.

Full text
Abstract:
Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.
APA, Harvard, Vancouver, ISO, and other styles
3

Lin, Hsin-Tsung, Wei-Han Pan, and Pi-Chung Wang. "Packet Classification Using TCAM of Narrow Entries." Technologies 11, no. 5 (2023): 147. http://dx.doi.org/10.3390/technologies11050147.

Full text
Abstract:
Packet classification based on rules of packet header fields is the key technology for enabling software-defined networking (SDN). Ternary content addressable memory (TCAM) is a widely used hardware for packet classification; however, commercially available TCAM chips have only limited storage. As the number of supported header fields in SDN increases, the number of supported rules in a TCAM chip is reduced. In this work, we present a novel scheme to enable packet classification using TCAM with entries that are narrower than rules by storing the most representative field of a ruleset in TCAM. Due to the fact that not all rules can be distinguished using one field, our scheme employs a TCAM-based multimatch packet classification technique to ensure correctness. We further develop approaches to reduce redundant TCAM accesses for multimatch packet classification. Although our scheme requires additional TCAM accesses, it supports packet classification upon long rules with narrow TCAM entries, and drastically reduces the required TCAM storage. Our experimental results show that our scheme requires a moderate number of additional TCAM accesses and consumes much less storage compared to the basic TCAM-based packet classification. Thus, it can provide the required scalability for long rules required by potential applications of SDN.
APA, Harvard, Vancouver, ISO, and other styles
4

Bazzi, Hiba S., Ramzi A. Jaber, Ahmad M. El-Hajj, Fathelalem A. Hija, and Ali M. Haidar. "Enhanced CPU Design for SDN Controller." Micromachines 15, no. 8 (2024): 997. http://dx.doi.org/10.3390/mi15080997.

Full text
Abstract:
Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power–Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.
APA, Harvard, Vancouver, ISO, and other styles
5

Daneshtalab, Masoud, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen. "Memory-Efficient On-Chip Network With Adaptive Interfaces." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 1 (2012): 146–59. http://dx.doi.org/10.1109/tcad.2011.2160348.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Da-Wei Chang, Ing-Chao Lin, Yu-Shiang Chien, Chin-Lun Lin, Alvin W. Y. Su, and Chung-Ping Young. "CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 12 (2014): 1806–17. http://dx.doi.org/10.1109/tcad.2014.2363385.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Chang, Hoseok, and Wonyong Sung. "Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, no. 1 (2009): 158–63. http://dx.doi.org/10.1109/tcad.2008.2009145.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Zhao, Mengying, Chenchen Fu, Zewei Li, et al. "Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 11 (2017): 1804–16. http://dx.doi.org/10.1109/tcad.2017.2666606.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Oboril, Fabian, Rajendra Bishnoi, Mojtaba Ebrahimi, and Mehdi B. Tahoori. "Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, no. 3 (2015): 367–80. http://dx.doi.org/10.1109/tcad.2015.2391254.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Wang, Ying, Huawei Li, and Xiaowei Li. "A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 10 (2018): 1971–84. http://dx.doi.org/10.1109/tcad.2017.2778060.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "On-chip memory TCAM"

1

Gnawali, Krishna Prasad. "EMERGING MEMORY-BASED DESIGNS AND RESILIENCY TO RADIATION EFFECTS IN ICS." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1863.

Full text
Abstract:
The performance of a modern computing system is improving with technology scaling due to advancements in the modern semiconductor industry. However, the power efficiency along with reliability does not scale linearly with performance efficiency. High leakage and standby power in sub 100 nm technology are critical challenges faced by circuit designers. Recent developments in device physics have shown that emerging non-volatile memories are very effective in reducing power dissipation because they eliminate stand by power and exhibit almost zero leakage powerThis dissertation studies the use of emerging non-volatile memory devices in designing circuit architecture for improving power dissipation and the performance of the computing system. More specically, it proposes a novel spintronic Ternary Content AddressableMemory (TCAM), a novel memristive TCAM with improved power and performance efficiency. Our experimental evaluation on 45 nm technology for a 256-bit word-size spintronic TCAM at a supply voltage of 1 V with a sense margin of 50 mV show that the delay is lessthan 200 ps and the per-bit search energy is approximately 3 fJ. The proposed spintronic TCAM consumes at least 30% less energy when compared to state-of-the-art TCAM designs. The search delay on a 144-bit proposed memristive TCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ on a 45 nm technology. It is 1.12 x times faster and dissipates 67% less search energy per bit than the fastest existing 144-bit MTCAM design.Emerging non-volatile memories are well known for their ability to perform fast analog multiplication and addition when they are arranged in crossbar fashion and are especially suited for neural network applications. However, such systems require the on-chip implementation of the backpropagation algorithm to accommodate process variations. This dissertation studies the impact of process variation in training memristive neural network architecture. It proposes a low hardware overhead on-chip implementation of the backpropagation algorithm that utilizes effectively the very dense memristive cross-bar arrayand is resilient to process variations.Another important issue that needs a careful study due to shrinking technology node is the impact of space or terrestrial radiation in Integrated Circuits (ICs) because the probability of a high energy particle causing an error increases with a decrease in thethreshold voltage and the noise margin. Moreover, single-event effects (SEEs) sensitivity depends on the set of input vectors used at the time of testing due to logical masking. This dissertation analyzes the impact of input test set on the cross section of the microprocessorand proposes a mechanism to derive a high-quality input test set using an automatic test pattern generation (ATPG) for radiation testing of microprocessors arithmetic and logical units..
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "On-chip memory TCAM"

1

Heeyeol Yu. "A memory- and time-efficient on-chip TCAM minimizer for IP lookup." In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010. http://dx.doi.org/10.1109/date.2010.5456921.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Hsieh, Chih-Chang, Hang-Ting Lue, Yung-Chun Li, et al. "Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance." In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). IEEE, 2023. http://dx.doi.org/10.23919/vlsitechnologyandcir57934.2023.10185361.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'On-chip memory TCAM' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography