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Journal articles on the topic 'On-chip memory TCAM'

Author: Grafiati
Published: 5 June 2025
Last updated: 1 August 2025

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1

Nguyen, Triet, Kiet Ngo, Nguyen Trinh, Bao Bui, Linh Tran, and Hoang Trang. "Efficient TCAM design based on dual port SRAM on FPGA." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (2021): 104–12. https://doi.org/10.11591/ijeecs.v22.i1.pp104-112.

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Ternary content addressable memory (TCAM) is a memory that allows high speed searching for data. Not only it is acknowledged as associative memory/storage but also TCAM can compare input searching content (key) against a collection of accumulated data and return the matching address which compatible with this input search data. SRAM-based TCAM utilizes and allocates blocks RAM to perform application of TCAM on FPGA hardware. This paper presents a design of 480×104 bit SRAM-based TCAM on altera cyclone IV FPGA. Our design achieved lookup rate over 150 millions input search data and update
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2

Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen, and Linh Tran. "Algorithmic TCAM on FPGA with data collision approach." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (2021): 89–96. https://doi.org/10.11591/ijeecs.v22.i1.pp89-96.

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Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have b
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3

Lin, Hsin-Tsung, Wei-Han Pan, and Pi-Chung Wang. "Packet Classification Using TCAM of Narrow Entries." Technologies 11, no. 5 (2023): 147. http://dx.doi.org/10.3390/technologies11050147.

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Packet classification based on rules of packet header fields is the key technology for enabling software-defined networking (SDN). Ternary content addressable memory (TCAM) is a widely used hardware for packet classification; however, commercially available TCAM chips have only limited storage. As the number of supported header fields in SDN increases, the number of supported rules in a TCAM chip is reduced. In this work, we present a novel scheme to enable packet classification using TCAM with entries that are narrower than rules by storing the most representative field of a ruleset in TCAM.
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4

Bazzi, Hiba S., Ramzi A. Jaber, Ahmad M. El-Hajj, Fathelalem A. Hija, and Ali M. Haidar. "Enhanced CPU Design for SDN Controller." Micromachines 15, no. 8 (2024): 997. http://dx.doi.org/10.3390/mi15080997.

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Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compa
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5

Daneshtalab, Masoud, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen. "Memory-Efficient On-Chip Network With Adaptive Interfaces." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 1 (2012): 146–59. http://dx.doi.org/10.1109/tcad.2011.2160348.

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6

Da-Wei Chang, Ing-Chao Lin, Yu-Shiang Chien, Chin-Lun Lin, Alvin W. Y. Su, and Chung-Ping Young. "CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 12 (2014): 1806–17. http://dx.doi.org/10.1109/tcad.2014.2363385.

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7

Chang, Hoseok, and Wonyong Sung. "Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, no. 1 (2009): 158–63. http://dx.doi.org/10.1109/tcad.2008.2009145.

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8

Zhao, Mengying, Chenchen Fu, Zewei Li, et al. "Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 11 (2017): 1804–16. http://dx.doi.org/10.1109/tcad.2017.2666606.

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9

Oboril, Fabian, Rajendra Bishnoi, Mojtaba Ebrahimi, and Mehdi B. Tahoori. "Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, no. 3 (2015): 367–80. http://dx.doi.org/10.1109/tcad.2015.2391254.

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10

Wang, Ying, Huawei Li, and Xiaowei Li. "A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 10 (2018): 1971–84. http://dx.doi.org/10.1109/tcad.2017.2778060.

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11

Salamy, Hassan, and J. Ramanujam. "An Effective Solution to Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 5 (2012): 717–25. http://dx.doi.org/10.1109/tcad.2011.2181848.

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12

Ю.В., Катунин, та Стенин В.Я. "Моделирование устойчивости к сбоям КМОП элементов ассоциативной памяти с использованием средств TCAD". Труды НИИСИ РАН 8, № 3 (2018): 71–79. http://dx.doi.org/10.25682/niisi.2018.3.0013.

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Ячейки памяти STG DICE (Spaced Transistor Groups DICE) с транзисторами, разделенными на две группы, совместно с комбинационной логикой являются основой для проектирования устойчивых к сбоям элементов ассоциативной памяти. Результаты TCAD моделирования воздействий одиночных ядерных частиц с треками, проходящими на глубинах от 50 нм до 850 нм от поверхности кристалла, показывают, что воздействия заряда с трека только на одну из групп транзисторов не приводит к сбоям в диапазоне линейных потерь энергии (ЛПЭ) 1-60 МэВ×см2/мг. Сбой логического состояния STG DICE возможен при треках вдоль линии, сое
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13

Couzi, Noémie, Paul Devoge, Abderrezak Marzaki, et al. "Innovative Design and Validation of a Zero-Cost Medium-Voltage Transistor for Iot Applications." ECS Meeting Abstracts MA2025-01, no. 36 (2025): 1726. https://doi.org/10.1149/ma2025-01361726mtgabs.

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The growing demands of the Internet of Things (IoT) industry require the development of efficient and cost-effective manufacturing technologies [1, 2]. In this context, this paper presents a fabrication process flow, physical and electrical simulations (based on Technology Computer Aided Design or TCAD tools) and electrical and reliability experimental results related to a new zero-cost transistor manufactured in a 40 nm embedded Non-Volatile Memory (eNVM) technology. This transistor is designed to provide the same electrical characteristics as a Medium Voltage (MV) MOS transistor. The propose
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14

Li, Yijun, Jianshi Tang, Bin Gao, et al. "Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning." Nature Communications 14, no. 1 (2023). http://dx.doi.org/10.1038/s41467-023-42981-1.

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AbstractIn this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and car
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15

"Multi-Core Eight Bit Ternary Content-Addressable Memory Design Based Image Learning System." International Journal of Innovative Technology and Exploring Engineering 9, no. 1 (2019): 4037–41. http://dx.doi.org/10.35940/ijitee.a5303.119119.

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In this research work, the image is learned to find features to make use of during its analysis and a genetic apices based low power Ternary Content-Addressable Memory (TCAM) is designed to implement the proposed image learning system. A technique called Content Matching Search Register is proposed in this work to perform the image learning operations in proposed TCAM architecture. This paper proposes an ImOFF algorithm for image analysis. The focus of this multi-core TCAM (MC-TCAM) is to make fast computations and search based designs. The focus application of this research work is in the des
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16

Xu, Weihong, Saransh Gupta, Justin Morris, et al. "Tri-HD: Energy-Efficient On-Chip Learning With In-Memory Hyperdimensional Computing." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024, 1. http://dx.doi.org/10.1109/tcad.2024.3435679.

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17

Chang, Da-Wei, Ing-Chao Lin, and Lin-Chun Yong. "ROHOM: Requirement-aware Online Hybrid On-chip Memory Management for Multicore Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 1. http://dx.doi.org/10.1109/tcad.2016.2584048.

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18

Pilato, Christian, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P. Carloni. "System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 1. http://dx.doi.org/10.1109/tcad.2016.2611506.

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19

"An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 1 (2005): 4–17. http://dx.doi.org/10.1109/tcad.2004.839493.

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20

Peng, Xiaochen, Shanshi Huang, Hongwu Jiang, Anni Lu, and Shimeng Yu. "DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 1. http://dx.doi.org/10.1109/tcad.2020.3043731.

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21

Rani, Khushboo, and Hemangee K. Kapoor. "Investigating Frequency Scaling, Non-Volatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 1. http://dx.doi.org/10.1109/tcad.2020.3007555.

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