Relevant bibliographies by topics / On-chip redundancy

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'On-chip redundancy'

Author: Grafiati
Published: 30 May 2022
Last updated: 31 July 2025

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Journal articles on the topic "On-chip redundancy"

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Rozanov, V. V., and E. A. Suvorova. "VLSI AND SYSTEM-ON-CHIP REDUNDANT COMPONENTS SYNTHESIS." Issues of radio electronics, no. 8 (August 20, 2018): 33–39. http://dx.doi.org/10.21778/2218-5453-2018-8-33-39.

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Redundancy - mostly used method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault tolerance. From Application Specified Integrated Circuit (ASIC) design point of view redundancy means area and power increasing. On early design stages, it is necessary to see the correlation between the components hardware description and its synthesized equivale
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Zhou, Xiaofeng, Lu Liu, and Zhangming Zhu. "A Fault-Tolerant Deflection Routing for Network-on-Chip." Journal of Circuits, Systems and Computers 26, no. 03 (2016): 1750037. http://dx.doi.org/10.1142/s0218126617500372.

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Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performa
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Li, Ran, Rui Ding, Zi Jian Min, and Hui Mei Yuan. "Design of Redundant Parallel Power Supply Based on Integrated DC/DC Modules." Applied Mechanics and Materials 229-231 (November 2012): 1568–71. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1568.

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Taking into account the efficiency, cost-effectiveness and reliability of power supply, redundant parallel power supply controlled by microcontroller could be a good solution for us. This paper analyzes principles and traits of parallel current sharing structure. Then a design of redundancy parallel current sharing structure is introduced, which is based on integrated buck chip LM2678 and microcontroller MSP430. The design has good fault-tolerant ability, and its output voltage can be adjusted easily. The capability and feasibility of this design has been verified by the simulation and experim
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Yu, Qiaoyan, Meilin Zhang, and Paul Ampadu. "Addressing network-on-chip router transient errors with inherent information redundancy." ACM Transactions on Embedded Computing Systems 12, no. 4 (2013): 1–21. http://dx.doi.org/10.1145/2485984.2485993.

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Yu, Anbo, Chenyu Wang, Xiaoqiang Guo, Zheng Li, Chunjiang Zhang, and Josep M. Guerrero. "New Rotor Position Redundancy Decoding Method Based on Resolver Decoder." Micromachines 13, no. 6 (2022): 903. http://dx.doi.org/10.3390/mi13060903.

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In view of the frequent safety problems of electric vehicles, the research on accurately obtaining the rotor position of the motor through the resolver is an important means to improve the functional safety of the system. The commonly used resolver decoding method involves the resolver decoding chip method and software decoding method, but few studies integrate the two decoding methods. A single method of motor rotor position acquisition cannot meet the requirements of system functional safety. To fill this gap, this paper proposes a method to simultaneously integrate hardware decoding and sof
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Cai, Bai-gen, Cheng-ming Jin, Lian-chuan Ma, Yuan Cao, and Hideo Nakamura. "Analysis on the application of on-chip redundancy in the safety-critical system." IEICE Electronics Express 11, no. 9 (2014): 20140153. http://dx.doi.org/10.1587/elex.11.20140153.

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Cao, Ruihu, Niansong Mei, and Qian Lian. "Method for Improving the Reliability of SRAM-Based PUF Using Convolution Operation." Electronics 11, no. 21 (2022): 3493. http://dx.doi.org/10.3390/electronics11213493.

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This paper introduces a novel and efficient physical unclonable function (PUF) extraction method for SRAM. The proposed one-layer convolution scheme is based on a convolution operation, which significantly enhances the reliability of the PUF. To further reduce the hardware resources, a lightweight solution is presented based on a one-layer convolution scheme at the cost of a higher redundancy coefficient and a larger range for the inter-chip Hamming distance (HD). Both the above schemes only use certain hardware resources in the initial stage and the hardware resources are automatically releas
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UPADHYAYA, SHAMBHU J., and I.-SHYAN HWANG. "DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS." International Journal of Reliability, Quality and Safety Engineering 02, no. 04 (1995): 419–29. http://dx.doi.org/10.1142/s0218539395000290.

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This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spar
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Mohammed, Hala, Wameedh Flayyih, and Fakhrul Rokhani. "Tolerating Permanent Faults in the Input Port of the Network on Chip Router." Journal of Low Power Electronics and Applications 9, no. 1 (2019): 11. http://dx.doi.org/10.3390/jlpea9010011.

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Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses
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Sun, H., Q. Sun, S. Biereigel, et al. "A radiation tolerant clock generator for the CMS endcap timing layer readout chip." Journal of Instrumentation 17, no. 03 (2022): C03038. http://dx.doi.org/10.1088/1748-0221/17/03/c03038.

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Abstract We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizi
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Dissertations / Theses on the topic "On-chip redundancy"

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Keller, Andrew Mark. "Using On-Chip Error Detection to Estimate FPGA Design Sensitivity to Configuration Upsets." BYU ScholarsArchive, 2017. https://scholarsarchive.byu.edu/etd/6302.

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SRAM-based FPGAs provide valuable computation resources and reconfigurability; however, ionizing radiation can cause designs operating on these devices to fail. The sensitivity of an FPGA design to configuration upsets, or its SEU sensitivity, is an indication of a design's failure rate. SEU mitigation techniques can reduce the SEU sensitivity of FPGA designs in harsh radiation environments. The reliability benefits of these techniques must be determined before they can be used in mission-critical applications and can be determined by comparing the SEU sensitivity of an FPGA design with and wi
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Chenet, Cristiano Pegoraro. "Análise de soft errors em conversores analógico-digitais e mitigação utilizando redundância e diversidade." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/127693.

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Este trabalho aborda os soft errors em conversores de dados analógico-digitais e a mitigação usando redundância e diversidade. Nas tecnologias CMOS recentes, os efeitos singulares (SEEs, Single Event Effects) são um grupo de efeitos da radiação espacial que afetam a confiabilidade e disponibilidade dos sistemas. Os soft errors são SEEs que não danificam diretamente o sistema e podem ser posteriormente corrigidos. Seus principais subgrupos são o Single Event Upset (SEU), o Single Event Transient (SET) e o Single Event Functional Interrupt (SEFI). Uma das técnicas em nível de sistema amplamente
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Aguilera, Carlos Julio González. "Avaliação de conversores AD sob efeitos de radiação e mitigação utilizando redundância com diversidade." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/179530.

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Este trabalho aborda um sistema de aquisição de dados (SAD) analógico-digital, baseado em um esquema redundante com diversidade de projeto, que é testado em dois ambientes diferentes de radiação. O primeiro experimento considera um teste de dose total ionizante (Total Ioninzig Dose - TID) sob irradiação gama, e o segundo experimento considera os efeitos de eventos singulares (Single Event Effects - SEE) sob irradiação por íons pesados. O SAD é composto, principalmente, por três conversores analógicos-digitais (ADCs) e dois votadores. A técnica usada é a Redundância Modular Tripla (Triple Modul
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Djedidi, Oussama. "Modélisation incrémentale des processeurs embarqués pour l'estimation des caractéristiques et le diagnostic." Electronic Thesis or Diss., Aix-Marseille, 2019. http://www.theses.fr/2019AIXM0639.

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Les systèmes-sur-puce (Systems on Chip, SoC) sont de plus en plus embarqués dans des systèmes à risque comme les systèmes aéronautiques et les équipements de production d’énergie. Cette évolution technologique permet un gain de temps et de performance, mais présente des limites en termes de fiabilité et de sécurité. Ainsi, le développement d’outils de surveillance et de diagnostic des systèmes électroniques embarqués, en particuliers les SoC, est devenu l’un des verrous scientifiques à lever pour assurer une large utilisation de ces systèmes dans les équipements à risque en toute sécurité. Ce
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Перепелицин, Артем Євгенович. "Методи і засоби розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем". Thesis, Національний аерокосмічний університет ім. М. Є. Жуковського "Харківський авіаційний інститут", 2018. http://repository.kpi.kharkov.ua/handle/KhPI-Press/38557.

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Дисертація на здобуття наукового ступеня кандидата технічних наук (доктора філософії) за спеціальністю 05.13.05 "Комп'ютерні системи та компоненти". – Національний технічний університет "Харківський політехнічний інститут", Харків, 2018 р. Дисертаційна робота присвячена розв'язанню важливої науково-технічної задачі, яка полягає в розробленні методів і засобів створення мультипараметризовних проектів програмованої логіки для вбудованих систем. Метою роботи є скорочення кількості необхідних ресурсів, підвищення продуктивності або підвищення надійності вбудованих систем на програмовної логіці з
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Перепелицин, Артем Євгенович. "Методи і засоби розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем". Thesis, Національний технічний університет "Харківський політехнічний інститут", 2018. http://repository.kpi.kharkov.ua/handle/KhPI-Press/38548.

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Дисертація на здобуття наукового ступеня кандидата технічних наук (доктора філософії) за спеціальністю 05.13.05 "Комп'ютерні системи та компоненти". – Національний технічний університет "Харківський політехнічний інститут", Харків, 2018 р. Дисертаційна робота присвячена розв'язанню важливої науково-технічної задачі, яка полягає в розробленні методів і засобів створення мультипараметризовних проектів програмованої логіки для вбудованих систем. Метою роботи є скорочення кількості необхідних ресурсів, підвищення продуктивності або підвищення надійності вбудованих систем на програмовної логіці з
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Vasudevan, Siddarth. "Design and Development of a CubeSat Hardware Architecture with COTS MPSoC using Radiation Mitigation Techniques." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-285577.

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CubeSat missions needs components that are tolerant against the radiation in space. The hardware components must be reliable, and it must not compromise the functionality on-board during the mission. At the same time, the cost of hardware and its development should not be high. Hence, this thesis discusses the design and development of a CubeSat architecture using a Commercial Off-The- Shelf (COTS) Multi-Processor System on Chip (MPSoC). The architecture employs an affordable Rad-Hard Micro-Controller Unit as a Supervisor for the MPSoC. Also, it uses several radiation mitigation techniques suc
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Hsun-Chieh, Yu. "Is More Redundancy Better For On-Chip Bus Encoding." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611322913.

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Yu, Hsun-Chieh, and 游訓傑. "Is More Redundancy Better For On-Chip Bus Encoding." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/75609640278846016691.

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碩士<br>元智大學<br>資訊工程學系<br>93<br>Due to the presence of significant capacitive coupling between two adjacent lines in deep submicron process technologies, many bus encoding methods have been proposed to reduce self-transition activities, coupling-transition activities, or worst-case crosstalk delay. However these methods were shown not viable for energy reduction based on same wire-pitch assumption. In this thesis, we revisit this issue not only from the energy but also from the delay and codec overhead perspectives. We focus on the methods employing many redundant lines for eliminating crosstalk
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Moriam, Sadia. "On Fault Resilient Network-on-Chip for Many Core Systems." Doctoral thesis, 2018. https://tud.qucosa.de/id/qucosa%3A34064.

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Rapid scaling of transistor gate sizes has increased the density of on-chip integration and paved the way for heterogeneous many-core systems-on-chip, significantly improving the speed of on-chip processing. The design of the interconnection network of these complex systems is a challenging one and the network-on-chip (NoC) is now the accepted scalable and bandwidth efficient interconnect for multi-processor systems on-chip (MPSoCs). However, the performance enhancements of technology scaling come at the cost of reliability as on-chip components particularly the network-on-chip become increasi
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Book chapters on the topic "On-chip redundancy"

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Ding, Sophia. "Secure Payment." In Trends in Data Protection and Encryption Technologies. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-33386-6_32.

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AbstractSecure payment is an essential element of digital commerce in a world where cash is becoming redundant, credit cards are becoming less and less critical, and mobile devices are becoming means of payment. Therefore, it must be considered through the lens of various payment methods: Credit cards have been around since the 1950s, but the introduction of chip technology and contactless payment raises new challenges for the security of payments. Commercial payment service providers, such as credit card issuers or infrastructure operators, typically implement secure payment. Additionally, th
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Salehi, Mohammad, Florian Kriebel, Semeen Rehman, and Muhammad Shafique. "Power-Aware Fault-Tolerance for Embedded Systems." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_24.

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AbstractPower-constrained fault-tolerance has emerged as a key challenge in the deep sub-micron technology. Multi-/many-core chips can support different hardening modes considering variants of redundant multithreading (RMT). In dark silicon chips, the maximum number of cores that can simultaneously be powered-on (at the full performance level) is constrained by the thermal design power (TDP). The rest of the cores have to be power-gated (i.e., stay “dark”), or the cores have to operate at a lower performance level. It has been predicted that about 25–50% of a many-core chip can potentially be
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Hahn, Eike, Dominik Kalinowski, Waldemar Mueller, Mohamed Abdelawwad, and Josef Boercsoek. "RISC-V Based Safety System-on-Chip with Hardware Comparator." In Proceedings of CECNet 2021. IOS Press, 2021. http://dx.doi.org/10.3233/faia210423.

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In this paper, a Safety System-on-Chip based on the open-source RISC-V processor SweRV EH1 from Western Digital is presented. A hardware comparator concept is followed. The SSoC is implemented on a Xilinx FPGA system and extended with standard peripherals from the Xilinx IP library and from Cobham Gaisler, so that the overall system has an Ethernet interface in addition to GPIO and UART. The goal is to create a complete redundancy approach with a hardware fault tolerance of nearly 1 from input to output based on the freely available RISC-V instruction set and prove its feasibility.
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Guang, Liang, Juha Plosila, and Hannu Tenhunen. "Self-Adaptive SoCs for Dependability." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2014. http://dx.doi.org/10.4018/978-1-4666-6034-2.ch001.

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Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI
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Venkatesha, Shashikiran, and Ranjani Parthasarathi. "Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core Systems." In Fault Tolerance [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.102823.

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Billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation, thermal dissipation, occurrence of faults in the circuits, and reliability issues. Existing approaches explore the usage of redundancy-based solutions for fault tolerance at core level, thread level, micro-architectural level, and software level. Core-level techniques improve the lifetime reliability of multi-core systems with asymmetric cores (large and small cores), which have gained momentum and focus among a large number of researchers. Based on the above
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Conference papers on the topic "On-chip redundancy"

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Saikawa, Yamato, and Yoichi Tomioka. "Approximated Triple Modular Redundancy of Convolutional Neural Networks Based on Residual Quantization." In 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2024. https://doi.org/10.1109/mcsoc64144.2024.00057.

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Heyrman, Kris, and Peter Veelaert. "Useful-state encoding: Network control with minimal redundancy." In 2010 International Symposium on System-on-Chip - SOC. IEEE, 2010. http://dx.doi.org/10.1109/issoc.2010.5625552.

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Jung, Jongpil, Kyungsu Kang, Jae-Jin Lee, Youngjun Yoon, and Chong-Min Kyung. "Cost-effective TSV redundancy configuration." In 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). IEEE, 2012. http://dx.doi.org/10.1109/vlsi-soc.2012.6379042.

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Jung, Jongpil, Kyungsu Kang, Jae-Jin Lee, Youngjun Yoon, and Chong-Min Kyung. "Cost-effective TSV redundancy configuration." In 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). IEEE, 2012. http://dx.doi.org/10.1109/vlsi-soc.2012.7332113.

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Miedema, Lukas, Benjamin Rouxel, and Clemens Grelck. "Task-level Redundancy vs Instruction-level Redundancy against Single Event Upsets in Real-time DAG scheduling." In 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2021. http://dx.doi.org/10.1109/mcsoc51149.2021.00062.

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Sim, Mong Tee, and Yanyan Zhuang. "A SpaceWire PHY with Double Data Rate and Fallback Redundancy." In 2020 IEEE 33rd International System-on-Chip Conference (SOCC). IEEE, 2020. http://dx.doi.org/10.1109/socc49529.2020.9524763.

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Bhattacharya, K., S. Kim, and N. Ranganathan. "Improving the reliability of on-chip L2 cache using redundancy." In 2007 25th International Conference on Computer Design ICCD 2007. IEEE, 2007. http://dx.doi.org/10.1109/iccd.2007.4601906.

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Wang, Shuo, and Lei Wang. "Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design." In 2006 IEEE/ACM International Conference on Computer Aided Design. IEEE, 2006. http://dx.doi.org/10.1109/iccad.2006.320170.

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Wang, Shuo, and Lei Wang. "Exploiting soft redundancy for error-resilient on-chip memory design." In the 2006 IEEE/ACM international conference. ACM Press, 2006. http://dx.doi.org/10.1145/1233501.1233610.

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Oszwald, Florian, Philipp Obergfell, Matthias Traub, and Juergen Becker. "Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration." In 2019 32nd IEEE International System-on-Chip Conference (SOCC). IEEE, 2019. http://dx.doi.org/10.1109/socc46988.2019.1570547977.

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