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Journal articles on the topic 'On-chip redundancy'

Author: Grafiati

Published: 30 May 2022

Last updated: 31 July 2025

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1

Rozanov, V. V., and E. A. Suvorova. "VLSI AND SYSTEM-ON-CHIP REDUNDANT COMPONENTS SYNTHESIS." Issues of radio electronics, no. 8 (August 20, 2018): 33–39. http://dx.doi.org/10.21778/2218-5453-2018-8-33-39.

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Redundancy - mostly used method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault tolerance. From Application Specified Integrated Circuit (ASIC) design point of view redundancy means area and power increasing. On early design stages, it is necessary to see the correlation between the components hardware description and its synthesized equivale

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2

Zhou, Xiaofeng, Lu Liu, and Zhangming Zhu. "A Fault-Tolerant Deflection Routing for Network-on-Chip." Journal of Circuits, Systems and Computers 26, no. 03 (2016): 1750037. http://dx.doi.org/10.1142/s0218126617500372.

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Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performa

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Li, Ran, Rui Ding, Zi Jian Min, and Hui Mei Yuan. "Design of Redundant Parallel Power Supply Based on Integrated DC/DC Modules." Applied Mechanics and Materials 229-231 (November 2012): 1568–71. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1568.

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Taking into account the efficiency, cost-effectiveness and reliability of power supply, redundant parallel power supply controlled by microcontroller could be a good solution for us. This paper analyzes principles and traits of parallel current sharing structure. Then a design of redundancy parallel current sharing structure is introduced, which is based on integrated buck chip LM2678 and microcontroller MSP430. The design has good fault-tolerant ability, and its output voltage can be adjusted easily. The capability and feasibility of this design has been verified by the simulation and experim

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Yu, Qiaoyan, Meilin Zhang, and Paul Ampadu. "Addressing network-on-chip router transient errors with inherent information redundancy." ACM Transactions on Embedded Computing Systems 12, no. 4 (2013): 1–21. http://dx.doi.org/10.1145/2485984.2485993.

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Yu, Anbo, Chenyu Wang, Xiaoqiang Guo, Zheng Li, Chunjiang Zhang, and Josep M. Guerrero. "New Rotor Position Redundancy Decoding Method Based on Resolver Decoder." Micromachines 13, no. 6 (2022): 903. http://dx.doi.org/10.3390/mi13060903.

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In view of the frequent safety problems of electric vehicles, the research on accurately obtaining the rotor position of the motor through the resolver is an important means to improve the functional safety of the system. The commonly used resolver decoding method involves the resolver decoding chip method and software decoding method, but few studies integrate the two decoding methods. A single method of motor rotor position acquisition cannot meet the requirements of system functional safety. To fill this gap, this paper proposes a method to simultaneously integrate hardware decoding and sof

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Cai, Bai-gen, Cheng-ming Jin, Lian-chuan Ma, Yuan Cao, and Hideo Nakamura. "Analysis on the application of on-chip redundancy in the safety-critical system." IEICE Electronics Express 11, no. 9 (2014): 20140153. http://dx.doi.org/10.1587/elex.11.20140153.

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Cao, Ruihu, Niansong Mei, and Qian Lian. "Method for Improving the Reliability of SRAM-Based PUF Using Convolution Operation." Electronics 11, no. 21 (2022): 3493. http://dx.doi.org/10.3390/electronics11213493.

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This paper introduces a novel and efficient physical unclonable function (PUF) extraction method for SRAM. The proposed one-layer convolution scheme is based on a convolution operation, which significantly enhances the reliability of the PUF. To further reduce the hardware resources, a lightweight solution is presented based on a one-layer convolution scheme at the cost of a higher redundancy coefficient and a larger range for the inter-chip Hamming distance (HD). Both the above schemes only use certain hardware resources in the initial stage and the hardware resources are automatically releas

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UPADHYAYA, SHAMBHU J., and I.-SHYAN HWANG. "DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS." International Journal of Reliability, Quality and Safety Engineering 02, no. 04 (1995): 419–29. http://dx.doi.org/10.1142/s0218539395000290.

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This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spar

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Mohammed, Hala, Wameedh Flayyih, and Fakhrul Rokhani. "Tolerating Permanent Faults in the Input Port of the Network on Chip Router." Journal of Low Power Electronics and Applications 9, no. 1 (2019): 11. http://dx.doi.org/10.3390/jlpea9010011.

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Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses

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Sun, H., Q. Sun, S. Biereigel, et al. "A radiation tolerant clock generator for the CMS endcap timing layer readout chip." Journal of Instrumentation 17, no. 03 (2022): C03038. http://dx.doi.org/10.1088/1748-0221/17/03/c03038.

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Abstract We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizi

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Mach, Ján, Lukáš Kohútka, and Pavel Čičák. "On-Chip Bus Protection against Soft Errors." Electronics 12, no. 22 (2023): 4706. http://dx.doi.org/10.3390/electronics12224706.

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The increasing performance demands for processors leveraged in mission and safety-critical applications mean that the processors are implemented in smaller fabrication technologies, allowing a denser integration and higher operational frequency. Besides that, these applications require a high dependability and robustness level. The properties that provide higher performance also lead to higher susceptibility to transient faults caused by radiation. Many approaches exist for protecting individual processor cores, but the protection of interconnect buses is studied less. This paper describes the

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Nasimi, Fahimeh, Mohammad Reza Khayyambashi, and Naser Movahhedinia. "Redundancy cancellation of compressed measurements by QRS complex alignment." PLOS ONE 17, no. 2 (2022): e0262219. http://dx.doi.org/10.1371/journal.pone.0262219.

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The demand for long-term continuous care has led healthcare experts to focus on development challenges. On-chip energy consumption as a key challenge can be addressed by data reduction techniques. In this paper, the pseudo periodic nature of ElectroCardioGram(ECG) signals has been used to completely remove redundancy from frames. Compressing aligned QRS complexes by Compressed Sensing (CS), result in highly redundant measurement vectors. By removing this redundancy, a high cluster of near zero samples is gained. The efficiency of the proposed algorithm is assessed using the standard MIT-BIH da

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Hernandez Herrera, H. D., M. Bregant, B. Sanchez, and W. Van Noije. "Onchip digital calibrated 2 mW 12-bit 25 MS/s SAR ADC with reduced input capacitance." Journal of Instrumentation 17, no. 04 (2022): C04013. http://dx.doi.org/10.1088/1748-0221/17/04/c04013.

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Abstract We present a 12-bits asynchronous SAR ADC with a low complexity digital on-chip calibration and just 2 pF of total array capacitance. The ADC architecture utilizes a redundant weighting switching of 2 fF MOM capacitors consuming 14 clock-cycles to complete the conversion. Taking advantage of redundancy, the weights of the MSB capacitors are estimated using the LSB array, thus it is possible to digitally compensate for the mismatch non-linearity directly over the ADC output. The circuit consumes 2 mW at 25 MS/s on a core area of 300 μm × 500 μm in 180 nm CMOS technology. ENOB improveme

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Zhou, Zi Guan, Xiao Shan Pan, Shu Gang Yin, Wei Li Ren, Sheng Bo Sun, and Yang Wang. "Research on Variable-Frequency-Point Variable-Bandwidth Wireless Broadband Radio Frequency Chip and its Application in the Smart Grid." Advanced Materials Research 347-353 (October 2011): 3107–15. http://dx.doi.org/10.4028/www.scientific.net/amr.347-353.3107.

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With the development of the smart grid, residential electricity services have a higher bandwidth and frequency requirement to the power system communication , the existing power 230MHz narrow-band data transmission communication has been unable to meet the needs of the two-way interaction between the users and the smart grid. In terms of current communication technology in the power system, this paper introduces a wireless broadband radio frequency chip ,which supports 100MHz to 1.2GHz frequency range, and 5KHz to 2MHz tunable bandwidth.With the chip embedded in intelligent electricity interac

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15

Menouni, Mohsine, Pierre Barrillon, Leyre Flores, et al. "Single event effects testing of the RD53B chip." Journal of Physics: Conference Series 2374, no. 1 (2022): 012084. http://dx.doi.org/10.1088/1742-6596/2374/1/012084.

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The RD53 collaboration has been working since 2014 on the development of pixel chips for the CMS and ATLAS Phase 2 tracker upgrade. This work has recently led to the development of the RD53B full-scale readout chip which is using the 65nm CMOS process and containing 153600 pixels of 50 × 50 μm 2 The RD53B chip is designed to be robust against the Single Event Effects (SEE), allowing such a complex chip to operate reliably in the hostile environment of the HL-LHC. Different SEE mitigation techniques based on the Triple Modular Redundancy (TMR) have been adopted for the critical information in t

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Savva, Andreas G., Theocharis Theocharides, and Chrysostomos Nicopoulos. "Robustness of Artificial Neural Networks Based on Weight Alterations Used for Prediction Purposes." Algorithms 16, no. 7 (2023): 322. http://dx.doi.org/10.3390/a16070322.

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Nowadays, due to their excellent prediction capabilities, the use of artificial neural networks (ANNs) in software has significantly increased. One of the most important aspects of ANNs is robustness. Most existing studies on robustness focus on adversarial attacks and complete redundancy schemes in ANNs. Such redundancy methods for robustness are not easily applicable in modern embedded systems. This work presents a study, based on simulations, about the robustness of ANNs used for prediction purposes based on weight alterations. We devise a method to increase the robustness of ANNs directly

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17

Fei, Ji You, Hua Li, and Bin Gao. "Based on the Single Chip Microcomputer Atmega168 Robot Control System Design." Applied Mechanics and Materials 341-342 (July 2013): 700–703. http://dx.doi.org/10.4028/www.scientific.net/amm.341-342.700.

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based on the single chip microcomputer atmega168 robot control system design This paper introduces using micro controller, many sensors, such as ultrasonic distance measuring sensor, infrared range sensor, infrared obstacle avoidance sensor, and also using motor driving module and dc motor design a robot which can operate independently, The robot can detect its own attitude, obstacles, competition venues edge automatically, then according to signal which the sensor feedback to micro controller controlling the motor produce pushing or avoid action. In the design of the robot, we using the senso

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18

Shafique, Muhammad Akmal, Naveed Khan Baloch, Muhammad Iram Baig, Fawad Hussain, Yousaf Bin Zikria, and Sung Won Kim. "NoCGuard: A Reliable Network-on-Chip Router Architecture." Electronics 9, no. 2 (2020): 342. http://dx.doi.org/10.3390/electronics9020342.

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Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost faul

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19

Najeeb, K., Vishal Gupta, V. Kamakoti, and Madhu Mutyam. "Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses." Journal of Low Power Electronics 2, no. 3 (2006): 425–36. http://dx.doi.org/10.1166/jolpe.2006.099.

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20

Arya, Namita, and Amit Prakash Singh. "Comparative Analysis of Time and Physical Redundancy Techniques for Fault Detection." Indonesian Journal of Electrical Engineering and Computer Science 6, no. 1 (2017): 66. http://dx.doi.org/10.11591/ijeecs.v6.i1.pp66-71.

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<p>The integration level in today’s world is continuously increasing in VLSI chips. VLSI circuit verification is a major challenge in these days. Integration capacity of VLSI circuits mimics the testing complexity of circuits. There is a significant chunk of the testing cost with respect to the whole fabrication prices. Hence it is important to cut down the verification cost. Time required during testing is a main factor for the cost of a chip. This time is directly proportional to the number of testing in the circuitry. So the test set should be very small. There is one way to generate

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21

Gonzalez, Carlos J., Diego Machado, Rafael G. Vaz, et al. "Testing a Fault Tolerant Mixed-Signal Design Under TID and Heavy Ions." Journal of Integrated Circuits and Systems 16, no. 3 (2021): 1–11. http://dx.doi.org/10.29292/jics.v16i3.567.

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This work presents results of three distinct radiation tests performed upon a fault-tolerant data acquisition system comprising a design diversity redundancy technique. The first and second experiments are Total Ionizing Dose (TID) essays, comprising gamma and X-ray irradiations. The last experiment considers single event effects, in which two heavy ion irradiation campaigns are carried out. The case study system comprises three analog-to-digital converters and two software-based voters, besides additional software and hardware resources used for controlling, monitoring and memory management.

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22

Xie, Yu, Yizhuang Xie, Bingyi Li, and He Chen. "Advancements in Spaceborne Synthetic Aperture Radar Imaging with System-on-Chip Architecture and System Fault-Tolerant Technology." Remote Sensing 15, no. 19 (2023): 4739. http://dx.doi.org/10.3390/rs15194739.

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With the continuous development of satellite payload and system-on-chip (SoC) technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems play a crucial role in various defense and civilian domains, including Earth remote sensing, military reconnaissance, disaster mitigation, and resource exploration. However, designing high-performance and high-reliability SAR imaging systems that operate in harsh environmental conditions while adhering to strict size, weight, and power consumption constraints remains a significant challenge. In this paper, we introduce a spaceborne SAR im

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Rashid, Muhammad, Naveed Khan Baloch, Muhammad Akmal Shafique, et al. "Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things." Sensors 20, no. 18 (2020): 5355. http://dx.doi.org/10.3390/s20185355.

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Network-on-chip (NoC) architectures have become a popular communication platform for heterogeneous computing systems owing to their scalability and high performance. Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. In the proposed scheme, the input port utilizes a bypass path, virtual channel (V

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Omar, Hamza, and Omer Khan. "PRISM." ACM Transactions on Architecture and Code Optimization 18, no. 3 (2021): 1–25. http://dx.doi.org/10.1145/3450523.

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Multicores increasingly deploy safety-critical parallel applications that demand resiliency against soft-errors to satisfy the safety standards. However, protection against these errors is challenging due to complex communication and data access protocols that aggressively share on-chip hardware resources. Research has explored various temporal and spatial redundancy-based resiliency schemes that provide multicores with high soft-error coverage. However, redundant execution incurs performance overheads due to interference effects induced by aggressive resource sharing. Moreover, these schemes

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Chen, Shih-Lun, He-Sheng Chou, Shih-Yao Ke, et al. "VLSI Design Based on Block Truncation Coding for Real-Time Color Image Compression for IoT." Sensors 23, no. 3 (2023): 1573. http://dx.doi.org/10.3390/s23031573.

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It has always been a major issue for a hospital to acquire real-time information about a patient in emergency situations. Because of this, this research presents a novel high-compression-ratio and real-time-process image compression very-large-scale integration (VLSI) design for image sensors in the Internet of Things (IoT). The design consists of a YEF transform, color sampling, block truncation coding (BTC), threshold optimization, sub-sampling, prediction, quantization, and Golomb–Rice coding. By using machine learning, different BTC parameters are trained to achieve the optimal solution gi

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Das, Abhishek, and Nur A. Touba. "A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote." Electronics 9, no. 5 (2020): 709. http://dx.doi.org/10.3390/electronics9050709.

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Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on

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Park, Daejin. "Low-Power Code Memory Integrity Verification Using Background Cyclic Redundancy Check Calculator Based on Binary Code Inversion Method." Journal of Circuits, Systems and Computers 25, no. 07 (2016): 1650068. http://dx.doi.org/10.1142/s0218126616500687.

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The integrity verification of on-chip flash memory data as code memory is becoming important in microcontroller-based applications such as automotive systems. On-the-fly memory fail-detection requires a fast detection method in the seamless background mode without any interruption of CPU operation and low-power flash access hardware to provide safety-conscious execution of the user-programmed firmware during system operations. In this paper, newly-designed read-path architecture based on the binary inversion techniques is proposed for on-chip flash-embedded microcontrollers. The proposed binar

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Nguyen, Hai T., Giao N. Pham, Anh N. Bui, Binh A. Nguyen, Ngoc T. Le, and Hanh T. Pham. "Linear Feedback Shift Register and its Applications in Digital System Design." International Journal of Emerging Technology and Advanced Engineering 11, no. 11 (2021): 204–8. http://dx.doi.org/10.46338/ijetae1121_24.

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In digital system design, the Linear Feedback Shift Register (LFSR) is the queen of logic functions, and the design engineers can use LFSR in both hardware (HW) or software (SW) implementation. In this paper, LFSR will be discussed in its HW implementation via Hardware description language. In addition, the application of LFSR in of pseudorandom number generator (PRNG), direct sequence spread spectrum (DSSS), cyclic redundancy check (CRC) is also given. Keywords-- Digital system design, System on chip, ASIC digital design, Linear feedback shift register

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Melo, Douglas R., Cesar A. Zeferino, Luigi Dilillo, and Eduardo A. Bezerra. "Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design." Sensors 19, no. 24 (2019): 5416. http://dx.doi.org/10.3390/s19245416.

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Reducing component size and increasing the operating frequency of integrated circuits makes the Systems-on-Chip (SoCs) more susceptible to faults. Faults can cause errors, and errors can be propagated and lead to a system failure. SoCs employing many cores rely on a Network-on-Chip (NoC) as the interconnect architecture. In this context, this study explores alternatives to implement the flow regulation, routing, and arbitration controllers of an NoC router aiming at minimizing error propagation. For this purpose, a router with Finite-State Machine (FSM)-based controllers was developed targetin

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Kurata, Kazuhiko, Luca Giorgi, Fabio Cavaliere, et al. "Silicon Photonic Micro-Transceivers for Beyond 5G Environments." Applied Sciences 11, no. 22 (2021): 10955. http://dx.doi.org/10.3390/app112210955.

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Here, we report on the design and performance of a silicon photonic micro-transceiver required to operate in 5G and 6G environments at high ambient temperatures above 105 °C. The four-channel “IOCore” micro-transceiver incorporates a 1310 nm quantum dot laser system and operates at a data rate of 25 Gbps and higher. The 5 × 5 mm micro-transceiver chip benefits from a multimode coupling interface for low-cost assembly and robust connectivity at high temperatures as well as an optical redundancy scheme, which increases reliability by over an order of magnitude.

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Paul, Priyanka, Sanjay Joshi, Ran Tian, Rubens Diogo Junior, Manohar Chakrabarti, and Sharyn E. Perry. "The MADS-domain factor AGAMOUS-Like18 promotes somatic embryogenesis." Plant Physiology 188, no. 3 (2021): 1617–31. http://dx.doi.org/10.1093/plphys/kiab553.

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Abstract AGAMOUS-Like 18 (AGL18) is a MADS domain transcription factor (TF) that is structurally related to AGL15. Here we show that, like AGL15, AGL18 can promote somatic embryogenesis (SE) when ectopically expressed in Arabidopsis (Arabidopsis thaliana). Based on loss-of-function mutants, AGL15 and AGL18 have redundant functions in developmental processes such as SE. To understand the nature of this redundancy, we undertook a number of studies to look at the interaction between these factors. We studied the genome-wide direct targets of AGL18 to characterize its roles at the molecular level

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Li, Shuai, Kuangyuan Sun, Yukui Luo, Nandakishor Yadav, and Ken Choi. "Novel CNN-Based AP2D-Net Accelerator: An Area and Power Efficient Solution for Real-Time Applications on Mobile FPGA." Electronics 9, no. 5 (2020): 832. http://dx.doi.org/10.3390/electronics9050832.

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Standard convolutional neural networks (CNNs) have large amounts of data redundancy, and the same accuracy can be obtained even in lower bit weights instead of floating-point representation. Most CNNs have to be developed and executed on high-end GPU-based workstations, for which it is hard to transplant the existing implementations onto portable edge FPGAs because of the limitation of on-chip block memory storage size and battery capacity. In this paper, we present adaptive pointwise convolution and 2D convolution joint network (AP2D-Net), an ultra-low power and relatively high throughput sys

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Youplao, Phichai, Nithiroth Pornsuwancharoen, and Preecha P. Yupapin. "High capacity terahertz frequency combs generated by small scale optical mesh network." Journal of Nonlinear Optical Physics & Materials 23, no. 01 (2014): 1450003. http://dx.doi.org/10.1142/s0218863514500039.

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A novel design of mesh ring resonator system is proposed and simulated to obtain the multi frequency comb bands, in which the frequency band less than 10 GHz (about 0.084 nm) of comb lines spacing with commercialized ring parameters is achieved. The proposed system is used to enhance the capacity of optical frequency comb for redundancy networks against the network element failures and to increase the survivability of the communication systems. The dependence of the mesh ring transmission characteristics with coupling coefficients of directional couplers is analyzed and studied. In application

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Xu, Jia, Han Pu, and Dong Wang. "Sparse Convolution FPGA Accelerator Based on Multi-Bank Hash Selection." Micromachines 16, no. 1 (2024): 22. https://doi.org/10.3390/mi16010022.

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Reconfigurable processor-based acceleration of deep convolutional neural network (DCNN) algorithms has emerged as a widely adopted technique, with particular attention on sparse neural network acceleration as an active research area. However, many computing devices that claim high computational power still struggle to execute neural network algorithms with optimal efficiency, low latency, and minimal power consumption. Consequently, there remains significant potential for further exploration into improving the efficiency, latency, and power consumption of neural network accelerators across div

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KANEKAWA, Nobuyasu. "Potential of Fault-Detection Coverage by means of On-Chip Redundancy - IEC61508: Are There Royal Roads to SIL 4?" IEICE Transactions on Information and Systems E96.D, no. 9 (2013): 1907–13. http://dx.doi.org/10.1587/transinf.e96.d.1907.

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Alnatheer, Suleman, and Mohammed Altaf Ahmed. "Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC." Micromachines 12, no. 7 (2021): 811. http://dx.doi.org/10.3390/mi12070811.

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The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit

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Hosseini, Fateme S., Fanruo Meng, Chengmo Yang, Wujie Wen, and Rosario Cammarota. "Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation." ACM Transactions on Embedded Computing Systems 20, no. 5s (2021): 1–21. http://dx.doi.org/10.1145/3477016.

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Hardware accelerators are essential to the accommodation of ever-increasing Deep Neural Network (DNN) workloads on the resource-constrained embedded devices. While accelerators facilitate fast and energy-efficient DNN operations, their accuracy is threatened by faults in their on-chip and off-chip memories, where millions of DNN weights are held. The use of emerging Non-Volatile Memories (NVM) further exposes DNN accelerators to a non-negligible rate of permanent defects due to immature fabrication, limited endurance, and aging. To tolerate defects in NVM-based DNN accelerators, previous work

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Zhang, Yi, Lufeng Qiao, Lin Hu, Xin Xu, and Qinghua Chen. "Cuckoo Bloom Hybrid Filter: Algorithm and Hardware Architecture for High Performance Satellite Internet Protocol Route Lookup." Applied Sciences 13, no. 18 (2023): 10360. http://dx.doi.org/10.3390/app131810360.

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The next-generation satellite Internet Protocol (IP) router is required to achieve tens of millions of route lookups per second, since satellite Internet services based on low Earth orbit (LEO) constellations have become a reality. Due to the limitation of hardware resources on satellites and the high reliability requirements for equipment, a new satellite IP route lookup architecture is proposed in this paper. The proposed architecture uses a Bloom and cuckoo filter-based structure called cuckoo Bloom hybrid filter (CBHF), which guarantees only one off-chip memory access per lookup, to accele

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Ji, Ling. "Software Anti-Interference Design of SCM Control System." Applied Mechanics and Materials 644-650 (September 2014): 667–69. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.667.

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SCM control system requires high reliability and security, the entire control system to operate safely and reliably only when a strong anti-interference capability. In switch input and output, the use of the instruction redundancy methods to achieve the switch signal input and output filtering; in data collection, based on the hardware anti-interference taken arithmetic average filtering method, in order to strengthen its anti-jamming capability. In the system status monitoring, watchdog feature is enabled with the MSP430F449 microcontroller, when the watchdog timer overflows, the system autom

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Huang, Feng Ying, Jun Wang, Yu Sen Xu, and Ji Wei Huang. "A Novel Design of PIE Decoding with Multiple CRC Circuit for RFID Tag." Advanced Materials Research 816-817 (September 2013): 957–61. http://dx.doi.org/10.4028/www.scientific.net/amr.816-817.957.

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This paper proposes a new synchronized serial-parallel CRC(Cycle Redundancy Check) with PIE(Pulse Interval Encoding) decoding circuit for the UHF(Ultra-High Frequency) RFID(Radio Frequency Identification), which is based on the ISO/IEC 18000-6C standards protocol. The parallel algorithm of CRC circuit is derived, and the serial or parallel CRC circuit on RFID tag chip is evaluated in this paper. Finally, the designed circuit is simulated and analyzed on the FPGA platform. Simulation results show that the proposed circuit meets the communication requirement of the protocol and addresses the pro

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Barkalov, Alexandr, Larysa Titarenko, Oleksandr Golovin, and Oleksandr Matvienko. "Address Translation in a Compositional Microprogram Control Unit." Cybernetics and Computer Technologies, no. 2 (June 6, 2025): 88–100. https://doi.org/10.34229/2707-451x.25.2.8.

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Introduction. Digital systems consist of combinational and sequential blocks. The most important sequential blocks include control units. Control unit circuits are not typical library components of CAD systems. Due to it, the designing a control unit circuit is a more labor-intensive process than implementing systems with such common blocks as registers, counters, arithmetic and logic blocks. The purpose of the article. When implementing digital systems, problems arise in optimizing their characteristics. This paper considers the problem of reducing hardware costs in the circuits of compositio

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Irfan, Kainat, and Mujeeb Ur Rehman. "Optimized Task Deployment in Dynamic Voltage and Frequency Scaling-Enabled Network-on-Chip Systems: Enhancing Energy Efficiency and Real-Time Responsiveness." Spectrum of Engineering and Management Sciences 2, no. 1 (2024): 214–22. https://doi.org/10.31181/sems21202426i.

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In modern multi-design computing systems, which employ dynamic voltage and frequency scaling (DVFS) and network-on-chip (NoC) communications, the optimization of task deployment is precarious for enhancing overall system performance. It introduces a comprehensive methodology that integrates task allocation, scheduling, frequency management, redundancy handling, and diverse data routing approaches. The aim is to optimize energy intake, real-time responsiveness, and system heftiness. The system design features a primary processing element associated with three slave computing units (CUs) within

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Braga, Davide, Grace Cummings, Cristinel Gingu, et al. "First test results of the HGCAL concentrator ASICs: ECON-T and ECON-D." Journal of Instrumentation 19, no. 03 (2024): C03050. http://dx.doi.org/10.1088/1748-0221/19/03/c03050.

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Abstract With over 6 million channels, the High Granularity Calorimeter for the CMS HL-LHC upgrade presents a unique data transmission challenge. The ECON ASICs provide a critical stage of on-detector data compression and selection for the trigger path (ECON-T) and data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65 nm CMOS, are radiation tolerant up to 200 Mrad and require low power consumption: < 2.5 mW/sensor-channel per chip. We report on the first functionality and radiation tests for the ECON-D-P1 full-functionality prototype. We present a comparison of single eve

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van Roermund, Arthur H. M. "Shifting the Frontiers of Analog and Mixed-Signal Electronics." Advances in Electronics 2014 (December 16, 2014): 1–16. http://dx.doi.org/10.1155/2014/590970.

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Nowadays, analog and mixed-signal (AMS) IC designs, mainly found in the frontends of large ICs, are highly dedicated, complex, and costly. They form a bottleneck in the communication with the outside world, determine an upper bound in quality, yield, and flexibility for the IC, and require a significant part of the power dissipation. Operating very close to physical limits, serious boundaries are faced. This paper relates, from a high-level point of view, these boundaries to the Shannon channel capacity and shows how the AMS circuitry forms a matching link in transforming the external analog s

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Ahmed, Mohammed Altaf, and Suleman Alnatheer. "Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM." Micromachines 13, no. 6 (2022): 971. http://dx.doi.org/10.3390/mi13060971.

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Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yie

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TA, Ashish. "NEURALINK: A Revolutionary Brain-Machine Interface for Human- Machine Symbiosis." International Journal for Research in Applied Science and Engineering Technology 13, no. 3 (2025): 3357–67. https://doi.org/10.22214/ijraset.2025.68062.

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As technology advances, Artificial Intelligence (AI) is increasingly integrated into daily life, raising concerns about human redundancy. This paper explores Neuralink’s efforts to merge human intelligence with AI using Brain-Machine Interface (BMI) and Neural Lace technology. Neuralink, founded by Elon Musk, envisions a future where humans achieve cognitive symbiosis with AI, mitigating fears of becoming obsolete. The paper details Neuralink's technological innovations, including the N1 chip, ultra-thin neural threads, and AI-powered robotic surgery systems. Furthermore, it addresses challeng

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Mestice, Marco, Bruno Neri, Gabriele Ciarpi, and Sergio Saponara. "Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL." Sensors 20, no. 14 (2020): 4013. http://dx.doi.org/10.3390/s20144013.

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The design of a Phase-Locked Loop (PLL) to generate the clock reference for the new Spacefibre standard is presented in this paper. Spacefibre has been recently released by the European Space Agency (ESA) and supports up to 6.25 Gbps for on-board satellite communications. Taking as a starting point a rad-hard 6.25 GHz Voltage Controlled Oscillator in 65 nm technology, this work presents the design of the key blocks for an integrated PLL: a Triple Modular Redundancy Phase/Frequency Detector, a Charge Pump, and a passive Loop Filter. The modeling activities carried out in an Advanced Design Syst

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Cheng, Xingguo, and Chaomeng Chen. "Vehicle Detection System with Statistical Functions Based on 3-Axis Anisotropic Magnetoresistive Using Wireless Communication Technology." Journal of Computational and Theoretical Nanoscience 17, no. 7 (2020): 2876–81. http://dx.doi.org/10.1166/jctn.2020.6749.

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In terms of current issues that the sensor’s output signal drifts along with the surrounding strong magnetic field by using the single or dual-axis analog anisotropic magnetoresistive (AMR) sensor in the traffic flow detection, a traffic flow detection system based on ZigBee wireless sensor network is developed and a novel approach by exercising the new digital three-axis AMR sensor to detect the traffic flow is proposed to solve these issues as mentioned above. Using Single Chip Microcomputer (SCM) control technique and utilizing wireless transmitting, an effective algorithm is designed. The

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Nourmandi-Pour, Reza. "A Programmable IEEE 1500-Compliant Wrapper for Testing of Word-Oriented Memory Cores." Journal of Circuits, Systems and Computers 27, no. 09 (2018): 1850134. http://dx.doi.org/10.1142/s0218126618501347.

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In today’s embedded technology, memories are the universal components. With the onset of the deep-submicron VLSI technology, the density and capacity of the memory are growing. However, providing a cost-effective test solution for these on-chip memories is becoming a challenging task. As memory and other processing cores have been embedded deeply in system chips, the IEEE std 1500 has been suggested to facilitate the test of these core types. Whereas up to now this standard has not presented a definite solution for testing of memory cores, in this paper, we proposed a programmable IEEE 1500-co

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Pullaiah, T., K. Manjunathachari, and B. L. Malleswari. "∆DHT-Zip: A Delta-difference Hybrid Tree Coding Scheme for End-to-end Packet Compression Framework in Network-on-Chips." International Journal of Computer Network and Information Security 17, no. 2 (2025): 19–33. https://doi.org/10.5815/ijcnis.2025.02.02.

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Due to the maximal transistor count, Multi-Processor System-on-Chip (MPSoC) delivers more performance than uniprocessor systems. Network on Chip (NoC) in MPSoC provides scalable connectivity compared to traditional bus-based interconnects. Still, NoC designs significantly impact MPSoC design as it increases power consumption and network latency. A solution to this problem is packet compression which minimizes the data redundancy within NoC packets and reduces the overall power consumption of the whole network by minimizing a data packet size. Latency and overhead of compressor and decompressor

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