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Relevant bibliographies by topics / On-Wafer electrical measurements

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Journal articles
Dissertations / Theses
Conference papers

Academic literature on the topic 'On-Wafer electrical measurements'

Author: Grafiati

Published: 31 May 2025

Last updated: 31 July 2025

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Journal articles on the topic "On-Wafer electrical measurements"

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Potts, David, Scott Hildreth, and Binod Kumar G. Nair. "Impacts of Nested Variance Components on Semiconductor Electrical Test Sampling." EDFA Technical Articles 24, no. 3 (2022): 4–10. http://dx.doi.org/10.31399/asm.edfa.2022-3.p004.

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Abstract Inline wafer electrical testing (WET) offers an early read on semiconductor manufacturing processes via measurements taken on test structures placed throughout the wafer. Interpreting the data can be challenging, however. In many cases, only a sample of the test sites are monitored in production. Complex manufacturing requirements further complicate the problem because some operations are iteratively executed within subregions across a given wafer, while others are run on the entire wafer at once, and still others are applied to wafers in batches. This results in a nested variance str

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Arscott, Steve. "On overtravel and skate in cantilever-based probes for on-wafer measurements." Journal of Micromechanics and Microengineering 32, no. 5 (2022): 057001. http://dx.doi.org/10.1088/1361-6439/ac521e.

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Abstract Due to the deformability of a microcantilever-based probe, there is an interesting and subtle interplay between the probe overtravel, the tip skate on the surface, and the ultimate tangency of the tip of the probe with the wafer surface. The relationship between these parameters is described here. The scalable model is tested using a macroscopic cantilever and found to be accurate in its predictions. In addition, to avoid potential skate-induced damage to metallisation, the idea of zero-skate using a cantilever-based probe has been introduced; minimal skate is demonstrated using a mac

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Savtchouk, Alexandre, Marshall Wilson, D. Marinskiy, B. Schrayer, C. Almeida, and Jacek Lagowski. "Recent Progress in Non-Contact Electrical Characterization for SiC and Related Compounds." Materials Science Forum 1089 (May 26, 2023): 51–56. http://dx.doi.org/10.4028/p-3bn937.

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An increasing interest in the non-contact corona charge-based electrical characterization technique, CnCV, for wide bandgap semiconductors, is justified by the reduction of cost and the reduction of testing feedback time [1]. In addition, the technique expands measurement capabilities. Regarding SiC, recent progress includes expanded dopant concentration range and dopant measurement on fresh epitaxial wafers. The latter is made possible with an ultraviolet wafer pretreatment technique [2]. The novel applications to AlGaN/GaN HEMT on insulating substrates demonstrate the benefits of a noninvasi

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Weatherspoon, M. H., and L. P. Dunleavy. "Vector Corrected On-Wafer Measurements of Noise Temperature." IEEE Transactions on Instrumentation and Measurement 54, no. 3 (2005): 1327–32. http://dx.doi.org/10.1109/tim.2005.847218.

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Lecarpentier, Gilbert, Rahul Agarwal, Wenqi Zhang, et al. "Die-to-Wafer Bonding of Thin Dies using a 2-Step Approach; High Accuracy Placement, then Gang Bonding." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (2010): 001254–81. http://dx.doi.org/10.4071/2010dpc-wa14.

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25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 10μm and 40μm. A special test structure was designed on the landing die to electrically determine the alignment accuracy after bonding - both with respect to the X-Y alignment and the rotation. Stacks were then assembled by collective hybrid bonding process. The top die is aligned and placed on the landing wafer coverer by a patterned polymer acting as a temporary alignment holder, and then the

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Wang, Yibang, Xingchang Fu, Aihua Wu, et al. "Development of gallium-arsenide-based GCPW calibration kits for on-wafer measurements in the W-band." International Journal of Microwave and Wireless Technologies 12, no. 5 (2019): 367–71. http://dx.doi.org/10.1017/s1759078719001521.

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AbstractWe present details of on-wafer-level 16-term error model calibration kits used for the characterization of W-band circuits based on a grounded coplanar waveguide (GCPW). These circuits were fabricated on a thin gallium arsenide (GaAs) substrate, and via holes, were utilized to ensure single mode propagation (i.e., eliminating the parallel-plate mode or surface mode). To ensure the accuracy of the definition for the calibration kits, multi-line thru-reflect-line (MTRL) assistant standards were also fabricated on the same wafer and measured. The same wafer also contained passive and acti

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Yu, Wan Cheng, Xiu Fang Chen, Xiao Bo Hu, and Xian Gang Xu. "Wafer-Scale Graphene on 4-Inch SiC." Materials Science Forum 858 (May 2016): 1133–36. http://dx.doi.org/10.4028/www.scientific.net/msf.858.1133.

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Wafer-scale graphene on SiC with uniform structural features was grown on semi-insulating 4 inch on-axis 4H-SiC (0001) face. Growth was carried out in a conventional physical vapor transport (PVT) growth system. Atmospheric pressure graphitization and a “face-down” orientation were account for the high uniformity of graphene. Atomic force microscopy, electrostatic force microscopy and Raman spectroscopy were used to confirm the uniformity of surface morphology and layer number. Electrical properties were also characterized by Hall measurements on 15×15mm2 samples sawed from the wafer. An avera

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Li, Xuan, Shiwei Feng, Zhihong Feng, et al. "A thermal boundary resistance measurement method based on a designed chip with the heat source separated from the temperature sensor." Applied Physics Letters 122, no. 7 (2023): 073501. http://dx.doi.org/10.1063/5.0137965.

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Measurements of thermal boundary resistance (TBR) are of great significance in the fields of electronic packaging and thermal management. In this study, a measurement method based on a designed 1 × 1 mm2 chip with a heat source separated from a temperature sensor was developed. The chip consists of a temperature sensor with nine Schottky diodes connected in series and a heat source composed of metal wires, which are separated by SiO2 to realize electrical isolation. With this chip, the TBR of samples can be extracted from transient temperature response curves of GaN on a Si wafer using the str

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Phung, Gia Ngoc, Franz Josef Schmuckle, Ralf Doerner, et al. "Influence of Microwave Probes on Calibrated On-Wafer Measurements." IEEE Transactions on Microwave Theory and Techniques 67, no. 5 (2019): 1892–900. http://dx.doi.org/10.1109/tmtt.2019.2903400.

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Vaha-Heikkila, T., M. Lahdes, M. Kantanen, and J. Tuovinen. "On-wafer noise-parameter measurements at w -band." IEEE Transactions on Microwave Theory and Techniques 51, no. 6 (2003): 1621–28. http://dx.doi.org/10.1109/tmtt.2003.812554.

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Dissertations / Theses on the topic "On-Wafer electrical measurements"

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Lee, Jun Seok. "On-Wafer Characterization of Electromagnetic Properties of Thin-Film RF Materials." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1308311479.

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Neckel, Wesling Bruno. "Fabrication, caractérisation et modélisation des transistors à effet de champ émergents." Electronic Thesis or Diss., Bordeaux, 2025. http://www.theses.fr/2025BORD0055.

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Au cours des dernières décennies, la mise à l'échelle a été utilisée pour atteindre les objectifs d'amélioration de la technologie des transistors à effet de champ (FET), en la rendant plus puissante et plus efficace. La mise à l'échelle tend à s'arrêter en raison de limites physiques, ce qui conduit à de nouvelles approches visant à accroître les fonctionnalités des transistors et des circuits. Les transistors à effet de champ à nanofils verticaux sans jonction (JL-VNWFET) conviennent à l'intégration 3D grâce à des canaux uniformément dopés qui éliminent le dopage complexe et peuvent être com

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Chen, Wei-Hsuan, and 陳蔚軒. "On-wafer 2-D electric-field-vector measurement using single-beam electro-optic probing technique." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/91189158300332752419.

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碩士<br>國立中山大學<br>光電工程研究所<br>88<br>Electro-Optic(EO) probing techniques are advancing rapidly in recent years due to their superior performance in characterization of semiconductor devices and circuits. Although the conventional systems can only monitor the amplitude distribution of electric field, some advanced EO probing techniques are able to measure not only the electric-field amplitude, but also direction of the electric field. Because valuable information can be released in such as chamfered bending transmission lines, patch antennas and wireless devices, etc., EO probing technique becomes

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Conference papers on the topic "On-Wafer electrical measurements"

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Kane, Terence. "In FAB 300mm Wafer Level Atomic Force Probe Characterization." In ISTFA 2012. ASM International, 2012. http://dx.doi.org/10.31399/asm.cp.istfa2012p0071.

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Abstract A 300mm wafer atomic force prober (AFP) has been installed into IBM’s manufacturing line to enable rapid, nondestructive electrical identification of defects. Prior to this tool many of these defects could not detected until weeks or months later. Moving failure analysis to the FAB provides a means of complementing existing FAB inspection and defect review tools as well as providing independent, non-destructive electrical measurements at an early point in the manufacturing cycle [1] Once the wafer sites are non destructively AFP characterized, the wafer is returned to its front openin

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Duraipandi, Devasena, John M. Heck, Raymond K. Yee, and Sang-Joon J. Lee. "A Finite Element Study of Geometric Modifications to Reduce Thermal Mismatch Curvature in Wafer Bonding." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-41453.

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Wafer-level packaging of RF MEMS devices offers an attractive option to reduce packaging cost significantly and ensures hermetic encapsulation of devices. Low-temperature cofired ceramic (LTCC) cap wafers are particularly favorable because they can be pre-patterned with through-wafer vias for integrated electrical contacts and high-density packaging, at a much lower cost than silicon wafers with similar features. However, thermal expansion mismatch between ceramic and silicon wafers at high bonding temperatures induces thermal stresses at the interface, resulting in wafer curvature. For exampl

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Doany, F. E., D. Grischkowsky, and C. C. Chi. "Carrier Lifetime vs. Ion-Implantation Dose in Silicon on Sapphire." In Picosecond Electronics and Optoelectronics. Optica Publishing Group, 1987. http://dx.doi.org/10.1364/peo.1987.we11.

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The generation of subpicosecond electrical pulses has recently been demonstrated using fast photoconductive switches driven by short laser pulses [1]. In these measurements electrical pulses on the order of 0.6 ps were obtained by shorting a charged transmission line fabricated on an ion-implanted silicon-on-sapphire (SOS) wafer. The major factors determining the shape and duration of these electrical pulses were the laser pulsewidths, the circuit characteristics of the photoconductive gaps and the transmission line, and the carrier lifetime of the semiconductor [2]. Since laser pulses shorter

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Tenney, Charles, Mohammad I. Albakri, Joseph Kubalak, Logan D. Sturm, Christopher B. Williams, and Pablo A. Tarazaga. "Internal Porosity Detection in Additively Manufactured Parts via Electromechanical Impedance Measurements." In ASME 2017 Conference on Smart Materials, Adaptive Structures and Intelligent Systems. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/smasis2017-3856.

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The flexibility offered by additive manufacturing (AM) technologies to fabricate complex geometries poses several challenges to non-destructive evaluation (NDE) and quality control (QC) techniques. Existing NDE and QC techniques are not optimized for AM processes, materials, or parts. Such lack of reliable means to verify and qualify AM parts is a significant barrier to further industrial adoption of AM technologies. Electromechanical impedance measurements have been recently introduced as an alternative solution to detect anomalies in AM parts. With this approach, piezoelectric wafers bonded

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Weber, Y., J. Goxe, S. Alves, et al. "Advanced Failure Analysis on Silicon Pipeline Defects and Dislocations in Mixed-Mode Devices." In ISTFA 2014. ASM International, 2014. http://dx.doi.org/10.31399/asm.cp.istfa2014p0502.

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Abstract The presence of crystalline defects, including dislocations and pipeline defect, is detrimental to both the processing and the intrinsic quality of semiconductor devices. The electrical parametric or functional failures generated by those defects require accurate identification and proper classification in a continuous improvement mindset. Depending on the failure analyst choice of the investigation technique, the distinction between a dislocation and a pipeline defect can be difficult. In this paper, based on case studies of mixed-mode devices, the various electrical and physical FA

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Chen, C. Q., G. B. Ang, P. T. Ng, et al. "Non-Visible Defect Analysis by the Nanoprobing Methodology." In ISTFA 2015. ASM International, 2015. http://dx.doi.org/10.31399/asm.cp.istfa2015p0414.

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Abstract This paper explains how the authors used nanoprobing techniques and electrical characterization to trace a die failure to a problem with the photoresist used to mask the wafer for ion implantation. Nanoprobing and leakage current measurements revealed significant differences between the inner and outer fingers of a multi-finger native transistor. Based on simulations, the differences can be attributed to severe scattering at the active edge of the Pwell due to problems with the photoresist, resulting in nonuniform doping profiles and die failure.

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Jacobs, K. J. P., A. Khaled, M. Stucchi, et al. "Light-Induced Capacitance Alteration for Nondestructive Fault Isolation in TSV Structures for 3D Integration." In ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0406.

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Abstract We report on a new non-destructive electrical fault isolation (EFI) technique to localize interconnection failures in through-silicon via (TSV) structures for three-dimensional (3-D) integration. The scanning optical microscopy (SOM) technique is based on light-induced capacitance alteration (LICA) and uses localized photon probing of TSV interconnect capacitance to localize interruptions of electrical connectivity. The technique is applicable to passivated devices and allows rapid, efficient, and non-destructive fault isolation at wafer level. We describe the physics behind signal ge

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Gupta, Raj K. "In-Situ Test Structures for Metrological and Mechanical Characterization of MEMS." In ASME 1998 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 1998. http://dx.doi.org/10.1115/imece1998-1149.

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Abstract Separating geometrical dependence from extracted mechanical stiffness parameters to obtain fundamental mechanical properties, such as the Young’s Modulus E and the internal (residual) stress σ within 10%, is difficult. Mechanical stiffness, obtained from an intermediate measured quantity, generally depends on high powers of structural geometry, but only linearly with mechanical property. For example, the maximum deflection of a uniformly loaded beam under linear-elastic conditions is proportional to L4 and 1/t3, where L is the beam length and t is the thickness, but is only linearly p

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Liu, Weiping, and Victor Giurgiutiu. "Finite Element Simulation of Piezoelectric Wafer Active Sensors Based Structural Health Monitoring." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-43570.

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Crack detection with piezoelectric wafer active sensors (PWAS) is emerging as an effective and powerful technique in structural health monitoring (SHM). Modeling and simulation of PWAS and host structure play an important role in the SHM applications with PWAS. For decades finite element method has been extensively applied in the analysis of piezoelectric materials and structures. The advantage of finite element analysis over analytical solutions is that stress and electrical field measurements of complex geometries, and their variations throughout the device, are more readily calculated. FEM

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Hartfield, C. D., J. J. Broz, and T. M. Moore. "Mechanical and Electrical Characterization of an IC Bond Pad Stack Using a Novel In-Situ Methodology." In ISTFA 2003. ASM International, 2003. http://dx.doi.org/10.31399/asm.cp.istfa2003p0486.

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Abstract The semiconductor industry’s efforts to integrate dielectrics into Si devices has driven characterization efforts to address the challenges presented by adoption of this new class of materials. Abundant literature exists on the considerations required for CMP process recommendations for successful fabrication, adhesion requirements for both fabrication and assembly, and considerations for interconnect structure to enable wire-bonding. There is also interest in understanding the wafer level test challenges presented by the low-K devices. In addition to the typical concerns about reachi

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