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Journal articles on the topic 'On-Wafer electrical measurements'

Author: Grafiati

Published: 31 May 2025

Last updated: 31 July 2025

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1

Potts, David, Scott Hildreth, and Binod Kumar G. Nair. "Impacts of Nested Variance Components on Semiconductor Electrical Test Sampling." EDFA Technical Articles 24, no. 3 (2022): 4–10. http://dx.doi.org/10.31399/asm.edfa.2022-3.p004.

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Abstract Inline wafer electrical testing (WET) offers an early read on semiconductor manufacturing processes via measurements taken on test structures placed throughout the wafer. Interpreting the data can be challenging, however. In many cases, only a sample of the test sites are monitored in production. Complex manufacturing requirements further complicate the problem because some operations are iteratively executed within subregions across a given wafer, while others are run on the entire wafer at once, and still others are applied to wafers in batches. This results in a nested variance str

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2

Arscott, Steve. "On overtravel and skate in cantilever-based probes for on-wafer measurements." Journal of Micromechanics and Microengineering 32, no. 5 (2022): 057001. http://dx.doi.org/10.1088/1361-6439/ac521e.

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Abstract Due to the deformability of a microcantilever-based probe, there is an interesting and subtle interplay between the probe overtravel, the tip skate on the surface, and the ultimate tangency of the tip of the probe with the wafer surface. The relationship between these parameters is described here. The scalable model is tested using a macroscopic cantilever and found to be accurate in its predictions. In addition, to avoid potential skate-induced damage to metallisation, the idea of zero-skate using a cantilever-based probe has been introduced; minimal skate is demonstrated using a mac

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Savtchouk, Alexandre, Marshall Wilson, D. Marinskiy, B. Schrayer, C. Almeida, and Jacek Lagowski. "Recent Progress in Non-Contact Electrical Characterization for SiC and Related Compounds." Materials Science Forum 1089 (May 26, 2023): 51–56. http://dx.doi.org/10.4028/p-3bn937.

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An increasing interest in the non-contact corona charge-based electrical characterization technique, CnCV, for wide bandgap semiconductors, is justified by the reduction of cost and the reduction of testing feedback time [1]. In addition, the technique expands measurement capabilities. Regarding SiC, recent progress includes expanded dopant concentration range and dopant measurement on fresh epitaxial wafers. The latter is made possible with an ultraviolet wafer pretreatment technique [2]. The novel applications to AlGaN/GaN HEMT on insulating substrates demonstrate the benefits of a noninvasi

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Weatherspoon, M. H., and L. P. Dunleavy. "Vector Corrected On-Wafer Measurements of Noise Temperature." IEEE Transactions on Instrumentation and Measurement 54, no. 3 (2005): 1327–32. http://dx.doi.org/10.1109/tim.2005.847218.

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5

Lecarpentier, Gilbert, Rahul Agarwal, Wenqi Zhang, et al. "Die-to-Wafer Bonding of Thin Dies using a 2-Step Approach; High Accuracy Placement, then Gang Bonding." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (2010): 001254–81. http://dx.doi.org/10.4071/2010dpc-wa14.

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25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 10μm and 40μm. A special test structure was designed on the landing die to electrically determine the alignment accuracy after bonding - both with respect to the X-Y alignment and the rotation. Stacks were then assembled by collective hybrid bonding process. The top die is aligned and placed on the landing wafer coverer by a patterned polymer acting as a temporary alignment holder, and then the

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Wang, Yibang, Xingchang Fu, Aihua Wu, et al. "Development of gallium-arsenide-based GCPW calibration kits for on-wafer measurements in the W-band." International Journal of Microwave and Wireless Technologies 12, no. 5 (2019): 367–71. http://dx.doi.org/10.1017/s1759078719001521.

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AbstractWe present details of on-wafer-level 16-term error model calibration kits used for the characterization of W-band circuits based on a grounded coplanar waveguide (GCPW). These circuits were fabricated on a thin gallium arsenide (GaAs) substrate, and via holes, were utilized to ensure single mode propagation (i.e., eliminating the parallel-plate mode or surface mode). To ensure the accuracy of the definition for the calibration kits, multi-line thru-reflect-line (MTRL) assistant standards were also fabricated on the same wafer and measured. The same wafer also contained passive and acti

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Yu, Wan Cheng, Xiu Fang Chen, Xiao Bo Hu, and Xian Gang Xu. "Wafer-Scale Graphene on 4-Inch SiC." Materials Science Forum 858 (May 2016): 1133–36. http://dx.doi.org/10.4028/www.scientific.net/msf.858.1133.

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Wafer-scale graphene on SiC with uniform structural features was grown on semi-insulating 4 inch on-axis 4H-SiC (0001) face. Growth was carried out in a conventional physical vapor transport (PVT) growth system. Atmospheric pressure graphitization and a “face-down” orientation were account for the high uniformity of graphene. Atomic force microscopy, electrostatic force microscopy and Raman spectroscopy were used to confirm the uniformity of surface morphology and layer number. Electrical properties were also characterized by Hall measurements on 15×15mm2 samples sawed from the wafer. An avera

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Li, Xuan, Shiwei Feng, Zhihong Feng, et al. "A thermal boundary resistance measurement method based on a designed chip with the heat source separated from the temperature sensor." Applied Physics Letters 122, no. 7 (2023): 073501. http://dx.doi.org/10.1063/5.0137965.

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Measurements of thermal boundary resistance (TBR) are of great significance in the fields of electronic packaging and thermal management. In this study, a measurement method based on a designed 1 × 1 mm2 chip with a heat source separated from a temperature sensor was developed. The chip consists of a temperature sensor with nine Schottky diodes connected in series and a heat source composed of metal wires, which are separated by SiO2 to realize electrical isolation. With this chip, the TBR of samples can be extracted from transient temperature response curves of GaN on a Si wafer using the str

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9

Phung, Gia Ngoc, Franz Josef Schmuckle, Ralf Doerner, et al. "Influence of Microwave Probes on Calibrated On-Wafer Measurements." IEEE Transactions on Microwave Theory and Techniques 67, no. 5 (2019): 1892–900. http://dx.doi.org/10.1109/tmtt.2019.2903400.

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10

Vaha-Heikkila, T., M. Lahdes, M. Kantanen, and J. Tuovinen. "On-wafer noise-parameter measurements at w -band." IEEE Transactions on Microwave Theory and Techniques 51, no. 6 (2003): 1621–28. http://dx.doi.org/10.1109/tmtt.2003.812554.

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11

Arias, Abraham, Nicola Nedev, Mario Curiel, et al. "Electrical Characterization of Interface Defects in MOS Structures Containing Silicon Nanoclusters." Advanced Materials Research 976 (June 2014): 129–32. http://dx.doi.org/10.4028/www.scientific.net/amr.976.129.

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The effect of annealing temperature on the properties of c-Si wafer/SiOx interface (x = 1.15 and 1.3) is studied by Transmission Electron Microscopy and Capacitance/Conductance-Voltage measurements. Furnace annealing for 60 min at 700 and 1000 °C is used to grow amorphous or crystalline Si nanoparticles. The high temperature process leads to an epitaxial overgrowth of the Si wafer and an increase of the interface roughness, 3-4 monolayers at 700 °C and 4-5 monolayers at 1000 °C. The increased surface roughness is in correlation with the higher density of electrically active interface states.

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Krost, A., Armin Dadgar, F. Schulze, R. Clos, K. Haberland, and T. Zettler. "Heteroepitaxy of GaN on Silicon: In Situ Measurements." Materials Science Forum 483-485 (May 2005): 1051–56. http://dx.doi.org/10.4028/www.scientific.net/msf.483-485.1051.

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Due to the lack of GaN wafers, so far, group-III nitrides are mostly grown on sapphire or SiC substrates. Silicon offers an attractive alternative because of its low cost, large wafer area, and physical benefits such as the possibility of chemical etching, lower hardness, good thermal conductivity, and electrical conducting or isolating for light emitting devices or transistor structures, respectively. However, for a long time, a technological breakthrough of GaN-on-silicon has been thought to be impossible because of the cracking problem originating in the huge difference of the thermal expan

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Chih-Hung Chen, Ying-Lien Wang, M. H. Bakr, and Zheng Zeng. "Novel Noise Parameter Determination for On-Wafer Microwave Noise Measurements." IEEE Transactions on Instrumentation and Measurement 57, no. 11 (2008): 2462–71. http://dx.doi.org/10.1109/tim.2008.925021.

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14

Cui, Yiran, and Georgios C. Trichopoulos. "A Quasi-Optical Testbed for Wideband THz On-Wafer Measurements." IEEE Transactions on Terahertz Science and Technology 9, no. 2 (2019): 126–35. http://dx.doi.org/10.1109/tthz.2019.2894505.

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15

Wang, Yi, and Michael J. Lancaster. "Coplanar to microstrip transitions for on-wafer measurements." Microwave and Optical Technology Letters 49, no. 1 (2006): 100–103. http://dx.doi.org/10.1002/mop.22056.

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16

Neudeck, Philip G., Liang Yu Chen, David J. Spry, Glenn M. Beheim, and Carl W. Chang. "Electrical Characterization of a 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design." Materials Science Forum 821-823 (June 2015): 781–84. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.781.

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This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA’s on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 °C. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 °C to 500 °C.

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Kallinger, Birgit, Daniel Kaminzky, Patrick Berwian, Jochen Friedrich, and Steffen Oppel. "Optical Stressing of 4H-SiC Material and Devices." Materials Science Forum 924 (June 2018): 196–99. http://dx.doi.org/10.4028/www.scientific.net/msf.924.196.

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Electrical testing with regard to bipolar degradation of high voltage SiC devices cannot be done on wafer level, but only expensively after module assembly. We show that 4H-SiC material can be optically stressed by applying high UV laser intensities, i.e. bipolar degradation as in electrical stress tests can be provoked on wafer level. Therefore, optical stressing can be used for control measurements and reliability testing. Different injection (=stress) levels have been used similar to the typical doping level of the base material and similar to the established electrical stress test. The ana

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18

Wei, S., S. Wu, I. Kao, and F. P. Chiang. "Measurement of Wafer Surface Using Shadow Moire´ Technique With Talbot Effect." Journal of Electronic Packaging 120, no. 2 (1998): 166–70. http://dx.doi.org/10.1115/1.2792612.

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In this paper, a modified shadow moire´ technique is applied to measure surface topology of wafers. When a wafer is sliced, either by an inner-diameter (ID) saw or wiresaw, the surface needs to be measured to ensure the consistency of quality. Two important characteristics of the wafer surface measurements are the warpage and total thickness variation (TTV). Currently, the most commonly used method of wafer measurement employs a pair of capacitive measuring probes which sample points on the surface of a rotating wafer to obtain the contours of surface. Many sampling points on the surface are n

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19

Farshchi Yazdi, Seyed Amir Fouad Farshchi, Matteo Garavaglia, Aldo Ghisi, and Alberto Corigliano. "An Experimental and Numerical Study on Glass Frit Wafer-to-Wafer Bonding." Micromachines 14, no. 1 (2023): 165. http://dx.doi.org/10.3390/mi14010165.

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A thermo-mechanical wafer-to-wafer bonding process is studied through experiments on the glass frit material and thermo-mechanical numerical simulations to evaluate the effect of the residual stresses on the wafer warpage. To experimentally characterize the material, confocal laser profilometry and scanning electron microscopy for surface observation, energy dispersive X-ray spectroscopy for microstructural investigation, and nanoindentation and die shear tests for the evaluation of mechanical properties are used. An average effective Young’s modulus of 86.5 ± 9.5 GPa, a Poisson’s ratio of 0.1

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Majidi-Ahy, R., M. Shakouri, and D. M. Bloom. "100 GHz active electronic probe for on-wafer S-parameter measurements." Electronics Letters 25, no. 13 (1989): 828. http://dx.doi.org/10.1049/el:19890558.

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Watanabe, Naoya, Hiroshi Yamamoto, Takahiko Mitsui, and Eiichi Yamamoto. "Hybrid Bonding of Via-middle TSV Wafer Fabricated using Direct Si/Cu Grinding, Residual Metal Removal, CVD, and CMP." International Symposium on Microelectronics 2020, no. 1 (2020): 000135–39. http://dx.doi.org/10.4071/2380-4505-2020.1.000135.

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Abstract We performed hybrid bonding of a via-middle through-silicon via (TSV) wafer that was fabricated using direct Si/Cu grinding, residual metal removal, chemical vapor deposition of a rear-side insulator, and chemical mechanical polishing. The rear side of the via-middle TSV wafer (wafer diameter: 197 mm, wafer thickness: 22 μm, TSV diameter: 5.5 μm, and total thickness variation: &lt;2 μm), which was mounted on a support glass, was bonded to a Cu electrode wafer (wafer diameter: 200 mm, wafer thickness: 625 μm, and Cu electrode diameter: 6 μm). The bonding was performed at room tempe

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Miller-Link, Elisa. "(Invited) Spatially Controlled Photo-Dedoping of Large-Area 2D MoS₂." ECS Meeting Abstracts MA2025-01, no. 15 (2025): 1161. https://doi.org/10.1149/ma2025-01151161mtgabs.

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2D materials, particularly transition metal dichalcogenides (TMDCs), hold great promise for applications in microelectronics. However, a significant challenge in commercializing these materials lies in achieving precise, wafer-scale doping with high spatial fidelity. Our results demonstrate stable, precise, and controllable photo-dedoping in wafer-scale molybdenum disulphide (MoS₂) using visible light. Hole trap states within the underlying oxide are shown to enable stable and long-lived dedoping in wafer scale monolayer MoS2. This underlying defective rich molybdenum oxide is grown concurrent

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SUHERMAN, P. M., T. J. JACKSON, Y. KOUTSONAS, R. A. CHAKALOV, and M. J. LANCASTER. "On-Wafer Measurements of Tuneability in Ba0.5Sr0.5TiO3 Thin Films." Integrated Ferroelectrics 61, no. 1 (2004): 133–37. http://dx.doi.org/10.1080/10584580490459044.

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24

Peng, Gang, Wen Bo Ma, Xiao Kun Huang, et al. "Electrical Transport Properties of Single SiC NW-FET." Advanced Materials Research 704 (June 2013): 281–86. http://dx.doi.org/10.4028/www.scientific.net/amr.704.281.

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A single SiC NW-FET (nanowire field effect transistor) was fabricated by FIB (Focus-Ion-Beam) method and the photo-electric properties of the device including I-V characteristic, transfer characteristic and time response et.al. were studied in this paper. SiC NWs (NWs) were prepared by pyrolysis of a polymer precursor with ferrocene as the catalyst by a CVD route. The NWs were suspended in ethanol by ultrasonic, then sprayed onto a silicon wafer with 300nm silicon oxide. Pt electrodes were deposited directly by FEI NanoLab 600i along with the SiC NW on silicon wafer. The transfer characteristi

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Teppati, Valeria, and Andrea Ferrero. "A Comparison of Uncertainty Evaluation Methods for On-Wafer $S$-Parameter Measurements." IEEE Transactions on Instrumentation and Measurement 63, no. 4 (2014): 935–42. http://dx.doi.org/10.1109/tim.2013.2287796.

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26

Lowry, Lyan, Paul Zschack, and Robert De Angelis. "Fluorine Implantation and Residual Stresses in Polysilicon Films." Advances in X-ray Analysis 38 (1994): 235–42. http://dx.doi.org/10.1154/s0376030800017845.

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Abstract X-ray diffraction techniques were utilized to study the film stress effects in silicon wafers subjected to several processing conditions. The wafer processing matrix consisted of three thicknesses of polysilicon deposited on (100) silicon with a 25 nm layer of Si02. The polysilicon was doped with phosphorous and arsenic after which the samples were implanted with fluorine at 30 KeV at a dose of 6 × 1015 cm2. A synchrotron radiation source at Brookhaven National Laboratory on beamline X-14 was employed to determine the residual stresses in the polysilicon film by a powder diffraction t

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Bhatia, Ekta, Soumen Kar, Jakub Nalaskowski, et al. "Chemical mechanical planarization for Ta-based superconducting quantum devices." Journal of Vacuum Science & Technology B 41, no. 3 (2023): 033202. http://dx.doi.org/10.1116/6.0002586.

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We report on the development of a chemical mechanical planarization (CMP) process for thick damascene Ta structures with pattern feature sizes down to 100 nm. This CMP process is the core of the fabrication sequence for scalable superconducting integrated circuits at a 300 mm wafer scale. This work has established the elements of various CMP-related design rules that can be followed by a designer for the layout of circuits that include Ta-based coplanar waveguide resonators, capacitors, and interconnects for tantalum-based qubits and single flux quantum circuits. The fabrication of these struc

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Xiang, Chao, Yulan Lu, Chao Cheng, Junbo Wang, Deyong Chen, and Jian Chen. "A Resonant Pressure Microsensor with a Wide Pressure Measurement Range." Micromachines 12, no. 4 (2021): 382. http://dx.doi.org/10.3390/mi12040382.

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This paper presents a resonant pressure microsensor with a wide range of pressure measurements. The developed microsensor is mainly composed of a silicon-on-insulator (SOI) wafer to form pressure-sensing elements, and a silicon-on-glass (SOG) cap to form vacuum encapsulation. To realize a wide range of pressure measurements, silicon islands were deployed on the device layer of the SOI wafer to enhance equivalent stiffness and structural stability of the pressure-sensitive diaphragm. Moreover, a cylindrical vacuum cavity was deployed on the SOG cap with the purpose to decrease the stresses gene

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Sushko, Oleksandr, Max Munoz Torrico, Robert S. Donnan, Clive G. Parini, and Rostyslav Dubrovka. "70-110 GHz On-wafer Probe Station S-parameters Measurements of Planar Multenna." Radioelectronics and Communications Systems 64, no. 6 (2021): 293–99. http://dx.doi.org/10.3103/s0735272721060029.

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Van Caekenberghe, Koen, Kenneth M. Brakora, Wonbin Hong, et al. "A 2–40 GHz Probe Station Based Setup for On-Wafer Antenna Measurements." IEEE Transactions on Antennas and Propagation 56, no. 10 (2008): 3241–47. http://dx.doi.org/10.1109/tap.2008.929433.

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Ahmed, Abdul-Rahman, Dong-Hyun Lee, and Kyung-Whan Yeom. "On-wafer noise parameters measurement using an extended six-port network and conventional noise figure analyzer." International Journal of Microwave and Wireless Technologies 9, no. 4 (2016): 821–29. http://dx.doi.org/10.1017/s1759078716000842.

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In this paper, we demonstrate the successful implementation of an onwafer noise parameters test set that employs an extended six-port network and a conventional noise figure analyzer. The necessary formulation that enables the calibration of the noise parameter test set as well as extraction of the noise wave correlation matrix of a two-port device under test (DUT) was tested for coaxial connector-type DUT measurement in an earlier work but not for onwafer-type DUT. Furthermore, we demonstrate the performance of this technique against data obtained from the well-known tuner method. Measurement

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Tiemeijer, L. F., R. J. Havens, R. de Kort, and A. J. Scholten. "Improved Y-factor method for wide-band on-wafer noise-parameter measurements." IEEE Transactions on Microwave Theory and Techniques 53, no. 9 (2005): 2917–25. http://dx.doi.org/10.1109/tmtt.2005.854243.

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Xie, Linli, Matthew F. Bauwens, Souheil Nadri, et al. "Electronic Calibration for Submillimeter-Wave On-Wafer Scattering Parameter Measurements Using Schottky Diodes." IEEE Transactions on Terahertz Science and Technology 10, no. 6 (2020): 583–92. http://dx.doi.org/10.1109/tthz.2020.3006744.

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Gojdka, Björn, Daniel Cichon, Yannik Lembrecht, et al. "Demonstration of Fully Integrable Long-Range Microposition Detection with Wafer-Level Embedded Micromagnets." Micromachines 13, no. 2 (2022): 235. http://dx.doi.org/10.3390/mi13020235.

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A fully integrable magnetic microposition detection for miniaturized systems like MEMS devices is demonstrated. Whereas current magnetic solutions are based on the use of hybrid mounted magnets, here a combination of Hall sensors with a novel kind of wafer-level integrable micromagnet is presented. 1D measurements achieve a precision <10 µm within a distance of 1000 µm. Three-dimensional (3D) measurements demonstrate the resolution of complex trajectories in a millimeter-sized space with precision better than 50 µm in real time. The demonstrated combination of a CMOS Hall sensor and wafer-l

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Fischer, Andreas, Ioan Voicu Vulcanean, Sebastian Pingel, and Anamaria Steinmetz. "Impact of organic particles from wafer handling equipment on silicon heterojunction pseudo-efficiency." EPJ Photovoltaics 14 (2023): 29. http://dx.doi.org/10.1051/epjpv/2023023.

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Within this paper a systematic analysis of particle transfer onto SHJ Solar cell precursors by handling with suction cups and the impact on the pseudo efficiency is presented. The study establishes a correlation between particle area coverage and a resulting loss of pseudo solar cell parameters. The analysis was carried out on one hand by means of SEM measurements at the contact points between suction cup and wafer to quantify particle transfer and on the other hand by means of suns photoluminescence imaging measurements to evaluate the resulting losses. It is shown that the choice of contact

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González-Posadas, Vicente, José Luis Jiménez-Martín, Angel Parra-Cerrada, David Espinosa Adams, and Wilmar Hernandez. "Stability, Mounting, and Measurement Considerations for High-Power GaN MMIC Amplifiers." Sensors 23, no. 23 (2023): 9602. http://dx.doi.org/10.3390/s23239602.

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In this paper, the precise design of a high-power amplifier (HPA) is shown, along with the problems associated with the stability of “on-wafer” measurements. Here, techniques to predict possible oscillations are discussed to ensure the stability of a monolithic microwave-integrated circuit (MMIC). In addition, a deep reflection is made on the instabilities that occur when measuring both on wafer and using a mounted chip. Stability techniques are used as tools to characterize measurement results. Both a precise design and instabilities are shown through the design of a three-stage X-band HPA in

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Kim, Jae-Hwan, Yoonsung Koo, Wansoo Song, and Sang Jeen Hong. "On-Wafer Temperature Monitoring Sensor for Condition Monitoring of Repaired Electrostatic Chuck." Electronics 11, no. 6 (2022): 880. http://dx.doi.org/10.3390/electronics11060880.

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The temperature of electrostatic chuck (ESC), a wafer susceptor used in semiconductor etch equipment, must accurately control the temperature of wafers during the etching process to obtain uniform and consistent process results. Failure to control the precise temperature can lead to rejection from the high-volume semiconductor manufacturing site (one of the most high-cost equipment components which can be repaired for its extended use). In this research, we propose a wireless-type on-wafer temperature monitoring system (OTMS) for easier and faster temperature monitoring to help temperature mea

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Rupp, Roland, Werner Schustereder, Tobias Höechbauer, et al. "Alternative Highly Homogenous Drift Layer Doping for 650 V SiC Devices." Materials Science Forum 858 (May 2016): 531–34. http://dx.doi.org/10.4028/www.scientific.net/msf.858.531.

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A new method for homogenous drift layer doping is introduced. Instead of in-situ doping during epitaxial growth a subsequent high energy ion implant step is used to dope the drift layer of 650V MPS (Merged-PN-Schottky) diodes. In order to avoid multiple implant steps with various energies for emulating a box-like doping profile, a novel “energy filter” membrane is used to transform the monochromatic ion beam to a beam with a continuous energy spectrum suited for box-like doping. The electrical characteristics of the diodes manufactured by this means show a very homogenous blocking behavior on

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Salim, Faiza M. "Technological Characteristics of Vanadyl Sulfate – Porous Silicon Heterojunction." NeuroQuantology 20, no. 1 (2022): 56–61. http://dx.doi.org/10.14704/nq.2022.20.1.nq22008.

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Near nano limit of [vanadium sulfate hydrate / porous silicon] heterojunction using zinc sulfide as a window for solar cell applications were investigated. Nanoparticles of vanadium sulfate hydrate were prepared by the electrochemical method followed by deposited in the form of thin films on bases of conductive glass and porous silicon to study the structural properties. The transmittance, absorbance and energy gap for the active material and the nanolayer window were performed. Grain size and roughness rate were determined via the surface topography test. The electrical parameters were measur

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Daffe, Khadim, Jaouad Marzouk, Christophe Boyaval, Gilles Dambrine, Kamel Hadaddi, and Steve Arscott. "A comparison of pad metallization in miniaturized microfabricated silicon microcantilever-based wafer probes for low contact force low skate on-wafer measurements." Journal of Micromechanics and Microengineering 32, no. 1 (2021): 015007. http://dx.doi.org/10.1088/1361-6439/ac3cd7.

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Abstract Miniaturized, microfabricated microelectromechanical systems-based wafer probes are used here to evaluate different contact pad metallization at low tip forces (<mN) and low skate on the on-wafer pads. The target application is low force RF probes for on-wafer measurements which cause minimal damage to both probes and pads. Low force enables the use of softer, more conductive metallisation. We have studied four different thin film contact pad metals based on their thin film electrical resistivity and micro-hardness: gold, nickel, molybdenum, and chromium. The contact pads sizes wer

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Oldsen, Marten, Ulrich Hofmann, Joachim Janes, Hans-Joachim Quenzer, and Bernd Wagner. "Waferlevel Vacuum Packaged Microscanners: A High Yield Fabrication Process for Mobile Applications." Journal of Integrated Circuits and Systems 4, no. 2 (2009): 73–78. http://dx.doi.org/10.29292/jics.v4i2.301.

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Packaging of MEMS is an important expense factor within the production costs and, to ensure mass producibility, the packaging has to be performed on a waferlevel. While for inertial MEMS this is state of the art, it has not yet been reported for scanning micromirrors. Therefore, Fraunhofer ISIT has developed a process technology based on two 30 μm thick epitaxially deposited polysilicon layers for the manufacturing of waferlevel vacuum packaged MEMS scanning mirrors. It allows the fabrication of vertically stacked combdrives for out-of-plane mirror operation and a low damping environment for t

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Kooho Jung, L. A. Hayden, O. D. Crisalle, et al. "A New Characterization and Calibration Method for 3-dB-Coupled On-Wafer Measurements." IEEE Transactions on Microwave Theory and Techniques 56, no. 5 (2008): 1193–200. http://dx.doi.org/10.1109/tmtt.2008.921688.

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Hartner, Walter, Martin Niessner, Francesca Arcioni, et al. "Reliability and Performance of Wafer Level Fan Out Package for Automotive Radar." Journal of Surface Mount Technology 34, no. 1 (2021): 32–39. http://dx.doi.org/10.37665/smt.v34i1.12.

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Embedded wafer level ball grid array (eWLB) or FO-WLP (Fan-out wafer-level packaging) is investigated as a package for MMICs (Monolithic Microwave Integrated Circuit) for automotive radar applications in the 77GHz range. Special focus is put on the thermo-mechanical performance to achieve automotive quality targets. The typical fatigue modes “solder ball fatigue” and “copper fatigue”, evolving during thermo-mechanical stress like cycling on board will be discussed. Simulation as well as experimental preparation results for typical fatigue levels are given. In addition, several influencing para

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Bogaerts, L., A. Phommahaxay, C. Gerets, et al. "TEMPORARY PROTECTIVE PACKAGING FOR OPTICAL MEMS." International Symposium on Microelectronics 2011, no. 1 (2011): 001052–57. http://dx.doi.org/10.4071/isom-2011-tha5-paper2.

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The fragility of MEM devices is one of the main concerns in case of standard packaging. Steps such as wafer dicing, die handling, assembly and wire bonding can seriously damage the device functionality if the MEM devices are not properly protected during the assembly processes. In this paper we report for the first time on bonding and removal of protective temporary caps used to ease the packaging of MEMS for optical applications. The package, based on a heat decomposable and photo-patternable polymer sealing ring, is gross leak tight, fulfills the MIL spec for shear testing and respects the t

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Zhou, Yongxin, Yuandong Gu, and Songsong Zhang. "Nondestructive Wafer Level MEMS Piezoelectric Device Thickness Detection." Micromachines 13, no. 11 (2022): 1916. http://dx.doi.org/10.3390/mi13111916.

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This paper introduces a novel nondestructive wafer scale thin film thickness measurement method by detecting the reflected picosecond ultrasonic wave transmitting between different interfacial layers. Unlike other traditional approaches used for thickness inspection, this method is highly efficient in wafer scale, and even works for opaque material. As a demonstration, we took scandium doped aluminum nitride (AlScN) thin film and related piezoelectric stacking layers (e.g. Molybedenum/AlScN/Molybdenum) as the case study to explain the advantages of this approach. In our experiments, a laser wi

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Chéron, Jérôme, Michel Campovecchio, Denis Barataud, et al. "Electrical modeling of packaged GaN HEMT dedicated to internal power matching in S-band." International Journal of Microwave and Wireless Technologies 4, no. 5 (2012): 495–503. http://dx.doi.org/10.1017/s1759078712000530.

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The electrical modeling of power packages is a major issue for designers of high-efficiency hybrid power amplifiers. This paper reports the synthesis and the modeling of a packaged Gallium nitride (GaN) High electron mobility transistor (HEMT) associating a nonlinear model of the GaN HEMT die with an equivalent circuit model of the package. The extraction procedure is based on multi-bias S-parameter measurements of both packaged and unpackaged (on-wafer) configurations. Two different designs of 20 W packaged GaN HEMTs illustrate the modeling approach that is validated by time-domain load-pull

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Bitincka, E., G. Gilardi, and M. K. Smit. "On-Wafer Optical Loss Measurements Using Ring Resonators With Integrated Sources and Detectors." IEEE Photonics Journal 6, no. 5 (2014): 1–12. http://dx.doi.org/10.1109/jphot.2014.2352627.

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Shangguan, Dongkai, Yao Jian Lin, Won Kyung Choi, Seng Guan Chow, and Seung Wook Yoon. "Experimental Study on 28nm Chip/Package Interactions in eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages." International Symposium on Microelectronics 2016, S2 (2016): S1—S22. http://dx.doi.org/10.4071/isom-2016-slide-9.

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To meet the continued demand for form factor reduction and functional integration of electronic devices, WLP (Wafer Level Packaging) is an attractive packaging solution with many advantages in comparison with standard BGA (Ball Grid Array) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, eWLB (Embedded Wafer Level BGA) is a fan-out WLP solution which can enable applications that require higher I/O density, s

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Hefter, J., and P. G. Rossoni. "Electrical microcharacterization of Si-TaSi2 eutectic composites." Proceedings, annual meeting, Electron Microscopy Society of America 50, no. 2 (1992): 1700–1701. http://dx.doi.org/10.1017/s0424820100133138.

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Semiconductor-metal eutectic composites, formed by directional solidification from the melt, are composed of arrays of continuous metallic fibers contained within a single-crystal semiconductor matrix. Such composites contain rods having diameters of ≈1 μm with inter-rod spacings on the order of 10 μm. These rods form cylindrical Schottky junctions with the Si and can be used as the basis for a variety of electronic and optoelectronic devices, including photodetectors and bulk field effect transistors. Electron beam induced current (EBIC) measurements permit the determination of the depletion

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Huang, Siyi, Masao Ikeda, Minglong Zhang, Jianjun Zhu, and Jianping Liu. "Suitable contacting scheme for evaluating electrical properties of GaN-based p-type layers." Journal of Semiconductors 44, no. 5 (2023): 052802. http://dx.doi.org/10.1088/1674-4926/44/5/052802.

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Abstract A suitable contacting scheme for p-(Al)GaN facilitating quick feedback and accurate measurements is proposed in this study. 22 nm p+-GaN followed by 2 nm p-In0.2Ga0.8N was grown on p-type layers by metal-organic chemical vapor deposition. Samples were then cut into squares after annealing and contact electrodes using In balls were put at the corners of the squares. Good linearity between all the electrodes was confirmed in I–V curves during Hall measurements even with In metal. Serval samples taken from the same wafer showed small standard deviation of ~ 4% for resistivity, Hall mobil

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