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Dissertations / Theses on the topic 'Operational transconductance amplifier (OTA)'
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1
Vora, Ashish. "A 90 dB, 85 MHz operational transconductance amplifier (OTA) using gain boosting technique /." Link to online version, 2005. https://ritdml.rit.edu/dspace/handle/1850/1319.
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Ramachandran, Arun. "Nonlinearity and noise modeling of operational transconductance amplifiers for continuous time analog filters." Texas A&M University, 2003. http://hdl.handle.net/1969.1/3925.
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A general framework for performance optimization of continuous-time OTA-C
(Operational Transconductance Amplifier-Capacitor) filters is proposed. Efficient
procedures for evaluating nonlinear distortion and noise valid for any filter of arbitrary
order are developed based on the matrix description of a general OTA-C filter model .
Since these procedures use OTA macromodels, they can be used to obtain the results
significantly faster than transistor-level simulation. In the case of transient analysis, the
speed-up may be as much as three orders of magnitude without almost no loss of
accuracy. This makes it possible to carry out direct numerical optimization of OTA-C
filters with respect to important characteristics such as noise performance, THD, IM3,
DR or SNR. On the other hand, the general OTA-C filter model allows us to apply
matrix transforms that manipulate (rescale) filter element values and/or change topology
without changing its transfer function. The above features are a basis to build automated
optimization procedures for OTA-C filters. In particular, a systematic optimization
procedure using equivalence transformations is proposed. The research also proposes
suitable software implementations of the optimization process. The first part of the
research proposes a general performance optimization procedure and to verify the
process two application type examples are mentioned. An application example of the
proposed approach to optimal block sequencing and gain distribution of 8th order
cascade Butterworth filter (for two variants of OTA topologies) is given. Secondly the
modeling tool is used to select the best suitable topology for a 5th order Bessel Low Pass
Filter. Theoretical results are verified by comparing to transistor-level simulation withCADENCE. For the purpose of verification, the filters have also been fabricated in
standard 0.5mm CMOS process.
The second part of the research proposes a new linearization technique to
improve the linearity of an OTA using an Active Error Feedforward technique. Most
present day applications require very high linear circuits combined with low noise and
low power consumption. An OTA based biquad filter has also been fabricated in 0.35mm
CMOS process. The measurement results for the filter and the stand alone OTA have
been discussed. The research focuses on these issues.
3
Sun, Shao-Chi. "Design and evaluation of a g m-RC bandpass filter using a 42 GHz linear OTA incorporating heterojunction bipolar transistors." Ohio University / OhioLINK, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1179864547.
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Michalička, Filip. "Syntéza elektronicky rekonfigurovatelných kmitočtových filtrů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413078.
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This diploma thesis deals with design of reconection-less electronically reconfigurable filter structures which have single input and single output using unconventional active elements, which have ability to adjust one of their parameter e.g. gain or transconductance. The first part describes basic parameters of frequency filters, the division of filters by frequency transfer response and used circuit elements, their operational modes, the principle of reconnection-less electronically reconfiguration and the circuit design method MUNV. Second part describes all active elements used in the proposal of filters, their properties and the implementation using existing transistor-level models. The third part contains the design of three reconnection-less electronically reconfigurable filters and the simulations results obtained from simulation programs OrCAD Capture and PSpice. The obtained results were compared with theoretical behaviour. This part also contains results of these analyses: sensitivity, parasitic, Monte Carlo and temperature to determine the behaviour in varied cases.
5
Anderson, Matthew Wilamowski Bogdan M. "Wide range tunable transconductance filters." Auburn, Ala, 2008. http://repo.lib.auburn.edu/EtdRoot/2008/SPRING/Electrical_and_Computer_Engineering/Thesis/Anderson_William_22.pdf.
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Czajkowski, Ondřej. "Operační transkonduktanční zesilovač (OTA) pro využití v programovatelných analogových polích." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219036.
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Operational amplifier will be designed and optimized with respect to set of required parameters. Real CMOS technology (available at Department of Microelectronics) will be used for designed OTA circuit and its simulations. Designed OTA will be used as universal operation amplifier configurable block in FPAA (field-programmable analog array) structures.
7
Nousek, Petr. "Porovnávací studie nízkonapěťových operačních zesilovačů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218696.
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This work deals with methods used in design of low voltage operational amplifiers. It describes some of the most commonly used methods. Properties of these methods are verified by computer simulation of operational transconductance amplifiers that are utilizing them.
8
Mora, Sánchez Alexander [Verfasser]. "Sigma-Delta Analog-to-Digital Modulators with a Single Operational Transconductance Amplifier for Low-Power SoC Design in Biomedical Applications / Alexander Mora Sánchez." Aachen : Shaker, 2007. http://d-nb.info/1164340336/34.
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Johansson, Anders. "Evaluation of different CMOS processes using a circuit optimization tool." Thesis, Linköping University, Electronics System, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-52338.
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The geometry of CMOS processes has decreased in a steady pace over the years at the same time as the complexity has increased. Even if there are more requirements on the designer today, the main goal is still the same: to minimize the occupied area and power dissipation. This thesis investigates if a prediction of the costs in future CMOS processes can be made. By implementing several processes on a test circuit we can see a pattern in area and power dissipation when we change to smaller processes.
This is done by optimizing a two-stage operational transconductance amplifier on basis of a given specification. A circuit optimization tool evaluates the performance measures and costs. The optimization results from the area and power dissipation is used to present a diagram that shows the decreasing costs with smaller processes and also a prediction of how small the costs will be for future processes. This thesis also presents different optimization tools and a design hexagon that can be used when we struggle with optimization trade-offs.
10
Kosztyu, Tomáš. "Moderní aktivní prvky a jejich chování v lineárních blocích." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218124.
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The topic of this master’s thesis was a frequency filters and their realization using modern active elements like UVC, UCC, VFA, CFA and OTA. The base point of this thesis was designed frequency filters with these active elements, when the shape of the transfer function will be identical for all structures and compare the characteristics of active elements. The proposed frequency filters are second order with one or two active elements. In the first part of thesis are discussed basic properties of frequency filters, their properties and distribution. Next are described the general characteristics of active filters and their basic elements such as operational amplifier OTA, VFA and CFA, and recently more frequently used voltage and current conveyor. The second part is the frequency filters designed with these elements is the same transfer function. Subsequently, simulations are done all the filters and obtained the frequency response. Finally, these filters are experimentally made and made practical measurements.
11
Prášek, David. "Autokompenzace ofsetu operačního zesilovače pro přesná měření." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218048.
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This work deals with the problems of the design of two stage operational amplifier with automatic offset compensation for precise measurement. Full design operational amplifier is aimed at appropriate realization in technology CMOS07 with usage Cadence design environment. The goal of the design is minimum offset value as well as the adherence to the parameters of the operational amplifier which are introduced in submission of the thesis.
12
Uher, Jiří. "Návrh filtračních struktur fraktálního řádu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242051.
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This thesis deals with the fractional (1+)-order filters. The proposed filters operate in the current-mode. The derivation of the filters has been achieved using a third-order aproximation of the coresponding fractional-order transfer functions. It also describes active elements such as universal current conveyor, current follower and operational transconductance amplifier. In the end of this thesis some new circuit solutions of the fractional-order filter are proposed. Then the proposed filters are realized and experimentally measured.
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Langhammer, Lukáš. "Nelineární obvodové struktury s proudovými aktivními prvky." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2012. http://www.nusl.cz/ntk/nusl-219456.
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This thesis deals with non-linear curcuit structures with current active elements. In its introduction this work deals with a description of the current active elements, such as current conveyor, transconductance operational amplifier and current follower. Further the text pays attention to the possiblities of the circuits for modification signals in analogue technology. First are described circuits of diode limiters and transducer. Great attention is paid to the amplifiers with current active elements. Are propřed simulated and practically realized circuits of universal precise full-wave rectifiers using operational amplifier and current conveyor and made comparisons of known and proposed circuits. The paper also discussed other circuit structures using of current active elements, such as multiplier, divider, a triangular signal generator and oscillators.
14
Gajdoš, Adam. "Elektronicky rekonfigurovatelné kmitočtové filtry." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-241983.
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The aim of the thesis was design of reconnection-less and electronically reconfigurable filters of SISO type with non-traditional active elements. Adjustability of bandwidth or quality factor is also required. First part of the thesis deals with theoretical analysis of filters, their operation modes and design of frequency filters using Signal-flow graph method aswell. Last but not least, electronical reconfiguration of transfer function and parasitic analysis was discussed. Another part describes active elements used in the practical part of thesis. Behaviors and design of active elements using existing circuits (e.g. UCC,EL2082) are described and their transformation into the Signal-flow graph form too. In the practical part five reconnection-less and reconfigurable filters of SISO type was designed using SNAP program. Simulations were done using Orcad program with ideal and real simulation models of active elements. Last part deals with filter design in EAGLE and experimental measurement.
15
Polách, Petr. "RC oscilátory pro pásmo vyšších kmitočtů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217477.
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This thesis deals with RC oscillators applicable in higher frequency ranges with the use of modern active elements. For individual function blocks (conveyor, current feedback amplifier, operational transconductance amplifier, voltage feedback amplifier) suitable models are suggested for the circuit simulator PSpice covering their characteristics on various levels, from an ideal one up to the full description of parasitic effects. On the basis of the study of recommended literature and company documentation various oscillator connections of the ranks 2 and 3 are suggested. By analysis through computer (PSpice, SNAP) the fulfilment of oscillation conditions, onset of oscillations were verified and by means of suitable simulations the effects of the impact on the parasitic characteristics of active elements was examined. Finally there are two oscillator connections stated and verified by simulations with the possibility of electronic retuning.
16
Prát, Marek. "Návrh elektronicky rekonfigurovatelných filtračních struktur s moderními aktivními prvky." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2018. http://www.nusl.cz/ntk/nusl-377113.
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The aim of master's thesis was design of electronically reconfigurable filters. Adjustability of pole frequency or quality factor is possible. First part of thesis deals with theoretical analysis of filters, their operation modes, design of frequency filters using Signal-Flow graph method and parasitic analysis. The next part describes active elements used in thesis. In a third part, three reconfigurable filters are described and designed and their simulations and parasitic analysis are made. Last part deals with filter design in EAGLE and experimental measurement.
17
Langhammer, Lukáš. "Plně diferenční kmitočtové filtry s moderními aktivními prvky." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-256565.
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Tato disertační práce se zaměřuje na výzkum v oblasti frekvenčních filtrů. Hlavním cílem je navrhnout a analyzovat plně diferenční kmitočtové filtry pracující v proudovém módu a využívající moderní aktivní prvky. Prezentované filtry jsou navrženy za použití proudových sledovačů, operačních transkonduktančních zesilovačů, plně diferenčních proudových zesilovačů a transrezistančních zesilovačů. Návrh se zaměřuje na možnost řídit některý z typických parametrů filtru pomocí řiditelných aktivních prvků, které jsou vhodně umístněny do obvodové struktury. Jednotlivé prezentované filtry jsou navrženy v nediferenční a diferenční verzi. Velký důraz je věnován srovnání plně diferenčních struktur s jejich odpovídajícími nediferenčními formami. Funkčnost jednotlivých návrhů je ověřena simulacemi a v některých případech i experimentálním měřením.
18
Csipkes, Gabor-Laszlo. "Integrated realizations of reconfigurable low pass and band pass filters for wide band multi-mode receivers." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2006. http://nbn-resolving.de/urn:nbn:de:swb:14-1145345696511-52655.
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With the explosive development of wireless communication systems the specifications of the supporting hardware platforms have become more and more demanding. According to the long term goals of the industry, future communications systems should integrate a wide variety of standards. This leads to the idea of software defined radio, implemented on fully reconfigurable hardware.Among other reconfigurable hardware blocks, suitable for the software radio concept, an outstanding importance belongs to the reconfigurable filters that are responsible for the selectivity of the system. The problematic of filtering is strictly connected to the architecture chosen for a multi-mode receiver realization. According to the chosen architecture, the filters can exhibit low pass or band pass frequency responses.The idea of reconfigurable frequency parameters has been introduced since the beginning of modern filtering applications due to the required precision of the frequency response. However, the reconfiguration of the parameters was usually done in a limited range around ideal values. The purpose of the presented research is to transform the classical filter structures with simple self-correction into fully reconfigurable filters over a wide range of frequencies. The ideal variation of the frequency parameters is continuous and consequently difficult to implement in real circuits. Therefore, it is usually sufficient to use a discrete programming template with reasonably small steps.There are several methods to implement variable frequency parameters. The most often used programming templates employ resistor and capacitor arrays, switched according to a given code. The low pass filter implementation proposed in this work uses a special switching template, optimized for a quasi-linear frequency variation over logarithmic axes. The template also includes the possibility to compensate errors caused by component tolerances and temperature. Another important topic concerns the implementation of programmable band pass filters, suitable for IF sampling receivers. The discussion is centered on the feasibility and the flexibility of different band pass filter architectures. Due to the high frequency requirements, the emphasis lays on filters that employ transconductance amplifiers and capacitorsDie rasch fortschreitende Entwicklung drahtloser Kommunikationssysteme führt zu immer anspruchsvolleren Spezifikationen der diese Systeme unterstützenden Hardwareplattformen. Zukünftige Kommunikationssysteme sollen übereinstimmend mit den längerfristigen Zielen der Industrie verschiedene Standards integrieren. Dies führt zu der Idee von vollständig rekonfigurierbarer Hardware, welche mittels Software gesteuert wird.Inmitten anderer rekonfigurierbarer Hardwareblöcke, die für das Software Radio Konzept geeignet sind, besitzen die steuerbaren Filter, welche wesentlichen Einfluss auf die Selektivität des Systems haben, eine enorme Bedeutung. Die Filterproblematik ist eng mit der gewählten Architektur der standardübergreifenden Empfängerrealisierung verknüpft. Die Filter können entsprechend der ausgesuchten Architektur Tiefpass- oder Bandpasscharakter annehmen.Die Idee rekonfigurierbarer Frequenzparameter wurde bereits mit Beginn moderner Filteranwendungen auf Grund geforderter Frequenzganggenauigkeit umgesetzt. Jedoch wurde die Parameterrekonfiguration üblicherweise nur in einem begrenzten Bereich um die Idealwerte herum vorgenommen. Das Ziel der vorgestellten Forschungsarbeit ist es, diese klassischen Filterstrukturen mit einfacher Selbstkorrektur in über große Frequenzbereiche voll rekonfigurierbare Filter zu transformieren. Idealerweise werden die Frequenzparameter kontinuierlich variiert weswegen sich die Implementierung in reellen Schaltkreisen als schwierig erweist. Deshalb ist es üblicherweise ausreichend, ein diskretes Steuerschema mit kleinen Schrittweiten zu verwenden.Es gibt verschiedene Methoden, variable Frequenzparameter zu implementieren. Die meisten Schemata verwenden Widerstands- und Kondensatorfelder, die entsprechend eines Kodes geschaltet werden. Die in dieser Arbeit vorgestellte Implementierung eines Tiefpassfilters nutzt ein spezielles Umschaltschema, welches für die quasi-lineare Frequenzvariation bei Darstellung über logarithmischen Axen optimiert wurde. Es beinhaltet weiterhin die Möglichkeit, Fehler zu kompensieren, die durch Bauelementtoleranzen und Temperaturschwankungen hervorgerufen werden.Ein weiteres interessantes Thema betrifft die Implementierung steuerbarer Bandpassfilter, die für Empfänger mit Zwischenfrequenzabtastung geeignet sind. Die Betrachtung beschränkt sich hierbei auf die Durchführbarkeit und Flexibilität verschiedener Bandpassfilterarchitekturen. Auf Grund hoher Frequenzanforderungen liegt der Schwerpunkt auf Filtern, die auf Transkonduktanzverstärkern und Kondensatoren basieren
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Csipkes, Gabor-Laszlo. "Integrated realizations of reconfigurable low pass and band pass filters for wide band multi-mode receivers." Doctoral thesis, [S.l.] : [s.n.], 2005. http://deposit.ddb.de/cgi-bin/dokserv?idn=979677483.
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Li, Rong Ding. "A very wideband operational transconductance amplifier and capacitor (OTA-C) filter in CMOS VLSI technology." Thesis, 2003. http://spectrum.library.concordia.ca/2281/1/MQ83870.pdf.
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Wideband analog signal processing systems are useful in many applications, such as telecommunication, multimedia and consumer electronics. An analog filter is an important subsystem in such systems. Among the existing realization methods of continuous-time domain integrated analog filter, OTA-C topology is the most useful one, and it offers good performances with lower power consumption and high frequency operation. In this work, several existing OTA cells selected from literature are studied. Based on the comparison of g m value, bandwidth, output resistance, and dynamic range in terms of DC power dissipation and substrate area requirement, an optimum OTA cell is selected for the implementation of wideband OTA-C filter. Using selected OTA cell as the basic building block, a fully differential highly linear, very wideband sixth-order filter is designed using 0.18 om CMOS technological process. Three identical biquads are connected using PRB (Primary Resonator Block) technique to realized a sixth order bandpass filter that has a passband from 2 MHz to 400 MHz. Simulation results show that the filter consumes 80.70 mW of power with supply voltages of ±1.5 V. The dynamic range for % THD with 0.42 V (peak-to-peak) at 100 MHz is close to 40 dB and the third order intermodulation intercept (IIP 3 ) is -27.29 dBW (i.e. 2.71 dBm)
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Mobarak, Mohamed Salah Mohamed. "Linearization and Efficiency Enhancement Techniques for RF and Baseband Analog Circuits." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8836.
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High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption.
An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth.
Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power.
High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels.
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Kim, Ju Sung. "Broadband RF Front-End Design for Multi-Standard Receiver with High-Linearity and Low-Noise Techniques." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10512.
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Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications.
In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies.
A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback.
For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind.
A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver.
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"Operational transconductance amplifier with a rail-to-rail constant transconductance input stage." 2002. http://library.cuhk.edu.hk/record=b5891100.
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Chan Shek-Hang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 94-97).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Table of Contents --- p.v
List of Figures --- p.ix
List of Tables --- p.xiii
Chapter Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Overview --- p.1
Chapter 1.2 --- Significance of the research --- p.2
Chapter 1.3 --- Objectives --- p.3
Chapter 1.4 --- Thesis outline --- p.4
Chapter Chapter 2 --- Background theory --- p.5
Chapter 2.1 --- Introduction --- p.5
Chapter 2.2 --- Electrical properties of MOS transistors --- p.5
Chapter 2.2.1 --- Strong inversion --- p.5
Chapter 2.2.2 --- Weak inversion --- p.6
Chapter 2.2.3 --- Moderate inversion --- p.8
Chapter 2.2.4 --- The transistors biased in this work --- p.8
Chapter 2.3 --- Rail-to-rail signals --- p.8
Chapter 2.4 --- Rail-to-rail operational amplifier --- p.10
Chapter 2.4.1 --- Rail-to-rail differential input pairs --- p.10
Chapter 2.4.1.1 --- Principle --- p.10
Chapter 2.4.1.2 --- Two stage operational amplifier --- p.13
Chapter 2.4.2 --- Folded-cascode gain stage --- p.14
Chapter 2.5 --- The nature of operational amplifier distortion --- p.16
Chapter 2.5.1 --- The total harmonic distortion --- p.17
Chapter Chapter 3 --- Constant transconductance rail-to-rail input stage --- p.20
Chapter 3.1 --- Introduction --- p.20
Chapter 3.2 --- Review of constant-gm input stage --- p.20
Chapter 3.2.1 --- Rail-to-rail input stages with current-based gm control --- p.20
Chapter 3.2.1.1 --- gm controlled by three-times current mirror --- p.21
Chapter 3.2.1.2 --- gm controlled by square root current control --- p.23
Chapter 3.2.1.3 --- gm controlled by using current switches only --- p.25
Chapter 3.2.2 --- Rail-to-rail input stages with voltage-based gm control --- p.28
Chapter 3.2.2.1 --- gm controlled by an ideal zener diode --- p.28
Chapter 3.2.2.2 --- gm controlled by two diodes --- p.30
Chapter 3.2.2.3 --- gm controlled by an electronic zener --- p.31
Chapter 3.3 --- Conclusion --- p.32
Chapter Chapter 4 --- Proposed constant transconductance rail-to-rail input stage --- p.34
Chapter 4.1 --- Introduction --- p.34
Chapter 4.2 --- Principle of the conventional input stage --- p.35
Chapter 4.2.1 --- Translinear circuit --- p.35
Chapter 4.3 --- Previous work --- p.36
Chapter 4.3.1 --- Input bias circuit --- p.36
Chapter 4.3.2 --- Weak inversion operation --- p.38
Chapter 4.3.3 --- Power up problem --- p.43
Chapter 4.4 --- Operational transconductance amplifier with proposed input biased stage --- p.47
Chapter 4.4.1 --- Proposed input biased stage architecture --- p.47
Chapter 4.4.2 --- Proposed input biased stage with 2 gm control circuits --- p.50
Chapter 4.4.3 --- OTA with proposed input biased stage --- p.51
Chapter Chapter 5 --- Simulation Results --- p.54
Chapter 5.1 --- Introduction --- p.54
Chapter 5.2 --- DC bias simulation --- p.54
Chapter 5.2.1 --- Total transconductance variation --- p.54
Chapter 5.2.2 --- Power consumption --- p.56
Chapter 5.3 --- AC simulation --- p.56
Chapter 5.3.1 --- Open-loop gain --- p.57
Chapter 5.3.2 --- Gain-bandwidth product --- p.59
Chapter 5.3.3 --- Phase margin --- p.59
Chapter 5.4 --- Transient simulation --- p.60
Chapter 5.4.1 --- Voltage follower --- p.60
Chapter 5.4.2 --- Total harmonic distortion --- p.62
Chapter 5.4.3 --- Step response --- p.65
Chapter 5.5 --- Conclusion --- p.67
Chapter Chapter 6 --- Layout Consideration --- p.68
Chapter 6.1 --- Introduction --- p.68
Chapter 6.2 --- Substrate tap --- p.68
Chapter 6.3 --- Input protection circuitry --- p.69
Chapter 6.4 --- Die micrographs of the OTA --- p.71
Chapter Chapter 7 --- Measurement Results --- p.74
Chapter 7.1 --- Introduction --- p.74
Chapter 7.2 --- DC bias measurement results --- p.74
Chapter 7.2.1 --- Total transconductance variation --- p.74
Chapter 7.2.2 --- Power consumption --- p.77
Chapter 7.3 --- AC measurement results --- p.78
Chapter 7.3.1 --- Open-loop gain --- p.78
Chapter 7.3.2 --- Gain-bandwidth product --- p.81
Chapter 7.3.3 --- Phase margin --- p.81
Chapter 7.4 --- Transient measurement result --- p.82
Chapter 7.4.1 --- Voltage follower --- p.82
Chapter 7.4.2 --- Total harmonic distortion --- p.85
Chapter 7.4.3 --- Step response --- p.87
Chapter 7.5 --- Conclusion --- p.88
Chapter Chapter 8 --- Conclusion --- p.90
Chapter 8.1 --- Contribution --- p.90
Chapter 8.2 --- Further development --- p.91
Chapter Chapter 9 --- Appendix --- p.92
Chapter Chapter 10 --- Bibliography --- p.94
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Jiao, Weishing, and 焦偉信. "Low-Power Two-Stage CMOS Operational Transconductance Amplifier." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/11329314256451004703.
Full textAbstract:
碩士國立高雄海洋科技大學
微電子工程研究所
100
Two-stage operational transconductance amplifiers (OTA) operated in the ±1.5V power supply range were designed and fabricated using the TSMC 0.35um technology. Both NMOS and PMOS differential input topologies were designed and its circuit characteristics were compared and analyzed. HSPICE simulated results showed following characteristics for both NMOS and PMOS OTA circuits: Power consumption, 0.19mW, 0.28mW; Phase margin, 53°, 45°; Unity gain band width, 4.4MHz, 1.6MHz; Open loop gain, 76.6dB, 73.2dB; Input common mode range, ±1.3V, ±1.3V and Output swing, 2.64V, 2.57V, respectively. To decrease mismatch (due to process variations) effect and reduce the offset voltage, the “Common Centroid" method with multi-finger structures were employed throughout the layout and floorplan. Moreover, both NMOS and PMOS devices were proper isolated with guard rings to avoid noise coupling effects. On chip measurement show that despite basic NMOS OTA circuit functioned properly, there are still room for improvements. For example, when the close loop gain = 10 and the input signal large than 0.04V, some devices in the circuit were turned off. Furthermore, due to limitation of slew rate, the output signal started to show signs of distortion when the input signal large than 17KHz.
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Yang, Kun-Yin, and 楊昆穎. "The Research of Operational Transconductance Amplifier and Current Follower." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/ut6t9k.
Full textAbstract:
碩士中原大學
電子工程研究所
91
There are two emphases in this thesis: the transformation of voltage-mode to current-mode OTA circuit in chapter 3 and low voltage CMOS class AB current follower in chapter 4. In chapter 3, we use a simple and predictable adjoint transformation to transfer the voltage-mode OTA circuit into current-mode one that we anticipated. The transfer function of the voltage-mode OTA circuit will be identical to that of the current-mode OTA circuit and vice versa. This adjoint transformation is very simple. When transfer, we need only BOTA and OTA as active elements and passive elements need no change at all. Also, the circuit structure will be slightly changed; it is the major advantage of this transformation. Alternatively, a new low voltage class AB current follower is presented in chapter 4. It’s the improvement in accordance with defects of the circuit structure at present. The main merits of this circuit are large input current and wide operating bandwidth and operating voltage. Moreover, the input resistances of both positive- and negative-type current followers are 4Kohms, and the output resistances are about 100Kohms. The input current range is -400uA to 400uA. The bandwidth of the positive current follower is about 225MHz while that of the negative one is 158MHz, and the harmonic distortion of the positive current follower is about 2.38% while that of the negative one is 2.39%. The characteristics of the circuit exhibit larger progress than the circuits proposed in the past. So that the circuit has less limitations in applications and the characteristics of the circuit are indirectly improved. Thus, it is more practicable to develop the circuit system with high efficiency.
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Tom, Strung-Ane, and 唐春安. "The Design and Applications of Highly-Linear Operational Transconductance Amplifier." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/65721925636355022401.
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Wang, Chao-Ho, and 王朝河. "A Novel Voltage-Control Sinusoidal Oscillator using Operational Transconductance Amplifier." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/43060234384192057704.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
90
Abstract In this research, we intend to develop a sinusoidal VCO with low harmonic distortion. A new sinusoidal VCO is developed with only two OTAs. The number of OTAs is fewer than that previously presented in other papers. The oscillator will be easy to debug and the complexity of the oscillator can be reduced. An AGC control mechanism is applied to the VCO to control the oscillation amplitude and to reduce the harmonic distortion. The oscillation is designed with the frequency around 100MHz and the oscillation amplitude is around 100mV. The simulation results and the problem encountered are discussed.
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Lee, Kun-Chu, and 李昆築. "An Integrated Operational Transconductance Amplifier Design for Doppler Ultrasound System." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/w9g7n5.
Full textAbstract:
碩士國立中央大學
電機工程學系
106
In recent years, the global aging has driven the development of the therapeutic and auxiliary medical device market, especially the use of home care, such as blood glucose meters, blood pressure monitors, etc. Therefore, it is very important to develop care equipment with mobility, miniaturization, and low power consumption. This paper presents the design of the probe driving circuit in Doppler ultrasound system for blood flow sensing, which is an operational- transconductance-amplifier(OTA) with high current, high linearity, and low power consumption. Three circuit architectures are presented, namely conventional OTA architecture, complementary OTA architecture, and OTA with slew rate enhancer. The circuits in this paper are designed and implemented with an integrated circuit. They were fabricated in VIS 0.5μm SOI 2P4M 5V CMOS process. The supply voltage is 5V, and the load capacitor is 2nF. The area of complementary OTA architecture is 850*560µm2. The area of OTA with slew rate enhancer is 812.5*532.07μm2. The IC measurement achieves 5MHz sine wave signal and 10MHz sine wave signal, respectively. The slew-rate is 68V/μs and 100V/μs, and the static power consumption is 140mW and 48mW, respectively. For the large capacitive load of ultrasound probes, using the architectures proposed in this paper to drive can reduce the overall system power consumption. The development of miniaturized, wearable or mobile medical products for battery-powered can extend the life cycle, and the stability can be greatly improved.
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Durisety, Chandra Sekhar Acharyula. "A high gain multi-stage operational amplifier using compound transconductance element." 2006. http://etd.utk.edu/2006/DurisetyChandra.pdf.
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Wang, Wei-Chiang, and 王煒強. "Testable Design and Implementation of Operational Transconductance Amplifier-Capacitor Based Circuits." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/31880000026438702132.
Full textAbstract:
碩士國立成功大學
電機工程學系
87
The operational transconductance amplifier-capacitor (OTA-C) technique has become today the technique of choice for high-frequency circuits. However, similar to other analog circuits, testing an OTA-C based circuit is a difficult problem. In recent years, this problem becomes even more difficult because of the increase of circuit complexity. In this thesis, a systematic approach to design testable OTA-C based circuits is proposed. We first derive a general form for the state equation of OTA-C low-pass filters and OTA-C oscillators. Then, we present a general current-mode testable architecture for OTA-C based circuits. A universal procedure for the testable OTA-C based circuits design based on this architecture is given. By using this procedure, we can easily and fastly add the test circuit to the OTA-C based circuits. The basic idea of this method is as follows. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. Besides, the testable OTA-C based circuits designed with multiple $g_m$ values are also proposed and the threshold determination is also discussed in this thesis. Finally, the simulation and experimental results are given. A test chip has been fabricated using a 0.5$\mu$m, 2P2M CMOS technology. These results show that our design has the following advantages: 1) easy to design and implement; 2) high accuracy in error detection; 3) little impact on the circuit performance of the CUT; 4) high (concurrent) error detection speed; 5) small area overhead.
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Chen, Hung-chang, and 陳弘昌. "A Linearity Improved and Digitally Programmable Operational Transconductance Amplifier for Gm-C Filter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/63599032971070667902.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
95
In this thesis, a linearity improved and digitally programmable operational transconductance amplifiers (OTA) for Gm-C filter has been designed and implemented in a 0.35-µm 2P4M CMOS process. In order to improve the linearity of OTA, we used an adaptive biasing technique. In addition, the transconductance of OTA can be controlled by our proposed digitally programmable current mirror technique. A second-order bandpass filter was designed to verify the linearity and transconductance of OTA by using our proposed techniques. The digitally programmable OTA has been simulated by circuit simulator, HSPICE. While the sampling frequency and input frequency are 50 MHz and 10 MHz respectively, the signal-to-noise and distortion ratio (SNDR) of the digitally programmable OTA is 61 dB. In our bandpass filter, the specification of 56-dB third-order intermodulation (IM3) was also achieved with input frequency mixed 9 MHz and 10 MHz.
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pan, sheng-wen, and 潘聖文. "Low Power Rail-to-Rail Input Stage Operational Transconductance Amplifier for Biomedical System Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/62665708499160164958.
Full textAbstract:
碩士中原大學
電子工程研究所
97
The development of integrated circuit (IC) technologies for biomedical system applications has been widely used in recent years. Moreover, it has brought a considerable amount of portable and implantable biomedical equipment. In order to satisfy with ambulatory functions, low power and low voltage has been essential condition for the front-end circuit. Hence, as a basic analog building block, operational transconductance amplifier (OTA) has a limited voltage headroom due to the low battery-voltage characteristics, and it thereby needs rail-to-rail input signal swing to maximize the signal operational range. The paper present a low-power low-voltage rail-to-rail operational transconductance amplifier (OTA), which combined bulk-driven differential pair, PMOS differential pair, shunt down circuit and folded cascode load. Based on the proposed topology, the low voltage OTA with rail-to-rail input common-mode range is achieved. The scheme not only avoids leakage current of conventional bulk-driven circuit but also reduces power consumption. The simulated power consumption of the OTA is 23μW under conditions of 0.9V supply voltage in TSMC 0.35μm Mixed Signal 2P4M Polycide 3.3/5V technology.
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Fu, Ming-Kai, and 傅明楷. "A Novel Low Voltage Operational Transconductance Amplifier Design Based on the Common-Mode Feed-Forward Technology." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/32598379538616172488.
Full textAbstract:
碩士逢甲大學
電子工程所
97
A CMOS pseudo differential operational transconductance amplifier (OTA) has been proposed in this study. It can operate at very low supply voltage with high linearity and high output impedance. Besides, it enhances the common mode rejection ratio (CMRR) by using a special common mode feed forward (CMFF) structure. The simulation results show that the CMRR is 79.6dB and this circuit has an open loop gain of 57.7dB under the supply voltage at 1.1V only. The unity gain frequency is 2.86MHz and it consumes only 63μW for the power dissipation. The chip has been manufactured in a 0.35μm-CMOS technology. The chip area is 0.15x0.1 mm2.
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Abu, Patricia Angela R., and 艾翠霞. "Design of 60-Hz Notch Filter and Operational Transconductance Amplifier for Minimizing Power Line Interferencein Electrocardiogram Signals." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/35512938198195704092.
Full textAbstract:
碩士中原大學
電子工程研究所
97
A 60-Hz notch filter is designed to minimize the power line interference on electrocardiograph signals. A high CMRR and low noise operational transconductance amplifier was first designed which are major parameters for noise elimination on biomedical signals. The OTA was fully tested on all process corners for both MIMOS 0.35µm and TSMC 0.35µm technology and was fabricated using TSMC 0.35µm technology. The OTA has a CMRR of 138.28dB and 137.34dB for MIMOS and TSMC pre layout simulation respectively. TSMC post layout simulation shows a CMRR of 135.74dB. The noise margin on the other hand has a value of 2.87mV2/Hz and 486.90nV2/Hz for MIMOS and TSMC pre layout simulation respectively and as high as 488.26nV2/Hz for TSMC post layout simulation. In comparison with previously developed OTAs, the designed OTA has a high AC gain of 88.34dB, a high phase margin of 86.34o and ICMR of 2.64V. The OTA has a layout area of 101 x 256 um2 without the bonding pads and 788 x 814 um2 with bonding pads. The OTA chip was tested and testing results shows an output swing of -1.65V to +1.65V and ICMR of 2.43V. The designed high CMRR and low noise OTA was used in the design of the 60-Hz notch filter. The commonly used RC Twin T notch filter configuration was used in the initial design of the with its center frequency at 60.11Hz. It has an attenuation of -60 dB and a Q factor of 0.25. A bootstrapped Twin T configuration was then designed in order to increase the Q factor of the notch filter. The additional resistor in conventional bootstrapped Twin T was eliminated and was replaced by a single transistor thus having the possibility for chip implementation. The bootstrapped Twin T has a Q factor of 3.48 which is 13.92 times as that of unaided Twin T configuration. The Q of the bootstrapped Twin T is adjusted through the size of the transistor. The large resistor component for the RC Twin T notch filter was replaced with its switched capacitor equivalent. All four switched capacitor resistor equivalent configuration was tested – parallel, series, series-parallel and bilinear switched capacitor configuration. Through the use of switches, capacitors and an external clock, resistors can be replaced thus providing the possibility of chip implementation.
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Chang, Yen-Shuo, and 張晏碩. "On the Design of a Low Voltage Pseudo Differential Operational Transconductance Amplifier with Common Mode and HD3 Feed Forward Cancellation Technologies." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/40563080582167111030.
Full textAbstract:
碩士逢甲大學
電子工程所
100
A pseudo differential Operational Transconductance Amplifier (OTA) has been proposed in this research. This OTA can operate at low supply voltage with high linearity. Here, we use two technologies, one of them is common mode feed forward and the other is HD3 feed forward. Simulation results show that the common mode rejection ratio (CMRR) is 68.6dB and third harmonic distortion (HD3) is -66.6dB. This OTA consumes 75.8μW for the power dissipation. The chip has been manufactured in a 0.18μm-CMOS technology. The chip area is 0.69x0.38 mm2.