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1

Boyd, Richard L. (Richard Lyman). "An optical phase locked loop for semiconductor lasers." Thesis, Massachusetts Institute of Technology, 1988. http://hdl.handle.net/1721.1/35943.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1988.<br>Title as it appeared in MIT Graduate list, June, 1988: An optical phase locked loop.<br>Includes bibliographical references.<br>by Richard L. Boyd.<br>M.S.
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2

Beaudoin, Francis. "Design and implementation of a gigabit-rate optical, receiver and a digital frequency-locked loop for phase-locked loop based applications." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79996.

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The large demand for high-bandwidth communication systems has brought down the cost of optical system components. To be competitive in a crowded market, implementation of the different systems of an optical transceiver on a single chip has become mandatory.<br>CMOS technologies, especially state-of-the-art processes like the 0.18mum CMOS, permit integration of huge amounts of transistors per millimeter square. Furthermore, deep-submicron CMOS processes have similar RF performances to their traditional bipolar equivalent. It is therefore a small footstep to go to congregate high-speed an
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3

Kassa, Wosen Eshetu. "Modélisation électrique de laser semi-conducteurs pour les communications à haut débit de données." Thesis, Paris Est, 2015. http://www.theses.fr/2015PEST1016/document.

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Cette distinction est également valable pour le genre des individus (homme/femme). L'étude menée a montré que l'approche utilisant l'information spectrale des contours des phalanges permet une identification par seulement trois phalanges, à un taux EER (Equal Error Rate) inférieur à 0.24 %. Par ailleurs, il a été constaté « de manière surprenante » que la technique fondée sur les rapports de vraisemblance entre les phalanges permet d'atteindre un taux d'identification de 100 % et un taux d'EER de 0.37 %, avec une seule phalange. Hormis l'aspect identification/authentification, notre étude s'es
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4

Pinheiro, Ricardo Bressan. "Projeto de filtros tipo \"só-pólo\" para malhas de sincronismo de fase de alta frequência." Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-30112010-153611/.

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Apresenta-se a evolução dos sitemas de comunicação, com ênfase especial nos sistemas com tecnologia óptica. Discute-se a necessidade contínua do aumento de capacidade de tais sistemas de comunicação, e a consequente repercussão sobre os futuros sistemas ópticos. Em vista da necessidade do aumento de capacidade dos futuros sistemas de comunicação óptica, apresentam-se em seguida duas propostas recentes da literatura, sendo uma referente à realização de um gerador de pulsos ópticos estreitos, e a outra referente à implementação de um extrator de relógio realizado com técnicas ópticas. Apresenta-
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5

Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.

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Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analo
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6

Souder, William Dai Foster. "A low power 10 GHz phase locked loop for radar applications implemented in 0.13 um SiGe technology." Auburn, Ala, 2009. http://hdl.handle.net/10415/1631.

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7

Gdeisat, Munther Ahmad. "Fringe pattern demodulation using digital phase locked loops." Thesis, Liverpool John Moores University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.521754.

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8

Bordonalli, Aldario Chrestani. "Optical injection phase-lock loops." Thesis, University College London (University of London), 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.244183.

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9

Ratcliff, Marcus Dai Foster. "Phase locked loop analysis and design." Auburn, Ala, 2008. http://hdl.handle.net/10415/1452.

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10

Eklund, Robert. "Linearization of Voltage-Controlled Oscillators in Phase-Locked Loops." Thesis, Linköping University, Department of Science and Technology, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5366.

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<p>This is a thesis report done as part of the Master of Science in Electronics Design Engineering given at Linköping University, Campus Norrköping. The thesis work is done at Ericsson AB in the spring of 2005. The thesis describes a method of removing variations in the tuning sensitivity of voltage-controlled crystal oscillators due to different manufacturing processes. These variations results in unwanted variations in the modulation bandwidth of the phase-locked loop the oscillator is used in. Through examination of the theory of phase-locked loops it is found that the bandwidth of the loop
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11

Veillette, Benoît R. "On-chip characterization of charge-pump phase-locked loops." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0017/NQ44617.pdf.

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12

Stockmaster, Michael. "Tracking of multiple sinusoids using coupled phase-locked loops." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1412945248.

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13

Agaisse, Romain. "Auto-affinement spectral laser assisté par effet Brillouin." Electronic Thesis or Diss., Université de Rennes (2023-....), 2023. http://www.theses.fr/2023URENS091.

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La stabilité en fréquence des lasers est une propriété recherchée dans de nombreux domaines tels que les communications optiques, la spectroscopie ou encore la métrologie temps-fréquence. Dans ce contexte, l’institut Foton a mis au point un principe permettant d’auto-affiner spectralement un laser à des niveaux extrêmement bas. Pour cela on pompe un résonateur Brillouin non-réciproque ce qui génère une onde Stokes spectralement pure. L’ajout d’une boucle à verrouillage de phase qui contre-réagit sur la pompe permet alors d’éviter les sauts de modes du résonateur Brillouin tout
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14

Choi, Pyung. "An equivalent circuit structure macromodel for analog phase locked loops." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14875.

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15

Wilcock, Reuben. "Switched-current filters and phase-locked loops : methods and tools." Thesis, University of Southampton, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.416917.

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16

Pamarti, Sudhakar. "Enabling techniques for wide bandwidth fractional-N phase locked loops /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3091331.

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17

Thacker, Timothy Neil. "Phase-Locked Loops, Islanding Detection and Microgrid Operation of Single-Phase Converter Systems." Diss., Virginia Tech, 2009. http://hdl.handle.net/10919/29281.

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Within recent years, interest in the installation of solar-based, wind-based, and various other renewable Distributed Energy Resources (DERs) and Energy Storage (ES) systems has risen; in part due to rising energy costs, demand for cleaner power generation, increased power quality demands, and the need for additional protection against brownouts and blackouts. A viable solution for these requirements consists of installation of small-scale DER and ES systems at the single-phase (1Φ) distribution level to provide ancillary services such as peak load shaving, Static-VAr Compensation (STATCOM),
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18

Lee, Kun Seok. "Wideband phase-locked loops with high spectral purity for wireless communications." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44882.

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The objective of this research is to demonstrate the feasibility of the implementation of wideband RF CMOS PLLs with high spectral purity using deep sub-micron technologies. To achieve wide frequency coverage, this dissertation proposed a 45-nm SOI-CMOS RF PLL with a wide frequency range to support multiple standards. The PLL has small parasitic capacitance with the help of a SOI technology, increasing the frequency tuning range of a capacitor bank. A designed and fabricated chip demonstrates the PLL supporting almost all cellular standards with a single PLL. This dissertation also proposed a
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19

Sharkia, Ahmad. "On the design of type-i integer-n phase-locked loops." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/54504.

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The phase-locked loop (PLL) is an essential building block of modern communication and computing systems. In a wireless communication system, a PLL is almost always used as the local oscillator (LO) that synthesizes the required frequency for data transmission and reception. In wireline and optical communication systems, PLL-based clock and data recovery (CDR) circuits are often employed for the extraction of the clock signal from the incoming data signal, and aligning the recovered clock edge with the incoming data for optimal bit-error rate (BER) performance. Furthermore, in microprocessor a
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20

Watson, David Rae. "Application of phase locked loops to rapid acquisition in satellite communications." Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387068.

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21

Li, Shenggao. "High Performance GHZ RF CMOS IC's for Integrated Phase-Locked Loops." The Ohio State University, 2000. http://rave.ohiolink.edu/etdc/view?acc_num=osu1392372325.

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22

Zhu, Peiqing. "Design and characterization of phase-locked loops for radiation-tolerant applications." Ann Arbor, Mich. : ProQuest, 2008. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3331229.

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Thesis (Ph.D. in Electrical Engineering)--S.M.U.<br>Title from PDF title page (viewed Mar. 16, 2009). Source: Dissertation Abstracts International, Volume: 69-11, Section: B Adviser: Ping Gui. Includes bibliographical references.
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23

Kim, Seongwon. "Built-in self-test technique for high-speed phase-locked loops /." Thesis, Connect to this title online; UW restricted, 2001. http://hdl.handle.net/1773/5957.

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24

Thain, Walter E. "A methodology for modeling noise and spurious responses in phase-locked loops." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/13462.

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25

Upadhyaya, Parag. "A 5 GHZ low power, low jitter and fast settling phase locked loop architecture for wireline and wireless transceiver." Online access for everyone, 2008. http://www.dissertations.wsu.edu/Dissertations/Summer2008/P_Upadhyaya_072308.pdf.

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26

Thayaparan, Subramaniam. "Delay-locked loop techniques in direct sequence spread-spectrum receivers." Thesis, Hong Kong : University of Hong Kong, 1999. http://sunzi.lib.hku.hk/hkuto/record.jsp?B21904108.

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27

Bachmann, Adrian H. "Phase-locked Fourier domain optical coherence tomography /." Lausanne : EPFL, 2007. http://library.epfl.ch/theses/?nr=3847.

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Thèse Ecole polytechnique fédérale de Lausanne EPFL, no 3847 (2007), Faculté des sciences et techniques de l'ingénieur STI, Programme doctoral Photonique, Institut d'imagerie et optique appliquée IOA (Laboratoire d'optique biomédicale LOB). Dir.: Theo Lasser, Rainer Leitgeb.
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28

Davis, R. G. "Two-port millimetre wave oscillators and their stabilisation with phase-locked loops." Thesis, Lancaster University, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383542.

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29

Hsiao, Sen-Wen. "Built-in test for performance characterization and calibration of phase-locked loops." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51790.

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The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator
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30

Barat, Aakriti. "Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1483676715726685.

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31

Leung, Chi Tak. "Design of 1-V CMOS RF phase-locked loops and frequency synthesizers /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20LEUNG.

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32

Hallal, Ayman. "Génération d'ondes millimétriques et submillimétriques sur des systèmes fibrés à porteuses optiques stabilisées." Thesis, Rennes 1, 2017. http://www.theses.fr/2017REN1S005/document.

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Je rapporte dans ce manuscrit une étude théorique et expérimentale d’une source compacte, fiable et bas coût d’ondes électromagnétiques continues et cohérentes de 30 Hz de largeur de raie, accordables de 1 GHz à 500 GHz par pas de 1 GHz. Ces ondes sont générées par un photo-mélange de deux diodes lasers DFB (Distributed Feedback) très accordables autour de 1550 nm, stabilisées avec des polarisations orthogonales sur une même cavité Fabry-Perot optique fibrée. J’ai conçue des électroniques de correction très rapides pour chaque laser permettant d’avoir une bande passante d’asservissement de 7 M
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33

Vong, Chun-yin. "Performance study of uniform sampling digital phase-locked loops for [Pi]/4-differentially encoded quaternary phase-shift keying /." Hong Kong : University of Hong Kong, 1998. http://sunzi.lib.hku.hk/hkuto/record.jsp?B20007164.

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34

Inberg, R. Brandon. "Enhanced step mode FTIR position control." Thesis, Montana State University, 2005. http://etd.lib.montana.edu/etd/2005/inberg/InbergR1205.pdf.

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35

Cheng, Shanfeng. "Design of CMOS integrated phase-locked loops for multi-gigabits serial data links." Texas A&M University, 2006. http://hdl.handle.net/1969.1/4954.

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High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyze
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36

Kam, Brandon Ray. "(VDL)² : a jitter measurement built-in self-test circuit for phase locked loops." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/42119.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (p. 77-79).<br>This paper discusses the development of a new type of BIST circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a nominal jitter resolution of 10 ps with a capture range of +
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37

Chau-Chiun, Huang, and 黃超群. "Performance Analysis of Homodyne Phase-Locked Loops in Coherent Optical Fiber Communication Systems." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/16572851101593667623.

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碩士<br>國立清華大學<br>電機工程研究所<br>82<br>In this thesis, we firstly report the importance of the optimum phase deviation between mark-state and space-state bits in a PSK homodyne system with a balanced phase-locked- loop (PLL) receiver. The signal power penalty incurred by improper use of phase deviations is evaluated. It is found that such power penalty can amount to larger than 1.5 dB in a 10 Gbits/sec system. In the second part of this thesis, we explore the waveform distortion in
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38

Chin-Chung, Chou, and 周晉崇. "Performance Analysis of Balanced Phase-Locked Loops in Long- Haul Optical Fiber Communication Systems : Design Considerations." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/13860008342830761879.

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碩士<br>國立清華大學<br>電機工程研究所<br>81<br>We analyze the performance of a balanced PSK homodyne receiver accounting for the impacts of laser phase noise,data-to- phaselock crosstalk, shot noise and the noise induced by cascaded optical amplifiers. Of most interest in this thesis is the effect of accumulated optical amplifier noise on the performance of a phase-locked-loop. Due to such effect, the loop natural frequency should be properly chosen in order to reach an optimum system performance. It is
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39

Sharma, Jahnavi. "CMOS Signal Synthesizers for Emerging RF-to-Optical Applications." Thesis, 2018. https://doi.org/10.7916/D85Q66Z4.

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The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications li
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40

Nagarjun, K. P. "Generation and Bandwidth Scaling of silicon modulator based Integrated High Repetition rate Optical Frequency Combs." Thesis, 2020. https://etd.iisc.ac.in/handle/2005/4842.

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Optical Frequency Combs (OFC) are laser sources that consist of discrete, equally spaced lines in frequency space, have found extensive use in metrology, spectroscopy, sensing and optical communications. Generation of frequency combs in integrated platforms is of interest due to their potential use as Wavelength Division Multiplexing (WDM)sources for transmitters in high-speed optical communication applications. In this thesis, we explore the following aspects: First, using electro-optical simulations we examine the feasibility of optical frequency comb generation using strong phase modu
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41

Chuang, Kung-chang, and 莊恭彰. "A design of Phase-Locked Loop for the application in optical transmitter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/9z6t2n.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>94<br>This thesis describes a design of PLL clock generator for optical transmitter in a standard CMOS process. It can produce multiple-times clocks for a multiplexer which combines the parallel sequences of data at lower rates to generate a single high-speed serial signal. Our design methodology, simulation, and measurement can be summarized as follows. First, in order to analyze the PLL clock generator, we have established the loop parameters. The parameters effect on the PLL transient characteristic has been studied. Besides, noise sources were introduced into th
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42

Chen, Yi-Ju. "An integrated CMOS optical receiver with clock and data recovery Circuit." Diss., 2005. http://hdl.handle.net/2263/24807.

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Traditional implementations of optical receivers are designed to operate with external photodetectors or require integration in a hybrid technology. By integrating a CMOS photodetector monolithically with an optical receiver, it can lead to the advantage of speed performance and cost. This dissertation describes the implementation of a photodetector in CMOS technology and the design of an optical receiver front-end and a clock and data recovery system. The CMOS detector converts the light input into an electrical signal, which is then amplified by the receiver front-end. The recovery system su
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43

Iyer, S. P. Anand. "Phase Synthesis Using Coupled Phase-Locked Loops." 2008. https://scholarworks.umass.edu/theses/182.

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Phase Synthesis is a fundamental operation in Smart Antennas and other Phased Array systems based on beamforming. There are increasing commercial applications for Integrated Phased Arrays due to their low cost, size and power and also because the RF and digital signal processing can be performed on the same chip. These low cost beamforming applications have augmented interest in Coupled Phase Locked Loop (CPLL) systems for Phase Synthesis. Previous work on the implementation of Phase Synthesis systems using Coupled PLLs for low cost beamforming had the constraint of a limited phase range of ±9
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44

Yogesh, Prasad K. R. "Generation of Modulated Microwave Signals using Optical Techniques for Onboard Spacecraft Applications." Thesis, 2013. http://etd.iisc.ac.in/handle/2005/2849.

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This thesis deals with optical synthesis of unmodulated and modulated microwave signals. Generation of microwave signals based on optical heterodyning is discussed in detail. The effect of phase noise of laser on heterodyned output has been studied for different phase noise profiles. Towards this, we propose a generic algorithm to numerically model the linewidth broadening of a laser due to phase noise. Generation of microwave signals is demonstrated practically by conducting an optical heterodyning experiment. Signals ranging in frequency from 12.5 MHz to 27 GHz have been generated. Limitat
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45

Yogesh, Prasad K. R. "Generation of Modulated Microwave Signals using Optical Techniques for Onboard Spacecraft Applications." Thesis, 2013. http://etd.iisc.ernet.in/handle/2005/2849.

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This thesis deals with optical synthesis of unmodulated and modulated microwave signals. Generation of microwave signals based on optical heterodyning is discussed in detail. The effect of phase noise of laser on heterodyned output has been studied for different phase noise profiles. Towards this, we propose a generic algorithm to numerically model the linewidth broadening of a laser due to phase noise. Generation of microwave signals is demonstrated practically by conducting an optical heterodyning experiment. Signals ranging in frequency from 12.5 MHz to 27 GHz have been generated. Limitat
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46

Chen, Yen-Wen. "Low Power Techniques for Phase-Locked Loops." 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2807200400113100.

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47

Chen, Yen-Wen, and 陳彥文. "Low Power Techniques for Phase-Locked Loops." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/72y8ds.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>92<br>The goal of this work is to use a standard 0.35-μm CMOS process to implement the phase-locked loops with low power consumption, and the new methods of these three topics, reducing the power consumption of the VCO and divider, reducing the switching power of the output buffer and a dividerless PLL, are presented. The presented PLL include PFD, charge pump circuit, VCO, and divider, successfully reduces the power consumption on VCO and divider by regulated supply technique and novel schematic. To reduce the dynamic switching power consumption, we propose a new
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48

Lin, Jian-Da, and 林建達. "Delay-Locked Loops with phase error calibration." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/11571946077067957002.

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碩士<br>長庚大學<br>電機工程學系<br>100<br>Because of the development of technology, smaller scale of MOSFET, channel effect, low supply voltage, and process-voltage-temperature variations, circuit design has become more and more difficult. The synchronous problem between circuits is undoubtedly important in system integration. Delay-locked loop is designed and implemented to solve the problem of clock synchronization and tracking. Delay-locked loop is widely used because of easy design, stability, and low power consumption. This thesis presents a new method to improve DLL’s phase error. Due to the curren
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49

Chien-Cheng, Huang, and 黃建成. "Identifying Resonant Structure with Phase Locked Loops." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/05691156216365104340.

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碩士<br>國立交通大學<br>機械工程系所<br>96<br>This study presents a simple method to evaluate the natural frequency and the damping ratio of a second order system considering resonant excitation. Structural imperfection and the viscous damping can dramatically reduce the performance of micro-electromechanical systems (MEMS) in gyro or accelerometer applications. Using the phase locked loops (PLL) as the electrical driving circuit of the MEMS devices, the tracking frequency can be used to calculate the natural frequency and the damping ratio. The proposed method is implemented using a simple circuit.
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50

陳添欑. "The Transient Response of Phase-Locked Loops." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/64071139970715905349.

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碩士<br>國立臺灣大學<br>電機工程研究所<br>74<br>This thesis discusses the frequency step response and the phase step response of first-order and second-order phase-locked loops under no noise condition. With these studies, we may understand (1)If the PLL is initially locked, under what conditions will the PLL remain locked? (2)How to choose the PLL parameters to minimize the transient time? First, we introduce the basic principles and basic functional blocks of PLL. Second, we make a linear mode analysis of the various configurations of PLL, then to solve their formulas of the frequency step response and t
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