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Journal articles on the topic 'Optimal circuit'
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1
Maslov, Dmitri. "Optimal and asymptotically optimal NCT reversible circuits by the gate types." Quantum Information and Computation 16, no. 13&14 (2016): 1096–112. http://dx.doi.org/10.26421/qic16.13-14-2.
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We report optimal and asymptotically optimal reversible circuits composed of NOT, CNOT, and Toffoli (NCT) gates, keeping the count by the subsets of the gate types used. This study fine tunes the circuit complexity figures for the realization of reversible functions via reversible NCT circuits. An important consequence is a result on the limitation of the use of the T-count quantum circuit metric popular in applications.
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Dash, Sandeep K., Bishnu Prasad De, Pravin K. Samanta, et al. "Optimal Design of Voltage Reference Circuit and Ring Oscillator Circuit Using Multiobjective Differential Evolution Algorithm." Journal of Electrical and Computer Engineering 2023 (August 8, 2023): 1–11. http://dx.doi.org/10.1155/2023/7621594.
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This paper deals with the optimal design of different VLSI circuits, namely, the CMOS voltage reference circuit and the CMOS ring oscillator (RO). The optimization technique used here is the multiobjective differential evolution algorithm (MDEA). All the circuits are designed for 90 nm technology. The main objective of the CMOS voltage reference circuit is to minimize the voltage variation at the output. The targeted value of the reference voltage is 550 mV. A CMOS ring oscillator (RO) is designed depending on the performance parameters such as power consumption and phase noise. The optimal transistor sizing of each circuit is obtained from MDEA. Each circuit is implemented in SPICE by taking the optimal dimensions of the transistors, and the performance parameters are achieved. The designed voltage reference circuit achieves a reference voltage of 550 mV with 600 nW power dissipation. The reference voltage variation of 8.18% is observed due to temperature variation from −40°C to + 125°C. The MDEA-based optimal design of RO oscillates at 2.001 GHz frequency, has a phase noise of −87 dBc/Hz at 1 MHz offset frequency, and consumes 71 μW power. This work mainly aims to optimize the MOS transistors’ sizes using MDEA for better circuit performance parameters. SPICE simulation has been carried out by using the optimal values of MOS transistor sizes to exhibit the performance parameters of the circuit. Simulation results establish that design specifications are closely met. SPICE results show that MDEA is a better technique for the optimal design of the above-mentioned VLSI circuits.
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Kim, Kyunghun, Se Hyun Kim, Hyungjin Cheon, et al. "Electrohydrodynamic-Jet (EHD)-Printed Diketopyrrolopyroole-Based Copolymer for OFETs and Circuit Applications." Polymers 11, no. 11 (2019): 1759. http://dx.doi.org/10.3390/polym11111759.
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We report the employment of an electrohydrodynamic-jet (EHD)-printed diketopyrrolopyrrole-based copolymer (P-29-DPPDTSE) as the active layer of fabricated organic field-effect transistors (OFETs) and circuits. The device produced at optimal conditions showed a field-effect mobility value of 0.45 cm2/(Vs). The morphologies of the printed P-29-DPPDTSE samples were determined by performing optical microscopy, X-ray diffraction, and atomic force microscopy experiments. In addition, numerical circuit simulations of the optimal printed P-29-DPPDTSE OFETs were done in order to observe how well they would perform in a high-voltage logic circuit application. The optimal printed P-29-DPPDTSE OFET showed a 0.5 kHz inverter frequency and 1.2 kHz ring oscillator frequency at a 40 V supply condition, indicating the feasibility of its use in a logic circuit application at high voltage.
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Aizik, Yoni, and Avinoam Kolodny. "Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints." VLSI Design 2011 (April 7, 2011): 1–13. http://dx.doi.org/10.1155/2011/845957.
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A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG) is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.
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Patel, K. N., I. L. Markov, and J. P. Hayes. "Optimal synthesis of linear reversible circuits." Quantum Information and Computation 8, no. 3&4 (2008): 282–94. http://dx.doi.org/10.26421/qic8.3-4-4.
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In this paper we consider circuit synthesis for $n$-wire linear reversible circuits using the C-NOT gate library. These circuits are an important class of reversible circuits with applications to quantum computation. Previous algorithms, based on Gaussian elimination and LU-decomposition, yield circuits with $O\left(n^2\right)$ gates in the worst-case. However, an information theoretic bound suggests that it may be possible to reduce this to as few as $O\left(n^2/\log\, n\right)$ gates.
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Jyoti, Amitabh Wahi, and S. B. L. Tripathi. "Study on Machine Learning Application in Quantum Circuit Synthesis." RESEARCH REVIEW International Journal of Multidisciplinary 10, no. 4 (2025): 06–13. https://doi.org/10.31305/rrijm.2025.v10.n4.002.
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In this Research Paper we have highlighted about the Study on Machine Learning Application in Quantum Circuit Synthesis. Quantum circuit synthesis, a fundamental task in quantum computing, involves designing efficient circuits to execute quantum algorithms on quantum computers. Machine learning techniques have been increasingly applied to enhance this process. One key area where machine learning excels is in optimizing quantum circuits for specific tasks. Quantum circuit synthesis often involves a large search space of possible circuit configurations, making it computationally intensive to find optimal solutions. Machine learning algorithms, such as reinforcement learning or genetic algorithms, can efficiently navigate this search space to identify high-performing circuit configurations. These algorithms learn from past experiences and iteratively improve their performance, gradually converging towards optimal solutions. Machine learning can aid in automating the design process by predicting the performance of quantum circuits based on their characteristics. By analyzing large datasets of quantum circuits and their corresponding performance metrics, machine learning models can identify patterns and correlations, enabling the prediction of circuit performance without the need for exhaustive simulations. Additionally, machine learning techniques can assist in error mitigation in quantum circuits. Quantum computers are susceptible to various types of errors, which can degrade the performance of quantum algorithms. Machine learning algorithms can analyze error patterns and devise strategies to mitigate them, leading to more reliable quantum circuits.
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Zhong, Jiu Ming, and Han Jun Liu. "Optimal Design of High Power LED Driving Circuit." Advanced Materials Research 490-495 (March 2012): 2555–58. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2555.
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The loss of high power LED is analyzed and calculated. It is pointed out that high power LED driving circuit is required to be designed in detail instead of using BCD to 7-segment decoder. An example with 5 inch LED is presented. Some decoder circuits are designed and compared showing that the MC1413 is the optimal one. Example circuits are designed. The experiment results are in positive to the analysis results showing the feasibility of the proposed methods.
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Deng, Jingxi. "Systematic Analysis and Research on Integrated Circuit Design Optimization." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 197–201. http://dx.doi.org/10.54097/q42hbs73.
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After decades of development of integrated circuits, there has been great progress in all aspects. These advances are reflected in the optimization of manufacturing processes and circuits. When designing a circuit, considering the production cost and the performance of the circuit, the optimal design of the circuit is always a very important link. In this paper, two kinds of optimization ideas are introduced. One is from the point of view of the physical design of the circuit, two methods are introduced, which are adjusting the input power and reducing the circuit device. The other is to optimize the circuit from the point of view of algorithm. Genetic algorithm and simulated annealing algorithm are introduced. After optimizing the circuit, the circuit energy consumption is reduced, the circuit delay is reduced, the circuit runs faster, and the overall performance is also improved. In the future, with the development of related technologies, the optimization of integrated circuits will be faster.
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Yeh, Cheng-Yu, Jen Shiu, and Her-Terng Yau. "Circuit Implementation of Coronary Artery Chaos Phenomenon and Optimal PID Synchronization Controller Design." Mathematical Problems in Engineering 2012 (2012): 1–13. http://dx.doi.org/10.1155/2012/745396.
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This study aimed at the implementation and synchronization control of cardiac circuit. First, the MATLAB-Simulink was used to simulate the dynamic behavior of cardiac chaotic circuit, and simple electronic modules were used to implement the cardiac system. Then the Particle Swarm Optimization (PSO) was used to seek for the proportional, integral, and derivative gains of optimal PID controller, and the PID controller which could synchronize the slave cardiac circuit and the master cardiac circuit was obtained, in order to synchronize the master/slave chaotic cardiac circuits. This method can be provided for cardiac doctors to diagnose and medicate cardiac abnormality.
10
Chen, Zhuo, Guoding Liu, and Xiongfeng Ma. "Optimizing Circuit Reusing and its Application in Randomized Benchmarking." Quantum 9 (January 23, 2025): 1606. https://doi.org/10.22331/q-2025-01-23-1606.
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Quantum learning tasks often leverage randomly sampled quantum circuits to characterize unknown systems. An efficient approach known as ``circuit reusing,'' where each circuit is executed multiple times, reduces the cost compared to implementing new circuits. This work investigates the optimal reusing times that minimizes the variance of measurement outcomes for a given experimental cost. We establish a theoretical framework connecting the variance of experimental estimators with the reusing times R. An optimal R is derived when the implemented circuits and their noise characteristics are known. Additionally, we introduce a near-optimal reusing strategy that is applicable even without prior knowledge of circuits or noise, achieving variances close to the theoretical minimum. To validate our framework, we apply it to randomized benchmarking and analyze the optimal R for various typical noise channels. We further conduct experiments on a superconducting platform, revealing a non-linear relationship between R and the cost, contradicting previous assumptions in the literature. Our theoretical framework successfully incorporates this non-linearity and accurately predicts the experimentally observed optimal R. These findings underscore the broad applicability of our approach to experimental realizations of quantum learning protocols.
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Pietrzko, Stanislaw, and Qibo Mao. "Reduction of Structural Sound Radiation and Vibration Using Shunt Piezoelectric Materials." Solid State Phenomena 147-149 (January 2009): 882–89. http://dx.doi.org/10.4028/www.scientific.net/ssp.147-149.882.
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In this paper, structural sound and vibration control using passive and semi-active shunt piezoelectric damping circuits is presented. A piezoelectric patch with an electrical shunt circuit is bonded to a base structure. When the structure vibrates, the piezoelectric patch strains and transforms the mechanical energy of the structure into electrical energy, which can be effectively dissipated by the shunt circuit. Hence, the shunt circuit acts as a means of extracting mechanical energy from the base structure. First, different types of shunt circuits (such as RL series circuit, RL parallel circuit and RL-C circuit), employed in the passive damping arrangement, are analyzed and compared. By using the impedance method, the general modelling of different shunt piezoelectric damping techniques is presented. The piezoelectric shunt circuit can be seen as additional frequency-dependence damping of the system. One of the primary concerns in shunt damping is to choose the optimal parameters for shunt circuits. In past efforts most of the proposed tuning methods were based on modal properties of the structure. These methods are used to minimize the response of a particular structural mode whilst neglecting the contribution of the other modes. In this study, a design method based on minimization of the sound power of the structure is proposed. The optimal parameters for shunt circuits are obtained using linear quadratic optimal control theory. In general, the passive shunt circuit techniques are an effective method of modal damping. However, the main drawback of the passive shunt circuit is that the shunt piezoelectric is very sensitive to tuning errors and variations in the excitation frequency. To overcome this problem, the pulse-switching shunt circuit, a semi-active continuous switching technique in which a RL shunt circuit is periodically connected to a bonded piezoelectric patch, is introduced as structural damping. The switch law for pulse-switching circuit is discussed based on the energy dissipation technique. Compared with a standard passive piezoelectric shunt circuit, the advantages of the pulse-switching shunt circuit is a small required shunt inductance, a lower sensitivity to environmental changes and easier tuning. Very low external power for the switch controller is required so it may be possible to extract this energy directly from the vibration of the structure itself. Numerical simulations are performed for each of these shunts techniques focusing on minimizing radiated sound power from a clamped plate. It is found that the RL series, RL parallel and pulse-switching circuits have basically the same control performance. The RL–C parallel circuit allows us to reduce the value of the inductance L due to the insertion of an external capacity C. However, the control performance will be reduced simultaneously. The pulse-switching circuit is more stable than RL series circuit with regard to structural stiffness variations. Finally, experimental results are presented using an RL series/parallel shunt circuit, RL-C parallel shunt circuit and pulse-switching circuit. The experimental results have shown that the vibration and noise radiation of a structure can be reduced significantly by using these shunt circuits. The theoretical and experimental techniques presented in this study provide a valuable tool for effective shunt piezoelectric damping.
12
Wang, Jing Li. "Optimal Design of Electronic Circuit." Applied Mechanics and Materials 58-60 (June 2011): 2581–84. http://dx.doi.org/10.4028/www.scientific.net/amm.58-60.2581.
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Circuit optimization method should include the topology of automatic design circuit and automatically determine components parameters of the circuit. At present, CAD or EDA optimization tools is produced by combined optimization algorithm and the basic analysis above together with the tolerance analysis. In this paper, optimization design which can modular basic analog circuit by using Optimizer, which makes the circuit topology structure and component parameters tend to be more reasonable, provides the basis for teaching practice and scientific research. It has practical significance.
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Bittner, Kai, and Hans Georg Brachtendorf. "Optimal frequency sweep method in multi-rate circuit simulation." COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 33, no. 4 (2014): 1189–97. http://dx.doi.org/10.1108/compel-11-2012-0346.
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Purpose – Radio-frequency circuits often possess a multi-rate behavior. Slow changing baseband signals and fast oscillating carrier signals often occur in the same circuit. Frequency modulated signals pose a particular challenge. The paper aims to discuss these issues. Design/methodology/approach – The ordinary circuit differential equations are first rewritten by a system of (multi-rate) partial differential equations in order to decouple the different time scales. For an efficient simulation the paper needs an optimal choice of a frequency-dependent parameter. This is achieved by an additional smoothness condition. Findings – By incorporating the smoothness condition into the discretization, the paper obtains a non-linear system of equations complemented by a minimization constraint. This problem is solved by a modified Newton method, which needs only little extra computational effort. The method is tested on a phase locked loop with a frequency modulated input signal. Originality/value – A new optimal frequency sweep method was introduced, which will permit a very efficient simulation of multi-rate circuits.
14
Gaioni, Luigi. "Analytical Analysis of Power-Constrained Repeaters’ Insertion in Large-Scale CMOS Chips." Electronics 13, no. 22 (2024): 4368. http://dx.doi.org/10.3390/electronics13224368.
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As the die area of CMOS integrated circuits continues to increase, interconnects will become dominant in determining the performance of the circuits from the standpoint of speed and power consumption. Uniform repeater insertion is an effective method used to reduce the propagation delay of a signal in long resistive-capacitive lines. However, non-optimal repeaters’ insertion yields non-optimal circuit performance. In this work, we provide a mathematical treatment for optimal repeater insertion with power consumption constraints. In particular, a closed-form expression for the optimum number and size of repeaters is given for a two-stage buffer used as a repeater. The validation of the analytical solution is assessed by means of circuit simulations, by comparing the theoretical optimal number and size of the repeaters to be placed in the long resistive-capacitive line with the simulated values.
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Yaman, Orhan, Tuba Sanli, and Mehmet Karakose. "A Quine-McCluskey Based Method for Generating Optimum Combinational Logic Circuits from Reversible Quantum Circuits." Journal of Artificial Intelligence and Autonomous Intelligence 01, no. 01 (2024): 139–54. https://doi.org/10.54364/jaiai.2024.1110.
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Algorithms specifically designed for quantum computers have been developed. In quantum circuits, the Feynman, Toffoli, and Fredkin gates are employed instead of traditional inputs such as AND, OR, NAND, NOR, XOR, and XNOR in combinational logic gates. The ability to convert quantum circuits into combinational logic circuits, or vice versa, is of utmost importance. This essay study (or paper) aims to demonstrates the process of deriving combinational logic circuits from reversible quantum circuits. To achieve this, the Quine-McCluskey technique was utilized along with state tables generated from the quantum circuits to obtain an optimal logic expression that serves as the basis for constructing the combinational logic circuit. The resultant obtained combinational logic circuit was implemented within the MATLAB Simulink environment, and state tables were obtained. A comparison was made between the state tables derived from the quantum circuit and the combinational circuit, yielding successful results.
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Alhagi, Nouraddin, Maher Hawash, and Marek Perkowski. "Synthesis of reversible circuits for large reversible functions." Facta universitatis - series: Electronics and Energetics 23, no. 3 (2010): 273–86. http://dx.doi.org/10.2298/fuee1003273a.
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This paper presents a new algorithm MP (multiple pass) to synthesize large reversible binary circuits without ancilla bits. The well-known MMD algorithm for synthesis of reversible circuits requires to store a truth table (or a Reed-Muller - RM transform) as a 2n vector to represent a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large scale reversible circuits (30-bits), which is not possible with any existing algorithm. In addition, our unique multi-pass approach where the circuit is synthesized with various, yet specific, minterm orders yields quasi-optimal solution. The algorithm returns a description of the quasi-optimal circuit with respect to gate count or to its 'quantum cost'. Although the synthesis process in MP is relatively slower, the solution is found in real-time for smaller circuits of 8 bits or less.
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Liu, Shuyang. "Research on Optimal Design of Chip ESD Protection Circuit Based on CMOS Technology." Transactions on Computer Science and Intelligent Systems Research 1 (October 12, 2023): 86–90. http://dx.doi.org/10.62051/mxk4dx97.
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A high frequency circuit based on ESD protection and a new type of power grounding clamp circuit are designed. The oblique edge interfinger diode is used to achieve the optimal design of layout and performance. The design of electrostatic discharge protection circuit and flowsheet were completed in Jazz0.18-micron silicon germanium BiCMOS process. The protection voltage of electrostatic discharge is 3000 V. Higher electrostatic protection level can be obtained by changing the bifurcation index of diode. Improved protection of up to 4500 volts can be achieved. Through the test of the chip, it is proved that the chip fully meets the design requirements and can realize various types of digital circuits.
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Frasser, Christiam F., Miquel Roca, and Josep L. Rosselló. "Optimal Stochastic Computing Randomization." Electronics 10, no. 23 (2021): 2985. http://dx.doi.org/10.3390/electronics10232985.
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Stochastic computing (SC) is a probabilistic-based processing methodology that has emerged as an energy-efficient solution for implementing image processing and deep learning in hardware. The core of these systems relies on the selection of appropriate Random Number Generators (RNGs) to guarantee an acceptable accuracy. In this work, we demonstrate that classical Linear Feedback Shift Registers (LFSR) can be efficiently used for correlation-sensitive circuits if an appropriate seed selection is followed. For this purpose, we implement some basic SC operations along with a real image processing application, an edge detection circuit. Compared with the literature, the results show that the use of a single LFSR architecture with an appropriate seeding has the best accuracy. Compared to the second best method (Sobol) for 8-bit precision, our work performs 7.3 times better for the quadratic function; a 1.5 improvement factor is observed for the scaled addition; a 1.1 improvement for the multiplication; and a 1.3 factor for edge detection. Finally, we supply the polynomials and seeds that must be employed for different use cases, allowing the SC circuit designer to have a solid base for generating reliable bit-streams.
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Junyi, Lee, and Daniel Stephen Balint. "Optimal shunt parameters for maximising wave attenuation with periodic piezoelectric patches." Journal of Intelligent Material Systems and Structures 28, no. 1 (2016): 108–23. http://dx.doi.org/10.1177/1045389x16645861.
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Elastic metamaterials, which have huge potential in wave guiding and attenuation applications, can be built from structures with periodic piezoelectric patch arrays. Passive shunts offer the benefits of simplicity and low cost. In this paper, the effects of the magnitude and phase angle of the shunt impedance on the attenuation constant of a beam with periodic piezoelectric patch arrays were studied in order to determine the optimal shunt that produces the widest and most effective band gaps. The attenuation constants were found to be large when the phase angle is [Formula: see text] rad and when the magnitude decreases exponentially with the excitation frequency. This corresponds to a negative capacitance circuit, which is the optimal shunt for such systems. The attenuation constant of the system reduces significantly when the impedance deviates from the optimal value suggesting other circuits are less effective. The impedance and band structure of resistive–inductive (R-L), negative capacitance and resistive shunts were investigated. As expected, the negative capacitance circuit produces a large band gap, while the R-L circuit only produces a band gap around its natural frequency. The transmissibilities of a finite system with these circuits demonstrated that vibration transmissions are low within the band gaps. Furthermore, the stability of the negative capacitance circuit built using a dual-output second-generation current conveyor (DO-CCII) was examined by studying the pole diagrams. The system was found to be stable in ideal conditions but unstable when parasitic effects are considered. This suggests that the stability of the system is an important consideration for the implementation of this strategy and the different negative impedance converter designs available in the literature should be studied to find a suitable circuit configuration.
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Liu, Hong, and Shuang Zi Sun. "PSO Based Feature Extraction Method for Analog Circuits Fault Information." Applied Mechanics and Materials 721 (December 2014): 509–12. http://dx.doi.org/10.4028/www.scientific.net/amm.721.509.
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In order to improve the diagnosis efficiency of faulty circuits with tolerance and to ameliorate characteristic description of faulty symptom, the faulty features of the circuit with tolerance are created by information entropy method at first, and then feature extraction method based on discrete Particle Swarm Optimization algorithm (PSO) is proposed to obtain the optimal feature subset of faulty feature. At last, the optimal feature subset is used to train the classifier to diagnosis the faults of the circuit with tolerance. Experiments results show the validity of this proposed method.
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Fan, Austen Z., Paraschos Koutris, and Sudeepa Roy. "Circuits and Formulas for Datalog over Semirings." Proceedings of the ACM on Management of Data 3, no. 2 (2025): 1–22. https://doi.org/10.1145/3725230.
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In this paper, we study circuits and formulas for provenance polynomials of Datalog programs. We ask the following question: given an absorptive semiring and a fact of a Datalog program, what is the optimal depth and size of a circuit/formula that computes its provenance polynomial? We focus on absorptive semirings as these guarantee the existence of a polynomial-size circuit. Our main result is a dichotomy for several classes of Datalog programs on whether they admit a formula of polynomial size or not. We achieve this result by showing that for these Datalog programs the optimal circuit depth is either Θ(log m ) or Θ(log 2 m ), where m is the input size. We also show that for Datalog programs with the polynomial fringe property, we can always construct low-depth circuits of size O(log 2 m ). Finally, we give characterizations of when Datalog programs are bounded over more general semirings.
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Zou, Aicheng, Zhong Liu, and Xingguo Han. "A Low-Power High-Efficiency Adaptive Energy Harvesting Circuit for Broadband Piezoelectric Vibration Energy Harvester." Actuators 10, no. 12 (2021): 327. http://dx.doi.org/10.3390/act10120327.
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Existing piezoelectric vibration energy harvesting circuits require auxiliary power for the switch control module and are difficult to adapt to broadband piezoelectric vibration energy harvesters. This paper proposes a self-powered and low-power enhanced double synchronized switch harvesting (EDSSH) circuit. The proposed circuit consists of a low-power follow-up switch control circuit, reverse feedback blocking-up circuit, synchronous electric charge extraction circuit and buck-boost circuit. The EDSSH circuit can automatically adapt to the sinusoidal voltage signal with the frequency of 1 to 312.5 Hz that is output by the piezoelectric vibration energy harvester. The switch control circuit of the EDSSH circuit works intermittently for a very short time near the power extreme point and consumes a low amount of electric energy. The reverse feedback blocking-up circuit of the EDSSH circuit can keep the transmission efficiency at the optimal value. By using a charging capacitor of 1 mF, the charging efficiency of the proposed EDSSH circuit is 1.51 times that of the DSSH circuit.
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Bu, Xiang Yun, Ze Zhang, and Dong Xu Zhang. "Simulation and Research on the Improved Boost Circuit Based on Multisim." Advanced Materials Research 860-863 (December 2013): 2373–77. http://dx.doi.org/10.4028/www.scientific.net/amr.860-863.2373.
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In this paper, the working principle, the structure and the characteristics of an improved Boost circuit are introduced briefly, in addition, the simulation model of the improved Boost circuit is established using Multisim11.0, a simulation software of NI company. The results of the simulation verify the validity of the improved Boost circuit theory and establish the simulation model with optimal parameters. It also can be seen from the experimental results that the improved Boost circuit has a higher step-up ratio with the premise of no hardware upgrade. In general, the Multisim11.0 software plays an important role in the design of electronic circuits.
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Collado, Ana, and Apostolos Georgiadis. "Optimal Waveforms for Efficient Wireless Power Transmission." IEEE Microwave and Wireless Components Letters 24, no. 5 (2014): 354–56. https://doi.org/10.1109/LMWC.2014.2309074.
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This work shows how using specifically selected or designed waveforms in wireless power transfer (WPT) systems can lead to improved RF to dc conversion efficiency in rectifier circuits in the receiving end of these systems. Signals with different time domain waveforms are considered such as OFDM, white noise and chaotic waveforms, and the performance of a rectifier circuit operating at 433 MHz is evaluated when using these signals in comparison to a single carrier constant envelope signal. The performed experiments show that selecting high peak to average power ratio (PAPR) signals lead to improved RF-DC conversion efficiency in rectifier circuits.
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Bazylevych, R. P., R. A. Melnyk, and O. G. Rybak. "Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method." VLSI Design 11, no. 3 (2000): 237–48. http://dx.doi.org/10.1155/2000/58485.
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Mathematically the most difficult partitioning problem–packaging–is being considered. Its purpose is to minimize a number of partitions and to satisfy the constraints on the number of constituent elements and external nets. To solve the problem, the Optimal Circuit Reduction Method, suggested by R. Bazylevych is being used. The optimal reduction tree to reflect the hierarchical entrance of smaller clusters into bigger ones is being built for the first step. At the second step we select one or more tree vertices which better meet the given constraints and are the first partitions generated from. After creating every new partition we eliminate its elements from the circuit and repeat the procedure to complete all partitions. During the last stage optimization strategies to exchange some elements between the partitions are being used. Better or equivalent results among known tests confirm the effectiveness of this method.
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Kamioka, J., R. Matsuda, R. Mizokuchi, J. Yoneda, and T. Kodera. "Evaluation of a physically defined silicon quantum dot for design of matching circuit for RF reflectometry charge sensing." AIP Advances 13, no. 3 (2023): 035219. http://dx.doi.org/10.1063/5.0141092.
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This paper reports on the extraction of the equivalent circuit model parameters of a physically defined silicon quantum dot at a cryogenic temperature and design of the impedance matching circuits to improve the performance of a charge sensor for radio-frequency (RF) reflectometry. The I-V characteristics and the S-parameters of the quantum dot device are measured around a Coulomb peak at 4.2 K. The measured results are modeled by an RC parallel circuit, and the model parameters for the quantum dot device were obtained. We consider three impedance matching circuits for RF reflectometry of a quantum dot: shunt capacitor-series inductor type, shunt inductor-series capacitor type, and shunt inductor-series inductor-type. We formulate and compare the sensitivity and bandwidth of RF reflectometry for the three types of circuits. The analysis should be useful for selecting the optimal matching circuit and the circuit parameters for given equivalent circuit parameters and working frequency. This procedure is demonstrated for a quantum dot with the characterized model circuit along with simulated performance. This design technique of matching circuit for RF reflectometry can be applied to any device that can be represented by an RC parallel circuit. These results will facilitate to realize fast semiconductor qubit readout in various quantum dot platforms.
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Radmehr, Vahid, Sied Shafaei, Mohammad Noaparast, and Hadi Abdollahi. "Optimizing Flotation Circuit Recovery by Effective Stage Arrangements: A Case Study." Minerals 8, no. 10 (2018): 417. http://dx.doi.org/10.3390/min8100417.
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Recovery is one of the most important metallurgical parameters in designing and evaluating flotation circuits. The present study used the recovery arrangement for two and three stage circuits to evaluate the effect of stage recovery on the overall circuit recovery and flotation circuit configuration. The results showed that mainly the highest recovery value should be assigned to the rougher stage in order to achieve the maximum overall circuit recovery. Countercurrent rougher-cleaner and rougher-scavenger circuits, in which recycling streams step back one stage at a time, follow a general rule for the assignment of recovery. Finally, a flotation plant containing six flotation banks was examined as a case study. A program for calculating total circuit recovery, for all possible combinations of recovery was developed in MATLAB software. 720 recovery combinations were evaluated. The results showed that optimal recovery allocation in stages could be effective in achieving overall circuit recovery. It was shown that the use of a large number of stages in some of the flotation circuits leads to the loss of equipment and additional costs. The proposed approach can be employed as an effective tool for designing and optimizing various flotation circuits and their operational parameters.
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Aladdin Bayramov, Lala Bekirova, Aladdin Bayramov, Lala Bekirova. "MATHEMATICAL MODELING OF THE OPERATION OF AUDIO FREQUENCY (NO JUNCTION) AND JUNCTION RAIL CIRCUITS." PIRETC-Proceeding of The International Research Education & Training Centre 24, no. 03 (2023): 49–55. http://dx.doi.org/10.36962/piretc24032023-49.
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Rail circuits are the basic elements of modern railway automation and telemechanics systems, performing the functions of track sensors and telemechanical channels. It is shown that the calculation of their operating boundary conditions becomes more complicated with the application of junctionless audio frequency rail circuits. The analysis of track circuits consists of studying the changes in their operation in various modes when the circuit parameters are changed. During the analysis, the optimal values of the parameters of the circuit elements and the frequency of the power source are determined for the given operating conditions. An analysis of the factors affecting the operating currents and voltages of such rail circuit schemes has been carried out. When analyzing and calculating a track circuit, it is assumed that the track line and equipment elements are linear, that is, their parameters do not depend on the flowing currents. To simplify the calculations, the track circuit is represented by the corresponding mathematical model (equivalent circuit) for each mode. Depending on the type of equivalent circuit used, four-pole and multi-pole models are distinguished. At the same time, the analysis and reporting of jointed rail circuits are carried out. Based on their results, the directions that allow for more accurate modeling of the operating modes of the circuits of the non-joint audio frequency rail circuits have been determined. Keywords: Rail circuits, train traffic safety, audio frequency (no junction) track circuits, junction rail circuits, signaling system, track sensors, mathematical model, remote conditioning monitoring.
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Barkalov, Oleksandr O., Larisa A. Titarenko, Yaroslav Ye Vizor та Oleksandr V. Matvienko. "Synthesis of Сircuit of Сombined Automation with Reducing Area of Nano-PLA". Control Systems and Computers, № 4 (288) (вересень 2020): 05–13. http://dx.doi.org/10.15407/csc.2020.04.005.
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A method is proposed targeting reducing the area of combined automation circuits implemented with nano-PLAs. The method is based on optimal state assignment for Moore automation taking into account the existence of pseudo equivalent states. The proposed method allows reducing the area of nano-PLA required for implementing the circuit, as compared to a trivial two-level circuit. In this case, a part of the circuit implements the functions of Moore FSM. The results of research are given, as well as an example of synthesis.
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Aliev, Marat, Ezoz Tohirov, and Ravshan Aliev. "Mathematical Modeling of an Additional Shunt Zone in Track Circuits With a Potential Receiver: Algorithm and Calculations." Intellectual Technologies on Transport, no. 1 (April 14, 2024): 102–6. http://dx.doi.org/10.20295/2413-2527-2024-137-102-106.
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The paper presents an algorithm and methodology for calculating the additional shunt zone in track circuits with a potential receiver. The issues of mathematical modeing of a seamless track circuit are considered, and a method is proposed for determining the maximum shunting zone when the train moves away from the track circuit. The calculation results make it possible to conduct research and determine the optimal parameters of rail circuits with a potential receiver, which is important for taking technical easures to improve the operation of transport systems.
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Branislav Kuzmanović, Zoran Baus, and Petar Biljanović. "OPTIMAL RC PROTECTION OF THYRISTORS." Journal of Energy - Energija 55, no. 6 (2023): 690–705. http://dx.doi.org/10.37798/2006556405.
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Thyristors are susceptible to the increase rate of anode voltage, recovery overvoltage and current increase rate. They are therefore protected by means of supplementary circuits. Sometimes a protection circuit that has been designed to attenuate a certain transient process is not optimal for the attenuation of some other process, therefore a compromise solution is needed. In this paper, the optimal operating conditions of the thyristor protection are analyzed, where the thyristor parameters that are characteristic for the turn-on and turn-off period have been taken into consideration. The analysis has been performed in a normized form, which assures its general applicability.
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Mahrous, Hany, Mostafa Fedawy, Mira Abboud, Ahmed Shaker, W. Fikry, and Michael Gad. "A Multi-Objective Genetic Algorithm Approach for Silicon Photonics Design." Photonics 11, no. 1 (2024): 80. http://dx.doi.org/10.3390/photonics11010080.
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A multi-objective genetic algorithm approach is formulated to optimize the design of silicon-photonics complex circuits with contradicting performance metrics and no closed-form expression for the circuit performance. A case study is the interleaver/deinterleaver circuit which mixes/separates optical signals into/from different physical channels while preserving the wavelength-division-multiplexing specifications. These specifications are given as channel spacing of 50 GHz, channel 3-dB bandwidth of at least 20 GHz, channel free spectral range of 100 GHz, crosstalk of −23 dB or less, and signal dispersion less than 30 ps/nm. The essence of the proposed approach lies in the formulation of the fitness functions and the selection criteria to optimize the values of the three coupling coefficients, which govern the circuit performance, in order to accommodate the contradicting performance metrics of the circuit. The proposed approach achieves the optimal design in an incomparably short period of time when contrasted with the previous tedious design method based on employing Z-transform and visual inspection of the transmission poles and zeros.
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Tseng, Kuo-Hsiung, Yur-Shan Lin, Yun-Chung Lin, Der-Chi Tien, and Leszek Stobinski. "Deriving Optimized PID Parameters of Nano-Ag Colloid Prepared by Electrical Spark Discharge Method." Nanomaterials 10, no. 6 (2020): 1091. http://dx.doi.org/10.3390/nano10061091.
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Using the electrical spark discharge method, this study prepared a nano-Ag colloid using self-developed, microelectrical discharge machining equipment. Requiring no additional surfactant, the approach in question can be used at the ambient temperature and pressure. Moreover, this novel physical method of preparation produced no chemical pollution. This study conducted an in-depth investigation to establish the following electrical discharge conditions: gap electrical discharge, short circuits, and open circuits. Short circuits affect system lifespan and cause electrode consumption, resulting in large, non-nanoscale particles. Accordingly, in this study, research for and design of a new logic judgment circuit set was used to determine the short-circuit rate. The Ziegler–Nichols proportional–integral–derivative (PID) method was then adopted to find optimal PID values for reducing the ratio between short-circuit and discharge rates of the system. The particle size, zeta potential, and ultraviolet spectrum of the nano-Ag colloid prepared using the aforementioned method were also analyzed with nanoanalysis equipment. Lastly, the characteristics of nanosized particles were analyzed with a transmission electron microscope. This study found that the lowest ratio between short-circuit rates was obtained (1.77%) when PID parameters were such that Kp was 0.96, Ki was 5.760576, and Kd was 0.039996. For the nano-Ag colloid prepared using the aforementioned PID parameters, the particle size was 3.409 nm, zeta potential was approximately −46.8 mV, absorbance was approximately 0.26, and surface plasmon resonance was 390 nm. Therefore, this study demonstrated that reducing the short-circuit rate can substantially enhance the effectiveness of the preparation and produce an optimal nano-Ag colloid.
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Zemliak, Alexander, and Jorge Espinosa-Garcia. "Analysis of the structure of different optimization strategies." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 39, no. 3 (2020): 583–93. http://dx.doi.org/10.1108/compel-09-2019-0370.
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Purpose In this paper, on the basis of a previously developed approach to circuit optimization, the main element of which is the control vector that changes the form of the basic equations, the structure of the control vector is determined, which minimizes CPU time. Design/methodology/approach The circuit optimization process is defined as a controlled dynamic system with a special control vector. This vector serves as the main tool for generalizing the problem of circuit optimization and produces a huge number of different optimization strategies. The task of finding the best optimization strategy that minimizes processor time can be formulated. There is a need to find the optimal structure of the control vector that minimizes processor time. A special function, which is a combination of the Lyapunov function of the optimization process and its time derivative, was proposed to predict the optimal structure of the control vector. The found optimal positions of the switching points of the control vector give a large gain in CPU time in comparison with the traditional approach. Findings The optimal positions of the switching points of the components of the control vector were calculated. They minimize processor time. Numerical results are obtained for various circuits. Originality/value The Lyapunov function, which is one of the main characteristics of any dynamic system, is used to determine the optimal structure of the control vector, which minimizes the time of the circuit optimization process.
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V, Saravanan, Sivaramakrishnan A, and Ramkumar M. "CMOS NOISE ANALYSIS FOR MILLIMETER WAVE FREQUENCIES USING PAPR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) WHITE NOISE AND SPECKLE NOISE FOR TIME VARYING SIGNALS." ICTACT Journal on Microelectronics 9, no. 4 (2024): 1675–80. https://doi.org/10.21917/ijme.2024.0290.
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In millimeter-wave CMOS circuit design, addressing noise becomes pivotal for optimal performance. This research targets the unique challenges posed by white and speckle noise in time-varying signals, especially in the context of PAPR operational transconductance amplifiers (OTAs). The introduction highlights the prevalence of CMOS technology and the increasing demand for millimeter-wave frequencies in integrated circuits. Recognizing the criticality of noise in these applications, our research identifies a notable research gap in the literature concerning the joint impact of white and speckle noise on PAPR OTAs. The proposed method leverages advanced circuit simulations, emphasizing the utilization of tools like Cadence Virtuoso and Keysight Advanced Design System. This approach enables a comprehensive analysis of noise sources, emphasizing the minimization of noise contributions for optimal millimeter-wave circuit performance. Initial results showcase promising advancements in noise reduction strategies, contributing to the efficacy of PAPR OTAs at high frequencies. This research not only addresses an existing gap but also provides practical insights for designers aiming to enhance the noise resilience of millimeter-wave CMOS circuits.
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Khodataeva, Tatiana Sergeevna, Nikolai Vladimirovich Kashirin, Alexandra Ivanovna Averina, and Artyom Evgenyevich Guryanov. "Approaches to the Development of a Printed Circuit Board Defect Detection System Based on AOI Technology." Proceedings of the Institute for System Programming of the RAS 35, no. 4 (2023): 109–20. http://dx.doi.org/10.15514/ispras-2023-35(4)-5.
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Some modern approaches to detecting defects in printed circuit boards based on automatic optical inspection are considered in order to design their own control system. The importance of the control process is growing in connection with the tightening of the requirements imposed by modern production processes. At the enterprises of mass production of electronics, attempts are being made to achieve high quality of all parts, assemblies and finished products. The optical inspection system is one of the most important tools for automating the visual inspection of printed circuits. In addition to ensuring cost efficiency and product quality control, an automated control system can also collect statistical information to provide feedback to the production process. The review considers algorithms and methods for automated optical control of the conductive pattern on the surface of printed circuit boards in order to find the optimal method for detecting defects.
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Jung, Jihye, and In-Chan Choi. "A multi-commodity network model for optimal quantum reversible circuit synthesis." PLOS ONE 16, no. 6 (2021): e0253140. http://dx.doi.org/10.1371/journal.pone.0253140.
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Quantum computing is a newly emerging computing environment that has recently attracted intense research interest in improving the output fidelity, fully utilizing its high computing power from both hardware and software perspectives. In particular, several attempts have been made to reduce the errors in quantum computing algorithms through the efficient synthesis of quantum circuits. In this study, we present an application of an optimization model for synthesizing quantum circuits with minimum implementation costs to lower the error rates by forming a simpler circuit. Our model has a unique structure that combines the arc-subset selection problem with a conventional multi-commodity network flow model. The model targets the circuit synthesis with multiple control Toffoli gates to implement Boolean reversible functions that are often used as a key component in many quantum algorithms. Compared to previous studies, the proposed model has a unifying yet straightforward structure for exploiting the operational characteristics of quantum gates. Our computational experiment shows the potential of the proposed model, obtaining quantum circuits with significantly lower quantum costs compared to prior studies. The proposed model is also applicable to various other fields where reversible logic is utilized, such as low-power computing, fault-tolerant designs, and DNA computing. In addition, our model can be applied to network-based problems, such as logistics distribution and time-stage network problems.
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Aliev, Ravshan, Marat Aliev, and Shoyatbek Khakimov. "Determination of the optimal parameters of the control sensor at the crossing in the control mode." E3S Web of Conferences 420 (2023): 07026. http://dx.doi.org/10.1051/e3sconf/202342007026.
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On railway sections where there are intersections with road transport, control systems for crossing signaling with auto barriers are arranged. To control the entrance of the train to this section, track circuits with insulating joints are used. Such circuits have a number of significant drawbacks, one of which is the coming off of insulating joints, as well as breakage of the track circuit, which give 45% of the failures of automation systems on the haul. In this article, a study was made of a crossing track circuit with a tone frequency for the control mode. For the study, mathematical expressions for determining the most unfavorable moment were derived, an algorithmic expression for the control mode coefficient was presented, which gives more accurate information about the presence of damage. As a result, a block diagram was developed and graphs were displayed on the simulation model showing the influence and determination of the control mode of operation of the jointless tone track circuit. In conclusion, the results of the study are summarized.
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Zemliak, Alexander. "Analysis of Some Special Functions for a Problem of Optimization of Analog Circuits." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 22 (October 11, 2023): 98–110. http://dx.doi.org/10.37394/23201.2023.22.12.
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Further development of a generalized methodology for optimizing analog circuits is proposed. This methodology is based on the theory of optimal control. We have transformed the problem of minimizing the CPU time needed to optimize the circuit into the classical problem of minimizing the function in optimal control theory. In this case, we represent the process of optimizing the analog circuit as a controlled dynamic system. To analyze the properties of such a system, we propose to use the concept of the Lyapunov function of a dynamical system. The new special functions allow us to predict the CPU time for circuit optimization by analyzing the characteristics of the initial part of the process. It has been established that for any optimization strategy, there is a correlation between the behavior of these functions and the CPU time corresponding to these strategies.
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Manes, Argyris Giannisis, and Jahan Claes. "Distance-preserving stabilizer measurements in hypergraph product codes." Quantum 9 (January 30, 2025): 1618. https://doi.org/10.22331/q-2025-01-30-1618.
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Unlike the surface code, quantum low-density parity-check (QLDPC) codes can have a finite encoding rate, potentially lowering the error correction overhead. However, finite-rate QLDPC codes have nonlocal stabilizers, making it difficult to design stabilizer measurement circuits that are low-depth and do not decrease the effective distance. Here, we demonstrate that a popular family of finite-rate QLDPC codes, hypergraph product codes, has the convenient property of distance-robustness: any stabilizer measurement circuit preserves the effective distance. In particular, we prove the depth-optimal circuit in [Tremblay et al, PRL 129, 050504 (2022)] is also optimal in terms of effective distance.
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Molavi, Abtin, Amanda Xu, Swamit Tannu, and Aws Albarghouthi. "Dependency-Aware Compilation for Surface Code Quantum Architectures." Proceedings of the ACM on Programming Languages 9, OOPSLA1 (2025): 57–84. https://doi.org/10.1145/3720416.
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Practical applications of quantum computing depend on fault-tolerant devices with error correction. We study the problem of compiling quantum circuits for quantum computers implementing surface codes. Optimal or near-optimal compilation is critical for both efficiency and correctness. The compilation problem requires (1) mapping circuit qubits to the device qubits and (2) routing execution paths between interacting qubits. We solve this problem efficiently and near-optimally with a novel algorithm that exploits the dependency structure of circuit operations to formulate discrete optimization problems that can be approximated via simulated annealing , a classic and simple algorithm. Our extensive evaluation shows that our approach is powerful and flexible for compiling realistic workloads.
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Sakaba, Takeshi. "Optimal dissection of a model circuit." Journal of Physiology 596, no. 20 (2018): 4807–8. http://dx.doi.org/10.1113/jp276895.
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Sun, Chun-sheng, Shi-qiao Qin, Xing-shu Wang, and Dong-hua Zhu. "Optimal design of APD biasing circuit." Optoelectronics Letters 3, no. 3 (2007): 237–40. http://dx.doi.org/10.1007/s11801-007-6151-y.
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Ren, Xi-Jun, and Heng Fan. "Quantum circuits for asymmetric 1 to n quantum cloning." Quantum Information and Computation 15, no. 11&12 (2015): 914–22. http://dx.doi.org/10.26421/qic15.11-12-2.
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In this paper, we considered asymmetric $1\rightarrow n$ cloning circuits generalized from the asymmetric $1\rightarrow 2$ cloning circuit proposed by Bu\v{z}ek \textit{et al.} [Phys. Rev. A 56, 3446 (1997)]. The generalization is based on an information flux insight of the original cloning circuit. Specifically, the circuit separately and sequentially transfers the Z-type information and X-type information of the input state to the output copies with controlled-not gates. The initial input state of the clones defines the asymmetry among all output clones. Although the generalized circuits do not perform universally, the averaged fidelities over a uniform distribution of all possible input cloning states saturate the optimal fidelity tradeoff relations of universal asymmetric cloning.
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Wang, Yuehai, Yongzheng Yan, and Qinyong Wang. "Wavelet-Based Feature Extraction in Fault Diagnosis for Biquad High-Pass Filter Circuit." Mathematical Problems in Engineering 2016 (2016): 1–13. http://dx.doi.org/10.1155/2016/5682847.
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Fault diagnosis for analog circuit has become a prominent factor in improving the reliability of integrated circuit due to its irreplaceability in modern integrated circuits. In fact fault diagnosis based on intelligent algorithms has become a popular research topic as efficient feature extraction and selection are a critical and intricate task in analog fault diagnosis. Further, it is extremely important to propose some general guidelines for the optimal feature extraction and selection. In this paper, based on wavelet analysis, we will study the problems of mother wavelets selection, number of decomposition levels, and candidate coefficients selection by using a four-op-amp biquad filter circuit. After conducting several comparative experiments, some general guidelines for feature extraction for this type of analog circuits fault diagnosis are derived.
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Mohd. Tauheed Khan, Naresh Kumar, Aditi Malhotra, Aparna Marwah, and Daljeet Singh Bawa. "Efficient RF-to-DC Converters for Biomedical Implantable Devices." Journal of Advanced Zoology 44, S6 (2023): 10–21. http://dx.doi.org/10.17762/jaz.v44is6.1945.
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The power management section associated with the biomedical circuit is very crucial and should be optimally designed for optimal utilization of power. This work discusses the different power shaping or conversion circuits that had been taken for their performance analysis. The two-performance metrics power conversion efficiency and susceptibility against the wireless power transfer have been taken to investigate the operational performance of the biomedical circuits against the input signal strength and operating frequencies. Simulated results confirm the CNFET-based circuit performance is very good at a small value of input voltage 0.6V and a broad range of operating frequency (953 MHz). Therefore, a CNFET-based circuit can be used suitably in implantable devices with optimum power utilization and a remote powering mechanism over the RF link.
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Barra, Samir. "Intelligent Optimization of CMOS Operational Amplifier Using 3D Ant Colony Optimization." Electronics ETF 27, no. 2 (2023): 35–42. http://dx.doi.org/10.53314/els2327035b.
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This paper presents the use of an artificial intelligence (AI) tool based on ant colony behavior to design an operational amplifier circuit. The ant colony optimization (ACO) is implemented in a hybrid evolutionary sizing method to automate analog circuit design. This new meta-heuristic approach that combines the artificial intelligence of an ant colony and the 3D matrix method is developed to determine the optimal dimensions and the main influencing performances of fundamental analog circuits and, including operational amplifiers (op-amps). The proposed methodology uses ACO and Cadence Spectre as dimensioning techniques and implementation platform, respectively. The Three Dimensions (3D) ACO algorithm is successfully used for analog circuit sizing, and the obtained results demonstrate its effectiveness in sizing basic and more complicated analog circuits.
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Lee, Chia Yen, Ming Tsun Ke, Chin Lung Chang, Chien Hsiung Tsai, Lung Ming Fu, and Chiu Feng Lin. "Optimal Piping Design for Enhanced Energy Saving in District Cooling System – A Case Study." Advanced Materials Research 354-355 (October 2011): 744–52. http://dx.doi.org/10.4028/www.scientific.net/amr.354-355.744.
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This study performs a numerical investigation into the power consumption characteristics of various primary-secondary chilled water circuit designs in a district cooling system (DCS) installed in six buildings located within the same block in Taipei, Taiwan. An E20-II model is created of the DCS and a series of simulations are performed to determine the primary-secondary chilled water piping design which maximizes the energy saving obtained in the DCS over the course of a typical year. It is shown that the use of a region-pumping system or a boost-pumping system reduces the power consumption of the secondary chilled water circuit by 26.5% and 29.9%, respectively, compared to that of a common-pumping system. In addition, the results show that for a practical chilled water system in which the temperature differential on the primary side is 5.0oC while that on the secondary side is 6.5oC, an average monthly energy saving of around 5~7% is obtained compared to a DCS with equal temperature differentials in the primary-secondary circuits provided that the flow rate and the temperature differential of the chilled water in the primary circuit are a little less than those in the secondary circuit.
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Fang, M., S. Fenner, F. Green, S. Homer, and Y. Zhang. "Quantum lower bounds for fanout." Quantum Information and Computation 6, no. 1 (2006): 46–57. http://dx.doi.org/10.26421/qic6.1-3.
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We consider the resource bounded quantum circuit model with circuits restricted by the number of qubits they act upon and by their depth. Focusing on natural universal sets of gates which are familiar from classical circuit theory, several new lower bounds for constant depth quantum circuits are proved. The main result is that parity (and hence fanout) requires log depth quantum circuits, when the circuits are composed of single qubit and arbitrary size Toffoli gates, and when they use only constantly many ancill\ae. Under this constraint, this bound is close to optimal. In the case of a non-constant number $a$ of ancill\ae\ and $n$ input qubits, we give a tradeoff between $a$ and the required depth, that results in a non-constant lower bound for fanout when $a = n^{1-o(1)}$. We also show that, regardless of the number of ancill\ae\, arbitrary arity Toffoli gates cannot be simulated exactly by a constant depth circuit family with gates of bounded arity.
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Chen, Jia Yin, Guo Jun Liu, and Jiang An Wang. "Design Research of Optical Fiber Sensor Based on Reflective Intensity-Type Optical Sensing." Advanced Materials Research 846-847 (November 2013): 714–17. http://dx.doi.org/10.4028/www.scientific.net/amr.846-847.714.
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The paper conducts optimal design for reflective intensity-type optical sensing. It designs two holes on the back of sensor probe which reduces system damping due to diaphragm and space air. It sets reference circuit and realizes the light intensity compensation by the way of comparing ratio specific value of measuring circuit and reference circuit. According to the symmetry requirement of photoelectric detection circuit, the paper designs photoelectric detection treatment circuit. The experiment shows that intensity compensation method can compensate well the power fluctuation of light source and temperature drift caused by long-time operation of sensor.