Relevant bibliographies by topics / OxRAM - oxide-Based resistive memory

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers
  5. Reports

Academic literature on the topic 'OxRAM - oxide-Based resistive memory'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "OxRAM - oxide-Based resistive memory"

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Pedró, Marta, Javier Martín-Martínez, Marcos Maestro-Izquierdo, Rosana Rodríguez, and Montserrat Nafría. "Self-Organizing Neural Networks Based on OxRAM Devices under a Fully Unsupervised Training Scheme." Materials 12, no. 21 (October 24, 2019): 3482. http://dx.doi.org/10.3390/ma12213482.

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A fully-unsupervised learning algorithm for reaching self-organization in neuromorphic architectures is provided in this work. We experimentally demonstrate spike-timing dependent plasticity (STDP) in Oxide-based Resistive Random Access Memory (OxRAM) devices, and propose a set of waveforms in order to induce symmetric conductivity changes. An empirical model is used to describe the observed plasticity. A neuromorphic system based on the tested devices is simulated, where the developed learning algorithm is tested, involving STDP as the local learning rule. The design of the system and learning scheme permits to concatenate multiple neuromorphic layers, where autonomous hierarchical computing can be performed.
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Bocquet, Marc, Hassen Aziza, Weisheng Zhao, Yue Zhang, Santhosh Onkaraiah, Christophe Muller, Marina Reyboz, Damien Deleruyelle, Fabien Clermidy, and Jean-Michel Portal. "Compact Modeling Solutions for Oxide-Based Resistive Switching Memories (OxRAM)." Journal of Low Power Electronics and Applications 4, no. 1 (January 9, 2014): 1–14. http://dx.doi.org/10.3390/jlpea4010001.

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Yang, Yuchao, Patrick Sheridan, and Wei Lu. "Complementary resistive switching in tantalum oxide-based resistive memory devices." Applied Physics Letters 100, no. 20 (May 14, 2012): 203112. http://dx.doi.org/10.1063/1.4719198.

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Liu, Xinjun, Sharif Md Sadaf, Sangsu Park, Seonghyun Kim, Euijun Cha, Daeseok Lee, Gun-Young Jung, and Hyunsang Hwang. "Complementary Resistive Switching in Niobium Oxide-Based Resistive Memory Devices." IEEE Electron Device Letters 34, no. 2 (February 2013): 235–37. http://dx.doi.org/10.1109/led.2012.2235816.

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Huang, Yong, Zihan Shen, Ye Wu, Xiaoqiu Wang, Shufang Zhang, Xiaoqin Shi, and Haibo Zeng. "Amorphous ZnO based resistive random access memory." RSC Advances 6, no. 22 (2016): 17867–72. http://dx.doi.org/10.1039/c5ra22728c.

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Zhao, Enming, Shuangqiang Liu, Xiaodan Liu, Chen Wang, Guangyu Liu, and Chuanxi Xing. "Flexible Resistive Switching Memory Devices Based on Graphene Oxide Polymer Nanocomposite." Nano 15, no. 09 (September 2020): 2050111. http://dx.doi.org/10.1142/s1793292020501118.

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Flexible resistive switching memory devices based on graphene oxide (GO) polymer nanocomposite were prepared on flexible substrate to research the influence of bending on resistive switching behavior. The devices showed evident response in resistive switching memory characteristics to flexible bending. The 2000 cycles flexible bending leads to the switch of resistive switching memory characteristic from write-once-read-many time memory (WORM) to static random access memory (SRAM). Both WORM and SRAM memory properties are all repeatable, and the threshold switching voltage also showed good consistency. The resistive switching mechanism is attributed to the formation of carbon-rich conductive filaments for nonvolatile WORM characteristics. The bending-induced micro-crack may be responsible for the partial broken of the electrical channels, and may lead to the volatile SRAM characteristics.
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Choi, Shinhyun, Jihang Lee, Sungho Kim, and Wei D. Lu. "Retention failure analysis of metal-oxide based resistive memory." Applied Physics Letters 105, no. 11 (September 15, 2014): 113510. http://dx.doi.org/10.1063/1.4896154.

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Bishop, S. M., H. Bakhru, S. W. Novak, B. D. Briggs, R. J. Matyi, and N. C. Cady. "Ion implantation synthesized copper oxide-based resistive memory devices." Applied Physics Letters 99, no. 20 (November 14, 2011): 202102. http://dx.doi.org/10.1063/1.3662036.

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Seul Ki Hong, Ji Eun Kim, Sang Ouk Kim, Sung-Yool Choi, and Byung Jin Cho. "Flexible Resistive Switching Memory Device Based on Graphene Oxide." IEEE Electron Device Letters 31, no. 9 (September 2010): 1005–7. http://dx.doi.org/10.1109/led.2010.2053695.

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Rani, Janardhanan R., Se-I. Oh, Jeong Min Woo, and Jae-Hyung Jang. "Low voltage resistive memory devices based on graphene oxide–iron oxide hybrid." Carbon 94 (November 2015): 362–68. http://dx.doi.org/10.1016/j.carbon.2015.07.011.

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Dissertations / Theses on the topic "OxRAM - oxide-Based resistive memory"

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Benoist, Antoine. "Pre and post breakdwon modeling of high-k dielectrics regarding antifuse and OxRAM non-volatile memories." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEI007.

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Les mémoires non volatiles intégrées représentent une part importante du marché des semi-conducteurs. Bien qu'il s'adresse à de nombreuses applications différentes, ce type de mémoire fait face à des problèmes pour poursuivre la réduction continue de la résolution des technologies CMOS. En effet, l'introduction récente de high-k et de métal pour la grille des transistors menace la compétitivité de la solution Flash. En conséquence, de nombreuses solutions émergentes sont étudiées. L'Antifuse dans le cadre des mémoires OTP est utilisée pour l'identification de puces, la configuration de circuits, la réparation de système ou le stockage de données sécurisées. La programmation Antifuse repose sur la dégradation de l'oxyde de grille de son condensateur sous haute tension. Des travaux antérieurs ont déjà apporté quelques connaissances sur les mécanismes physiques impliqués sur des technologies à oxyde de grille SiO2. De nouveaux défis découlent de l'introduction des nouveaux matériaux de grille. Un examen complet est nécessaire sur les mécanismes de dégradation des oxydes impliqués dans la programmation Antifuse. L'utilisation intensive de la haute tension suggère également d'étendre notre connaissance sur la fiabilité dans cette gamme de tension. Les états pré et post-claquage de l'oxyde de grille sous des mécanismes à haute tension sont donc étudiés dans ce manuscrit se concentrant sur les technologies CMOS les plus avancées. Une loi en puissance type TDDB a été étendue vers les hautes tensions pour être utilisée comme un modèle de temps de programmation Antifuse. L'extension de la fiabilité TDDB nous donne également un élément clé pour modéliser la durée de vie du transistor de sélection. Des paramètres de programmation tels que l'amplitude de la tension, la compliance du courant ou la température sont également étudiés et leur impact sur le rendement en courant de lecture est abordé. Cette étude nous permet de rétrécir agressivement la surface globale de la cellule sans perte de performance ni de dégradation de la fiabilité. Un processus de caractérisation Antifuse est proposé pour être retravaillé et un modèle de programmation de tension-température-dépendante est inventé. Ce manuscrit a également mis l'accent sur la modélisation de courant de cellule programmée comme la fuite d’un oxyde de grille post-claquage. Un modèle compact MOSFET dégradé est proposé et comparé à l'état de l’art. Un bon accord est trouvé pour s'adapter à la large gamme de caractérisations I (V) de la cellule programmée. L'activation de ce modèle dans un environnement de design nous a permis de simuler la dispersion des distributions de courants de cellules programmées au niveau de la taille du produit à l'aide de runs Monte-Carlo. Enfin, cette thèse s'achève autour d'une étude d'investigation OxRAM comme une solution émergente. En combinant le dispositif Antifuse avec le mécanisme de commutation résistif de l'OxRAM, une solution hybride est proposée en perspective
Embedded Non Volatile Memories represent a significant part of the semiconductor market. While it addresses many different applications, this type of memory faces issues to keep the CMOS scaling down roadmap. Indeed, the recent introduction of high-k and metal for the CMOS gate is threatening the Flash’s competitiveness. As a consequence many emerging solutions are being. The Antifuse as part of the OTP memories is fully CMOS compliant, Antifuse memories are used for Chip ID, chip configuration, system repairing or secured data storage to say the least. The Antifuse programming relies on the gate oxide breakdown of its capacitor under high voltage. Previous work already brought some knowledge about the physical mechanisms involved but mainly on SiO2 gate oxide technologies. New challenges arise from the introduction of the new gate materials. A full review is needed about the oxide breakdown mechanisms involved in the Antifuse programming. The extensive use of high voltage also suggests to extend our knowledge about reliability within this voltage range. Pre and post gate oxide breakdown under high voltage mechanisms are then deeply investigated in this manuscript focusing on the most advanced CMOS technologies. Fowler Nordheim Tunneling has been confirmed as the main mechanism responsible for the gate oxide leakage conduction under high voltage during the wearout phase even-though defect contribution has been evidenced to mainly contribute under low voltage , e.g. the virgin Antifuse leakage current. A TDDB based power law has been extended toward high voltage to be used as a robust Antifuse programming time model. Extending the TDDB reliability under high electric field also gives us key element to model the selection MOSFET time to failure. Programming parameters such as voltage amplitude, current compliance or temperature are also investigated and their impact on the Read Current Yield are tackled. This study allows us to aggressively shrink the bitcell overall area without losing performance nor degrading the reliability. This study also reveals a worst case scenario for the programming parameters when temperature is very low. As a consequence, the early Antifuse characterization process is proposed to be rework and a programming voltage-temperature-dependent solution is invented. This manuscript also focused on the Antifuse programmed cell current modeling as gate oxide post-breakdown conduction. A remaining MOSFET compact model is proposed and compared to the state of the art. Good agreement is found to fit the wide range of read current. Enabling this model within a CAD environment has allowed us to simulate the Read Current Yield dispersion at product size level using Monte-Carlo runs. Finally, this thesis wraps up around an OxRAM investigation study as a serious emerging eNVM solution. Combining the Antifuse device with the resistive switching mechanism of the OxRAM, a hybrid solution is proposed as a perspective
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Chowdhury, Madhumita. "NiOx Based Resistive Random Access Memories." University of Toledo / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1325535812.

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Labalette, Marina. "Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI037/document.

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La gestion, la manipulation et le stockage de données sont aujourd’hui de réels challenges. Pour supporter cette réalité, le besoin de technologies mémoires plus efficaces, moins énergivores, moins coûteuses à fabriquer et plus denses que les technologies actuelles s’intensifie. Parmi les technologies mémoires émergentes se trouve la technologie mémoire résistive, dans laquelle l’information est stockée sous forme de résistance électrique au sein d’une couche d’oxyde entre deux électrodes conductrices. Le plus gros frein à l’émergence de tels dispositifs mémoires résistives en matrices passives à deux terminaux est l’existence d’importants courants de fuites (ou sneak paths) venant perturber l’adressage individuel de chaque point de la matrice. Les dispositifs complementary resistive switching (CRS), consistant en deux dispositifs OxRRAM agencés dos à dos, constituent une solution performante à ces courants de fuites et sont facilement intégrables dans le back-end-of-line (BEOL) de la technologie CMOS. Cette thèse a permis d’apporter la preuve de concept de la fabrication et de l’intégration de dispositifs CRS de façon 3D monolithique dans le BEOL du CMOS
In our digital era, management, manipulation and data storage are real challenges. To support this reality the need for more efficient, less energy and money consuming memory technologies is drastically increasing. Among those emerging memory technologies we find the oxide resistive memory technology (OxRRAM), where the information is stored as the electrical resistance of a switching oxide in sandwich between two metallic electrodes. Resistive memories are really interested if used inside passive memory matrix. However the main drawback of this architecture remains related to sneak path currents occurring when addressing any point in the passive matrix. To face this problem complementary resistive switching devices (CRS), consisting in two OxRRAM back to back, have been proposed as efficient and costless BEOL CMOS compatible solution. This thesis brought the proof of concept of fabrication and 3D monolithic integration of CRS devices in CMOS BEOL
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Chen, Wenbo. "Understanding of Oxide Based Resistive Random Access Memory Devices with Multi-level Resistance States and Application." University of Toledo / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1466719077.

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Ellis, Noah. "Design, fabrication, and characterization of nano-scale cross-point hafnium oxide-based resistive random access memory." Thesis, Georgia Institute of Technology, 2016. http://hdl.handle.net/1853/55038.

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Non-volatile memory (NVM) is a form of computer memory in which the logical value (1 or 0) of a bit is retained when the computer is in its’ powered off state. Flash memory is a major form of NVM found in many computer-based technologies today, from portable solid state drives to numerous types of electronic devices. The popularity of flash memory is due in part to the successful development and commercialization of the floating gate transistor. However, as the floating gate transistor reaches its’ limits of performance and scalability, viable alternatives are being aggressively researched and developed. One such alternative is a memristor-based memory application often referred to as ReRAM or RRAM (Resistive Random Access Memory). A memristor (memory resistor) is a passive circuit element that exhibits programmable resistance when subjected to appropriate current levels. A high resistance state in the memristor corresponds to a logical ‘0’, while the low resistance state corresponds to a logical ‘1’. One memristive system currently being actively investigated is the metal/metal oxide/metal material stack in which the metal layers serve as contact electrodes for the memristor with the metal oxide providing the variable resistance functionality. Application of an appropriate potential difference across the electrodes creates oxygen vacancies throughout the thickness of the metal oxide layer, resulting in the formation of filaments of metal ions which span the metal oxide, allowing for electronic conduction through the stack. Creation and disruption of the filaments correspond to low and high resistance states in the memristor, respectively. For some time now, HfO2 has been researched and developed to serve as a high-k material for use in high performance CMOS MOSFETs. As it happens, HfO2-based RRAM devices have proven themselves as viable candidates for NVM as well, demonstrating high switching speed (< 10 ns), large OFF/ON ratio (> 100), good endurance (> 106 cycles), long lifetime, and multi-bit storage capabilities. HfO2-based RRAM is also highly scalable, having been fabricated in cells as small as 10 x 10 nm2 while still maintaining good performance. Previous work examining switching properties of micron scale HfO2-based RRAM has been performed by the Vogel group. However, a viable process for fabrication of nano-scale RRAM is required in order to continue these studies. In this work, a fabrication process for nano-scale cross-point TiN/ HfO2/TiN RRAM devices will be developed and described. Materials processing challenges will be addressed. The switching performance of devices fabricated by this process will be compared to the performance of similar devices from the literature in order to confirm process viability.
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Manjunath, Vishal Jain. "Effect Of Interfacial Top Electrode Layer On The Performance Of Niobium Oxide Based Resistive Random Access Memory." University of Cincinnati / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1552657250617694.

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Petzold, Stefan [Verfasser], Lambert [Akademischer Betreuer] Alff, and Leopoldo [Akademischer Betreuer] Molina-Luna. "Defect Engineering in Transition Metal Oxide-based Resistive Random Access Memory / Stefan Petzold ; Lambert Alff, Leopoldo Molina-Luna." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2020. http://d-nb.info/1204200912/34.

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Guenery, Pierre-Vincent. "Nanostructures d’oxyde d’indium pour les mémoires résistives RRAM intégrées en CMOS Back-End-Of-Line." Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI114.

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Les mémoires informatiques actuelles qui ne sont que l'extrême miniaturisation de la technologie développée dans les années 1960, atteignent des limites technologiques difficilement surmontables techniquement et très couteuses. Les mémoires doivent donc se réinventer par une modification profonde de leur forme, comme le développement de structures en 3 dimensions par exemple, ou par l'utilisation de technologies innovantes. C'est un phénomène récent dans le domaine des mémoires qui nous a intéressé au cours de cette thèse. Il consiste à maîtriser électriquement et de manière réversible la résistivité d'une structure pour coder de l'information de manière pérenne, d'où son nom de mémoires résistive non volatile. Un grand nombre de recherches sont menées pour comprendre et maîtriser cette technologie dont le principal défaut actuel est son manque de reproductibilité. Nous proposons une approche originale consistant à l'intégration de nanoparticules d'oxyde d'indium dans la structure d'une mémoire résistive qui est directement compatible avec les puces déjà existantes. L’intégration de particules a pour but d'aider à rendre ces mémoires plus homogènes par un contrôle du comportement électrique de la structure. L'étude menée porte dans un premier temps sur les défis liés à la fabrication de la mémoire et en particulier sur le dépôt de nanoparticules. Pour avoir un effet bénéfique, la fabrication de celles-ci doit être parfaitement maîtrisée. Nous détaillons ensuite à la caractérisation électrique des mémoires et à la compréhension des phénomènes qui sont à l’origine du changement de résistivité des matériaux afin de tenter de mieux les contrôler
The current computer memories are nothing more than the extreme miniaturization of the technology developed in the 1960s. These memories reached technological limits that are technically difficult and very costly to overcome. Memories must therefore be reinvented by a profound change in their shape, such as the development of three-dimensional structures for example, or by the use of innovative technologies. A new physical phenomenon in the field of memories interested us during this thesis. It consists in an electrically and reversibly control of the resistivity of a structure that can reach at least two level to code the information in a durable way. These memories are called non-volatile resistive memories. A lot of research is being carried out to understand and control this technology. The main current defect of this emerging technology is its lack of reproducibility. We propose an original approach consisting in the integration of indium oxide nanoparticles into the structure of a resistive memory that is directly compatible with existing chips. The purpose of particle integration is to increase the homogeneity of these memories by controlling the electrical behaviour of the structure. The study initially focused on the challenges of memory manufacturing and in particular on the deposition of nanoparticles. To have a beneficial effect, the manufacture of these products must be perfectly controlled. The study then details the electrical characterization of the memories. We discuss about the phenomena that are at the origin of the change in resistivity in order to try to better control them
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Cheng, You-Wei, and 鄭又瑋. "Oxide-Based Resistive Random Access Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/52860599754950649604.

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碩士
國立交通大學
顯示科技研究所
98
In this thesis, we demonstrate inorganic resistive random access memory (RRAM) using sputtered SiO2 thin films, and investigate the influences of electrical characteristics of the devices with various post-annealing conditions. The results show that devices with RTA treatment can exhibit better electrical characteristics, especially in the significant improvement of endurance. We also analyze carrier transport behaviors in the high conductance state of devices and propose carrier transport mechanisms under different RTA treatments. In addition, we fabricate two different structures of organic RRAM: AlOx/Alq3 bi-layer and Alq3/MoO3/Alq3 tri-layer structures. It is found that interface defects at the AlOx/Alq3 interface dominate the resistive switching of organic RRAM using the bi-layer structure, and the high ON/OFF current ratio near 106 is obtained; the switching behavior of organic RRAM using the tri-layer structure originate from carrier confinement barriers produced by the difference of energy bands between the nano-structure MoO3 and Alq3 layers, and this devices exhibit a high ON/OFF current ratio about 104 and provide many write-read-erase-read cycles.
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Prakash, Amit, and AMIT PRAKASH. "Tantalum Oxide based Nanoscale Resistive Switching Memory Devices." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/95836377974390868649.

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博士
長庚大學
電子工程學系
101
Resistive random access memory (RRAM) is a promising candidate for the next generation non-volatile memory applications due to its simple metal-insulator-metal structure, low voltage/current with high speed of operation, low power consumption, long endurance and good data retention. Tantalum oxide (TaOx) is one of the most suitable materials due to its ease of deposition, good thermal stability (>1000 oC) and having two stable phases which will help to achieve good resistive switching characteristics. In this study, resistive memory characteristics of TaOxbased devices in via-hole and cross-point structures have been investigated. Resistive memory characteristics of IrOx/TaOx/WOx/W structured memory device have been investigated and a route to improve the uniformity of key switching parameters like set/reset voltage, low/high resistance states as well as switching cycles is demonstrated by selecting the electro-formation polarity in the positive bias region. The memory devices were characterized by high-resolution transmission electron microscopy, energy dispersive X-ray spectroscopy, X-ray photo-electron spectroscopy and Auger electron spectroscopy (AES) analyses. The switching mechanism in both negative and positive voltage formed devices is explained by the filamentary conduction model with oxygen ion migration. The improvement in the case of positive formed devices is due to accumulation of O2- ions at the IrOx/TaOx interface, which acts as series resistance. The devices have shown good read endurance of >105 times and data retention of >104 s at 85 oC. In order to achieve resistive switching at low current, the memory devices with Ti as interfacial layer in W/TaOx/W and W/TaOx/TiN structures have been fabricated. The improvement is due to the defect formation in the TaOx film. The devices with TiN bottom electrode have shown good forming-free repeatable bipolar resistive switching at a small current of <50 μA with small operation voltage of ±2.5 V. The low resistance state is independent, whereas high resistance increases with decreasing device size from 8×8 to 0.15×0.15 μm2 which confirms filamentary conduction mechanism and will benefit small size (<0. 4 μm) devices in future. In addition, oxygen deficient conducting filament is investigated. Long pulse endurance of >104 cycles, data retention of >5 hours at 125 oC, read endurance of >105 cycles and high device yield of >95% have also been obtained. In order to achieve high density, devices in Ir/TaOx/W cross-point structure have been investigated. The devices exhibited good formationfree bipolar resistive switching with a low current compliance of 100 μA and a small operation voltage of ±2.5. The devices have shown narrow statistical distribution of low/high resistance states and set/reset voltage and multilevel capability by limiting the reset voltage. Robust pulse endurance of >106 program/erase cycles, read endurance of >106 times and data retention at 85 oC under a low current operation of <100 μA are also obtained. Novel sidewall small size devices (20 nm × 4 μm) with small switching current of 50 μA are explored in this study for future high density low power nanoscale nonvolatile memory applications.
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Book chapters on the topic "OxRAM - oxide-Based resistive memory"

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Nagata, Takahiro. "Switching Control of Oxide-Based Resistive Random-Access Memory by Valence State Control of Oxide." In NIMS Monographs, 69–74. Tokyo: Springer Japan, 2020. http://dx.doi.org/10.1007/978-4-431-54850-8_5.

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Nagata, Takahiro. "Bias-Induced Interfacial Redox Reaction in Oxide-Based Resistive Random-Access Memory Structure." In NIMS Monographs, 41–67. Tokyo: Springer Japan, 2020. http://dx.doi.org/10.1007/978-4-431-54850-8_4.

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Makarov, Alexander, Viktor Sverdlov, and Siegfried Selberherr. "Modeling of the SET and RESET Process in Bipolar Resistive Oxide-Based Memory Using Monte Carlo Simulations." In Numerical Methods and Applications, 87–94. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-18466-6_9.

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Conference papers on the topic "OxRAM - oxide-Based resistive memory"

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Vianello, E., D. R. B. Ly, S. La Barbera, T. Dalgaty, N. Castellani, G. Navarro, G. Bourgeois, A. Valentian, E. Nowak, and D. Querlioz. "Metal Oxide Resistive Memory (OxRAM) and Phase Change Memory (PCM) as Artificial Synapses in Spiking Neural Networks." In 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2018. http://dx.doi.org/10.1109/icecs.2018.8617869.

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Dewolf, T., D. Cooper, N. Bernier, V. Delaye, A. Grenier, H. Grampeix, C. Charpin, et al. "Investigation of Switching Mechanism in HfO2-Based Oxide Resistive Memories by In-Situ Transmission Electron Microscopy and Electron Energy Loss Spectroscopy." In ISTFA 2017. ASM International, 2017. http://dx.doi.org/10.31399/asm.cp.istfa2017p0371.

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Abstract Forming and breaking a nanometer-sized conductive area are commonly accepted as the physical phenomenon involved in the switching mechanism of oxide resistive random access memories (OxRRAM). This study investigates a state-of-the-art OxRRAM device by in-situ transmission electron microscopy (TEM). Combining high spatial resolution obtained with a very small probe scanned over the area of interest of the sample and chemical analyses with electron energy loss spectroscopy, the local chemical state of the device can be compared before and after applying an electrical bias. This in-situ approach allows simultaneous TEM observation and memory cell operation. After the in-situ forming, a filamentary migration of titanium within the dielectric hafnium dioxide layer has been evidenced. This migration may be at the origin of the conductive path responsible for the low and high resistive states of the memory.
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Ielmini, D., S. Ambrogio, and S. Balatti. "Scaling of oxide-based resistive switching devices." In 2014 14th Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2014. http://dx.doi.org/10.1109/nvmts.2014.7060839.

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Holt, Joshua, Nathaniel Cady, and Jean Yang-Scharlotta. "Radiation testing of tantalum oxide-based resistive memory." In 2015 IEEE International Integrated Reliability Workshop (IIRW). IEEE, 2015. http://dx.doi.org/10.1109/iirw.2015.7437091.

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Makarov, Alexander, Viktor Sverdlov, and Siegfried Selberherr. "Stochastic modeling hysteresis and resistive switching in bipolar oxide-based memory." In 2010 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2010). IEEE, 2010. http://dx.doi.org/10.1109/sispad.2010.5604517.

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Puglisi, Francesco Maria, Paolo Pavan, Andrea Padovani, and Luca Larcher. "A compact model of hafnium-oxide-based resistive random access memory." In 2013 International Conference on IC Design & Technology (ICICDT). IEEE, 2013. http://dx.doi.org/10.1109/icicdt.2013.6563309.

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Makarov, A., V. Sverdlov, and S. Selberherr. "Stochastic modeling of the resistive switching mechanism in oxide-based memory." In 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2010). IEEE, 2010. http://dx.doi.org/10.1109/ipfa.2010.5531994.

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Zhang, Meiyun, Shibing Long, Guoming Wang, Zhaoan Yu, Yang Li, Dinglin Xu, Hangbing Lv, et al. "The statistics of set time of oxide-based resistive switching memory." In 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). IEEE, 2016. http://dx.doi.org/10.1109/ipfa.2016.7564324.

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Makarov, Alexander, Viktor Sverdlov, and Siegfried Selberherr. "A stochastic model of bipolar resistive switching in metal-oxide-based memory." In ESSDERC 2010 - 40th European Solid State Device Research Conference. IEEE, 2010. http://dx.doi.org/10.1109/essderc.2010.5618201.

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Jiang, Zizhen, Shimeng Yu, Yi Wu, Jesse H. Engel, Ximeng Guan, and H. S. Philip Wong. "Verilog-A compact model for oxide-based resistive random access memory (RRAM)." In 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2014. http://dx.doi.org/10.1109/sispad.2014.6931558.

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Reports on the topic "OxRAM - oxide-Based resistive memory"

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Chin, Matthew L., Matin Amani, Terrence P. O'Regan, A. G. Birdwell, and Madan Dubey. Effect of Atomic Layer Depositions (ALD)-Deposited Titanium Oxide (TiO2) Thickness on the Performance of Zr40Cu35Al15Ni10 (ZCAN)/TiO2/Indium (In)-Based Resistive Random Access Memory (RRAM) Structures. Fort Belvoir, VA: Defense Technical Information Center, August 2015. http://dx.doi.org/10.21236/ada623815.

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