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Dissertations / Theses on the topic 'Parallel information processing'
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1
Nicholas, Julian Jesuratnam. "Information processing in #parallel' visual pathways." Thesis, University of Oxford, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.386633.
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Ruokamo, A. (Ari). "Parallel computing and parallel programming models:application in digital image processing in mobile systems and personal mobile devices." Bachelor's thesis, University of Oulu, 2018. http://urn.fi/URN:NBN:fi:oulu-201802271269.
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Today powerful parallel computer architectures empower numerous application areas in personal computing and consumer electronics and parallel computation is an established mainstay in personal mobile devices (PMD). During last ten years PMDs have been equipped with increasingly powerful parallel computation architectures (CPU+GPU) enabling rich gaming, photography and multimedia experiences ultimately general purpose parallel computation through application programming interfaces.
This study views into current status of parallel computing and parallel programming, and specifically its application and practices of digital image processing applied in the domain of Mobile Systems (MS) and Personal Mobile Devices (PMD). The application of parallel computing and -programming has become more common today with the changing user-application requirements and with the increased requirements of sustained high-performance applications and functionality. Furthermore, the paradigm shift of data consumption in personal computing towards PMD and mobile devices is under increased interest. The history of parallel computation in MS and PMD is relatively new topic in academia and industry. The literature study revealed that while there is good amount of new application specific research emerging in this domain, the foundations of dominant and common parallel programming paradigms in the area of MS and PMD are still moving targets.
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Kilpatrick, Carol Elizabeth. "Capture and display of performanced information for parallel and distributed applications." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/8193.
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Stewart, Andrew James. "The time course of the influence of implicit causality information on resolving anaphors." Thesis, University of Glasgow, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241894.
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Evans, Greg. "Concurrent processing of visual and auditory information : an assessment of parallel versus sequential processing models /." Title page, contents and summary only, 1994. http://web4.library.adelaide.edu.au/theses/09PH/09phe922.pdf.
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Wiles, Janet. "Studies of problems related to parallel distributed associative models of memory." Thesis, The University of Sydney, 1988. https://hdl.handle.net/2123/26291.
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Parallel distributed associative (PDA) models are a new approach to the study of cognition. They lie between neuroscience and traditional psychological level computation. The PDA paradigm departs from the Rationalist tradition which is a logical, language-based approach to cognition and aims to provide a formal description of cognitive processes at the subsymbolic level using distributed memory structures and distributed control.
The first part of this thesis describes an analysis of a PDA model, the Memory Surface Model (MSM) developed by Goldschlager (1984), and compares it to other models in the same paradigm.
The second part concerns the implications of FDA models in developing high level primitives for cognitive processes. A method of representing concepts in PDA models is described, and it is shown that the acquisition of optimal concept prototypes and the communication of concepts in the model are intractable in general. A preliminary study using Johnson-Laird's theory of mental models to provide rational reasoning without an innate logical inference mechanism is described. This is discussed with respect to results of experiments described in the psychological literature.
This thesis investigates the feasibility of FDA models as an approach to studying cognition. It discusses how a distributed architecture could support high level primitives, and some effects of the use of those primitives in cognitive studies.
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Kalliomäki, Jarkko. "Parallel processing of nociceptive information evidence for multiple reflex and ascending nociceptive pathways /." Lund : Dept. of Physiology and Biophysics, University of Lund, 1992. http://books.google.com/books?id=PMlqAAAAMAAJ.
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Ruokamo, A. (Ari). "Building an image- and video processing application on Apple iOS platform using a parallel programming model." Master's thesis, University of Oulu, 2018. http://urn.fi/URN:NBN:fi:oulu-201805091684.
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Today powerful parallel computer architectures empower numerous application areas in personal computing and consumer electronics and parallel computation is an established mainstay in personal mobile devices (PMD). During last ten years PMDs have been equipped with increasingly powerful parallel computation architectures (CPU+GPU) enabling rich gaming, photography and multimedia experiences and general purpose parallel computation through application programming interfaces such as OpenGL ES and Apple Metal.
Using a narrative literature review this study viewed into current status of parallel computing and parallel programming and specifically its application and practices of digital image processing applied in the domain of Mobile Systems (MS) and Personal Mobile Devices (PMD). While the research on the context is an emerging topic, there still is a limited amount of research available on the topic. As acknowledged in the literature and in the practice, the OpenGL ES programming model for computing tasks can be a challenging environment for many programmers. With OpenGL ES, the paradigm shift from serial- to parallel programming, in addition to changes and challenges in used programming language and the tools supporting the development, can be a barrier for many programmers.
In this thesis a Design Science Research (DSR) approach was applied to build an artefact — an image- and video processing application on Apple iOS software platform using OpenGL ES parallel programming model. An Open Source Software (OSS) parallel computing library GPUImage was applied in the implementation of the artefact filtering- and effects functionality. Using the library, the process of applying the parallel programming model was efficient and productive. The used library structures and functionality were effectively suppressing the complexity of OpenGL ES setup- and management programming and provided efficient filter structures for implementing image- and video filters and effects. The application filtering performance was measured in real-time- and post-processing cases and was perceived as good, alongside the feedback collected from demonstration sessions and end-users.
However, designing new custom cinematic filters using OpenGL ES Shading Language is a challenging task and requires a great deal of specific knowledge of technical aspects of the OpenGL ES domain. The used programming language (OpenGL ES Shading Language) and tools supporting the work process of design, implementation and debugging of the GPU program algorithms were not optimal in terms of applicability and productivity. Findings note, that more generic and applicable language would benefit the development of parallel computation applications on PMD platforms.
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Chan, C. F. "Low bit-rate speech coding : A parallel processing approach using digital signal processors." Thesis, University of Essex, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.375652.
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Wu, Yuk Ying. "Movie allocation in parallel video servers /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?COMP%202002%20WU.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.<br>Includes bibliographical references (leaves 69-76). Also available in electronic version. Access restricted to campus users.
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Chelliah, M. "A Compiler and Symbolic Debugger for Occam." Thesis, Indian Institute of Science, 1989. https://etd.iisc.ac.in/handle/2005/77.
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We have implemented Occam, a parallel programming language, on a uniprocessor machine (MC-68020 based HORIZON I11 running on UNIX system V.2) with simulated concurrency. Occam is a descendant of CSP with a few convenient modifications like channels used for communication and procedures. Two additions to the original language, i.e., output guards and recursion have been proposed. Front end of the compiler was developed using LEX and YACC. An innovative code generator, generator based on tree pattern matching has been used to generate the back end of the compiler, which generates efficient MC-68020 assembly code. A kernel for process administration is the runtime support provided. It has been developed entirely in ' C ' and made available as a library. This is linked with the assembly module to generate the executable version of the input Occam program.
We have also interfaced our Occam compiler with Unix system V.2 source level debugger 'Sdb' so as to provide debugging support for Occam programmers. Issues involved in parallel debugging have been investigated and those demanding minimum effort have been incorporated in Occam debugger by modifying the runtime support of the uniprocessor implementation.
Modifications to the uniprocessor implementation so as to make it run on a shared memory multiprocessor machine(HCL MAGNUM-P with four MC-68030 processors) are also discussed. The support provided by MAGNUM-P at the architecture and operating system levels is explained in detail. Our Occam compiler for the multiprocessor generates code, but the generated code has not been tested since the machine is not yet ready.
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Chelliah, M. "A Compiler and Symbolic Debugger for Occam." Thesis, Indian Institute of Science, 1989. http://hdl.handle.net/2005/77.
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We have implemented Occam, a parallel programming language, on a uniprocessor machine (MC-68020 based HORIZON I11 running on UNIX system V.2) with simulated concurrency. Occam is a descendant of CSP with a few convenient modifications like channels used for communication and procedures. Two additions to the original language, i.e., output guards and recursion have been proposed. Front end of the compiler was developed using LEX and YACC. An innovative code generator, generator based on tree pattern matching has been used to generate the back end of the compiler, which generates efficient MC-68020 assembly code. A kernel for process administration is the runtime support provided. It has been developed entirely in ' C ' and made available as a library. This is linked with the assembly module to generate the executable version of the input Occam program.
We have also interfaced our Occam compiler with Unix system V.2 source level debugger 'Sdb' so as to provide debugging support for Occam programmers. Issues involved in parallel debugging have been investigated and those demanding minimum effort have been incorporated in Occam debugger by modifying the runtime support of the uniprocessor implementation.
Modifications to the uniprocessor implementation so as to make it run on a shared memory multiprocessor machine(HCL MAGNUM-P with four MC-68030 processors) are also discussed. The support provided by MAGNUM-P at the architecture and operating system levels is explained in detail. Our Occam compiler for the multiprocessor generates code, but the generated code has not been tested since the machine is not yet ready.
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Lundqvist, Viktor. "A smoothed particle hydrodynamic simulation utilizing the parallel processing capabilites of the GPUs." Thesis, Linköping University, Department of Science and Technology, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-21761.
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<p>Simulating fluid behavior has proven to be a demanding challenge which requires complex computational models and highly efficient data structures. Smoothed Particle Hydrodynamics (SPH) is a particle based computational model used to simulate fluid behavior that has been found capable of producing convincing results. However, the SPH algorithm is computational heavy which makes it cumbersome to work with.</p><p>This master thesis describes how the SPH algorithm can be accelerated by utilizing the GPU’s computational resources. It describes a model for how to distribute the work load on the GPU and presents a suitable data structure. In addition, it proposes a method to represent and handle moving objects in the fluids surroundings. Finally, the performance gain due to the GPU is evaluated by comparing processing times with an identical implementation running solely on the CPU.</p>
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Britton, Matthew Scott. "Stochastic task scheduling in time-critical information delivery systems." Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09phb8629.pdf.
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"January 2003" Includes bibliographical references (leaves 120-129) Presents performance analyses of dynamic, stochastic task scheduling policies for a real- time-communications system where tasks lose value as they are delayed in the system.
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Rex, David Bruce. "Object Parallel Spatio-Temporal Analysis and Modeling System." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/1278.
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The dissertation will outline an object-oriented model from which a next-generation GIS can be derived. The requirements for a spatial information analysis and modeling system can be broken into three primary functional classes: data management (data classification and access), analysis (modeling, optimization, and simulation) and visualization (display of data). These three functional classes can be considered as the primary colors of the spectrum from which the different shades of spatial analysis are composed. Object classes will be developed which will be designed to manipulate the three primary functions as required by the user and the data.
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Saini, Shivam. "Spark on Kubernetes using HopsFS as a backing store : Measuring performance of Spark with HopsFS for storing and retrieving shuffle files while running on Kubernetes." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-285561.
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Data is a raw list of facts and details, such as numbers, words, measurements or observations that is not useful for us all by itself. Data processing is a technique that helps to process the data in order to get useful information out of it. Today, the world produces huge amounts of data that can not be processed using traditional methods. Apache Spark (Spark) is an open-source distributed general-purpose cluster computing framework for large scale data processing. In order to fulfill its task, Spark uses a cluster of machines to process the data in a parallel fashion. External shuffle service is a distributed component of Apache Spark cluster that provides resilience in case of a machine failure. A cluster manager helps spark to manage the cluster of machines and provide Spark with the required resources to run the application. Kubernetes is a new cluster manager that enables Spark to run in a containerized environment. However, running external shuffle service is not possible while running Spark using Kubernetes as the resource manager. This highly impacts the performance of Spark applications due to the failed tasks caused by machine failures. As a solution to this problem, the open source Spark community has developed a plugin that can provide the similar resiliency as provided by the external shuffle service. When used with Spark applications, the plugin asynchronously back-up the data onto an external storage. In order not to compromise the Spark application performance, it is important that the external storage provides Spark with a minimum latency. HopsFS is a next generation distribution of Hadoop Distributed Filesystem (HDFS) and provides special support to small files (<64 KB) by storing them in a NewSQL database and thus enabling it to provide lower client latencies. The thesis work shows that HopsFS provides 16% higher performance to Spark applications for small files as compared to larger ones. The work also shows that using the plugin to back-up Spark data on HopsFS can reduce the total execution time of Spark applications by 20%-30% as compared to recalculation of tasks in case of a node failure.<br>Data är en rå lista över fakta och detaljer, som siffror, ord, mätningar eller observationer som inte är användbara för oss alla i sig. Databehandling är en teknik som hjälper till att bearbeta data för att få användbar information ur den. Idag producerar världen enorma mängder data som inte kan bearbetas med traditionella metoder. Apache Spark (Spark) är en öppen källkod distribuerad ram för allmänt ändamål kluster dator för storskalig databehandling. För att fullgöra sin uppgift använder Spark ett kluster av maskiner för att bearbeta data på ett parallellt sätt. Extern shuffle-tjänst är en distribuerad komponent i Apache Spark-klustret som ger motståndskraft vid maskinfel. En klusterhanterare hjälper gnista att hantera kluster av maskiner och förse Spark med de resurser som krävs för att köra applikationen. Kubernetes är en ny klusterhanterare som gör att Spark kan köras i en containeriserad miljö. Det är dock inte möjligt att köra extern shuffle-tjänst när du kör Spark med Kubernetes som resurshanterare. Detta påverkar starkt prestanda för Spark-applikationer på grund av misslyckade uppgifter orsakade av maskinfel. Som en lösning på detta problem har Spark-communityn med öppen källkod utvecklat ett plugin-program som kan tillhandahålla liknande motståndskraft som tillhandahålls av den externa shuffle-tjänsten. När det används med Spark- applikationer säkerhetskopierar plugin-programmet asynkront data till en extern lagring. För att inte kompromissa med Spark-applikationsprestandan är det viktigt att det externa lagret ger Spark en minimal latens. HopsFS är en nästa generations distribution av Hadoop Distribuerat filsystem (HDFS) och ger specialstöd till små filer (<64 kB) genom att lagra dem i en NewSQL-databas och därmed möjliggöra lägre klientfördröjningar. Examensarbetet visar att HopsFS ger 16 % högre prestanda till Spark-applikationer för små filer jämfört med större. Arbetet visar också att användning av plugin för att säkerhetskopiera Spark-data på HopsFS kan minska den totala körningstiden för Spark-applikationer med 20 % - 30 % jämfört med omberäkning av uppgifter i händelse av ett nodfel.
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Clarke, Thomas James Woodchurch. "General theory relating to the implementation of concurrent symbolic computation." Thesis, Cambridge [Cambridgeshire] : University of Cambridge, Computer Laboratory, 1989. http://catalog.hathitrust.org/api/volumes/oclc/20796926.html.
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Berthou, Gautier. "Implementation of an object-detection algorithm on a CPU+GPU target." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-206178.
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Systems like autonomous vehicles may require real time embedded image processing under hardware constraints. This paper provides directions to design time and resource efficient Haar cascade detection algorithms. It also reviews some software architecture and hardware aspects. The considered algorithms were meant to be run on platforms equipped with a CPU and a GPU under power consumption limitations. The main aim of the project was to design and develop real time underwater object detection algorithms. However the concepts that are presented in this paper are generic and can be applied to other domains where object detection is required, face detection for instance. The results show how the solutions outperform OpenCV cascade detector in terms of execution time while having the same accuracy.<br>System så som autonoma vehiklar kan kräva inbyggd bildbehandling i realtid under hårdvarubegränsningar. Denna uppsats tillhandahåller anvisningar för att designa tidsoch resurseffektiva Haar-kasad detekterande algoritmer. Dessutom granskas en del mjukvaruarkitektur och hårdvaruaspekter. De avsedda algoritmerna är menade att användas på plattformar försedda med en CPU och en GPU under begränsad energitillgång. Det huvudsakliga målet med projektet var att designa och utveckla realtidsalgoritmer för detektering av objekt under vatten. Dock är koncepten som presenteras i arbetet generiska och kan appliceras på andra domäner där objektdetektering kan behövas, till exempel vid detektering av ansikten. Resultaten visar hur lösningarna överträffar OpenCVs kaskaddetektor beträffande exekutionstid och med samtidig lika stor träffsäkerhet.
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Kumar, Mohan J. "Architecture, Performance and Applications of a Hierarchial Network of Hypercubes." Thesis, Indian Institute of Science, 1992. https://etd.iisc.ac.in/handle/2005/3925.
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This thesis, presents a multiprocessor topology, the hierarchical network of hyper-cubes, which has a low diameter, low degree of connectivity and yet exhibits hypercube like versatile characteristics. The hierarchical network of hyper-cubes consists of k-cubes interconnected in two or more hierarchical levels. The network has a hierarchical, expansive, recursive structure with a constant pre-defined building block. The basic building block of the hierarchical network of hyper-cubes comprises of a k-cube of processor elements and a network controller. The hierarchical network of hyper-cubes retains the positive features of the k-cube at different levels of hierarchy and has been found to perform better than the binary hypercube in executing a variety of application problems. The ASCEND/DESCEND class of algorithms can be executed in O(log2 N) parallel steps (N is the number of data elements) on a hierarchical network of hypercubes with N processor elements. A description of the topology of the hierarchical network of hypercubes is presented and its architectural potential in terms of fault-tolerant message routing, executing a class of highly parallel algorithms, and in simulating artificial neural networks is analyzed. Further, the proposed topology is found to be very efficient in executing multinode broadcast and total exchange algorithms. We subsequently, propose an improvisation of the network to counter faults, and explore implementation of artificial neural networks to demonstrate efficient implementation of application problems on the network. The fault-tolerant capabilities of the hierarchical network of hypercubes with two network controllers per k-cube of processor elements are comparable to those of the hypercube and the folded hypercube.
We also discuss various issues related to the suitability of multiprocessor architectures for simulating neural networks. Performance analysis of ring, hypercube, mesh and hierarchical network of hypercubes for simulating artificial neural networks is presented. Our studies reveal that the performance of the hierarchical network of hypercubes is better than those of ring, mesh, hypernet and hypercube topologies in implementing artificial neural networks.
Design and implementation aspects of hierarchical network of hypercubes based on two schemes, viz., dual-ported RAM communication, and transputers are also presented. Results of simulation studies for robotic applications using neural network paradigms on the transputer-based hierarchical network of hypercubes reveal that the proposed network can produce fast response times of the order of hundred microseconds.
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Kumar, Mohan J. "Architecture, Performance and Applications of a Hierarchial Network of Hypercubes." Thesis, Indian Institute of Science, 1992. http://hdl.handle.net/2005/53.
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This thesis, presents a multiprocessor topology, the hierarchical network of hyper-cubes, which has a low diameter, low degree of connectivity and yet exhibits hypercube like versatile characteristics. The hierarchical network of hyper-cubes consists of k-cubes interconnected in two or more hierarchical levels. The network has a hierarchical, expansive, recursive structure with a constant pre-defined building block. The basic building block of the hierarchical network of hyper-cubes comprises of a k-cube of processor elements and a network controller. The hierarchical network of hyper-cubes retains the positive features of the k-cube at different levels of hierarchy and has been found to perform better than the binary hypercube in executing a variety of application problems. The ASCEND/DESCEND class of algorithms can be executed in O(log2 N) parallel steps (N is the number of data elements) on a hierarchical network of hypercubes with N processor elements. A description of the topology of the hierarchical network of hypercubes is presented and its architectural potential in terms of fault-tolerant message routing, executing a class of highly parallel algorithms, and in simulating artificial neural networks is analyzed. Further, the proposed topology is found to be very efficient in executing multinode broadcast and total exchange algorithms. We subsequently, propose an improvisation of the network to counter faults, and explore implementation of artificial neural networks to demonstrate efficient implementation of application problems on the network. The fault-tolerant capabilities of the hierarchical network of hypercubes with two network controllers per k-cube of processor elements are comparable to those of the hypercube and the folded hypercube.
We also discuss various issues related to the suitability of multiprocessor architectures for simulating neural networks. Performance analysis of ring, hypercube, mesh and hierarchical network of hypercubes for simulating artificial neural networks is presented. Our studies reveal that the performance of the hierarchical network of hypercubes is better than those of ring, mesh, hypernet and hypercube topologies in implementing artificial neural networks.
Design and implementation aspects of hierarchical network of hypercubes based on two schemes, viz., dual-ported RAM communication, and transputers are also presented. Results of simulation studies for robotic applications using neural network paradigms on the transputer-based hierarchical network of hypercubes reveal that the proposed network can produce fast response times of the order of hundred microseconds.
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Postec, Hervé. "Architecture d'un systeme d'acquisition multiprocesseur." Caen, 1987. http://www.theses.fr/1987CAEN2025.
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Torzynski, Marc. "Reseaux de neurones formels : proprietes du modele de hopfield, realisations electroniques et optiques." Université Louis Pasteur (Strasbourg) (1971-2008), 1988. http://www.theses.fr/1988STR13230.
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On etudie un modele neuro-mimetique de traitement d'information, susceptible d'etre utilise comme une memoire associative. En premiere partie, on etudie les proprietes du modele et l'on quantifie la capacite memoire. Par simulation numerique, la tolerance du reseau a ses propres deficiences et ses facultes d'associativite. On montre theoriquement plusieurs points relatifs a l'information a l'aide d'une approche probabiliste du modele. En seconde partie, on etudie les possibilites d'implantation du modele
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Sheng, Yunlong. "Processeur optique de traitement en temps réel d'images vidéo : Application au calcul optique des moments bidimensionnels des images." Besançon, 1986. http://www.theses.fr/1986BESA2032.
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Dispositif optique de calcul analogique des moments d'images en éclairage incohérent. Calcul en parallèle des dix premiers moments bidimensionnels de l'image grâce a une matrice de masques photographiques codant optiquement les noyaux des différentes intégrales de moments. Un microordinateur effectue les opérations de reconnaissance de formes sur ce petit nombre de caractéristiques statistiques extraites optiquement. Le processeur optique réalise est enfin utilise pour l'identification de pages manuscrites saisies en temps réel par camera vidéo et classées par un microordinateur gérant les moments des pages calculées optiquement
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Derzapf, Evgenij [Verfasser], and Michael [Akademischer Betreuer] Guthe. "Parallel Mesh Processing / Evgenij Derzapf. Betreuer: Michael Guthe." Marburg : Philipps-Universität Marburg, 2012. http://d-nb.info/1028072422/34.
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Jaedicke, Michael [Verfasser]. "New concepts for parallel object relational query processing / M. Jaedicke." Berlin, 2001. http://d-nb.info/965553345/34.
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Burnod, Yves. "Modèle de cortex cérébral et implémentation sur un réseau de processeurs parallèles." Angers, 1988. http://www.theses.fr/1988ANGE0005.
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Un modèle théorique du cortex cérébral est proposé. Il est basé sur les connaissances actuelles en neurobiologie et fournit un type original de réseau de neurones pour intégrer les différentes fonctions de l'intelligence artificielle : reconnaissance des formes, positionnement moteur dans l'espace, programmation et langage. Ce modèle peut aider à résoudre les problèmes de communication entre des traitements concurrents effectues sur des ensembles hétérogènes d'informations, usuelles, auditives, motrices et symboliques.
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Shenoy, U. Nagaraj. "Automatic Data Partitioning By Hierarchical Genetic Search." Thesis, Indian Institute of Science, 1996. https://etd.iisc.ac.in/handle/2005/172.
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The introduction of languages like High Performance Fortran (HPF) which allow the programmer to indicate how the arrays used in the
program have to be distributed across the local memories of a multi-computer has not completely unburdened the parallel programmer from the intricacies of these architectures. In order to tap the full potential of these architectures, the compiler has to perform this crucial task of data partitioning automatically. This would not only
unburden the programmer but would make the programs more efficient since the compiler can be made more intelligent to take care of the
architectural nuances.
The topic of this thesis namely the automatic data partitioning deals with finding the best data partition for the various arrays used in
the entire program in such a way that the cost of execution of the entire program is minimized. The compiler could resort to runtime redistribution of the arrays at various points in the program if found profitable. Several aspects of this problem have been proven to be NP-complete. Other researchers have suggested heuristic solutions to solve this problem. In this thesis we propose a genetic algorithm namely the Hierarchical Genetic Search algorithm to solve this problem.<br>CDAC
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Shenoy, U. Nagaraj. "Automatic Data Partitioning By Hierarchical Genetic Search." Thesis, Indian Institute of Science, 1996. http://hdl.handle.net/2005/172.
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CDAC<br>The introduction of languages like High Performance Fortran (HPF) which allow the programmer to indicate how the arrays used in the
program have to be distributed across the local memories of a multi-computer has not completely unburdened the parallel programmer from the intricacies of these architectures. In order to tap the full potential of these architectures, the compiler has to perform this crucial task of data partitioning automatically. This would not only
unburden the programmer but would make the programs more efficient since the compiler can be made more intelligent to take care of the
architectural nuances.
The topic of this thesis namely the automatic data partitioning deals with finding the best data partition for the various arrays used in
the entire program in such a way that the cost of execution of the entire program is minimized. The compiler could resort to runtime redistribution of the arrays at various points in the program if found profitable. Several aspects of this problem have been proven to be NP-complete. Other researchers have suggested heuristic solutions to solve this problem. In this thesis we propose a genetic algorithm namely the Hierarchical Genetic Search algorithm to solve this problem.
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Wang, Chaoli. "A multiresolutional approach for large data visualization." Columbus, Ohio : Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1164730737.
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Lu, Jiamin [Verfasser]. "Parallel SECONDO : processing moving objects data at large scale / Jiamin Lu." Hagen : Fernuniversität Hagen, 2014. http://d-nb.info/1057895512/34.
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Аркатов, Денис Борисович. "Моделі та інформаційна технологія диспетчеризації руху для залізничного транспорту в умовах часових обмежень". Thesis, НТУ "ХПІ", 2016. http://repository.kpi.kharkov.ua/handle/KhPI-Press/22744.
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Дисертація на здобуття наукового ступеня кандидата технічних наук за спеціальністю 05.13.06 – інформаційні технології. – Національний технічний університет "Харківський політехнічний інститут", Харків, 2016.
У дисертаційній роботі вирішена актуальна науково-практична задача підвищення безпеки руху та ефективності перевезень за рахунок мінімізації витрат на диспетчерське управління шляхом зниження часу обробки навігаційних даних та прийняття рішень на основі розробки моделей та інформаційної технології диспетчеризації залізничного транспорту. Проведено аналіз основних проблем залізниці України, огляд її сучасного стану. Розроблено формальну модель задачі диспетчеризації руху, запропоновано класифікацію ситуацій порушення умов безпеки руху, які виникають під час руху залізничного транспорту. Розроблено схему інформаційного обміну системи диспетчеризації руху та імітаційну модель передачі навігаційних даних. Запропоновано схему функціонування підсистеми диспетчеризації руху, розроблено алгоритм визначення множини потягів, що знаходяться в ситуації порушення умов безпеки руху. Розроблено модель диспетчеризації руху диспетчерських зон в паралельному режимі та модель паралельної обробки даних, запропоновано алгоритм визначення ефективності паралельного алгоритму. Запропоновано формальне представлення мультиагентної системи диспетчеризації руху, розроблено алгоритм вирішення задачі диспетчеризації з використанням мультиагентного підходу. Представлено аналіз економічної ефективності використання інформаційної технології диспетчеризації руху в диспетчерському управлінні залізничного транспорту. Результати впроваджено у діяльність ВП "Основ'янська колійно-машинна станція" регіональної філії "Південна залізниця" ПАТ "Українська залізниця", ТОВ "Сайтосс", а також у навчальний процес кафедри програмної інженерії та інформаційних технологій управління НТУ "ХПІ".<br>Thesis for a candidate degree in technical science, specialty 05.13.06 – Information Technologies. – National Technical University "Kharkiv Polytechnic Institute", Kharkiv, 2016.
In this thesis the topical scientific and practical problem is solved, which is improving road safety and transport efficiency by minimizing the costs of dispatching management by reducing the navigational data processing time and decision-making through the development of models and information technology of railway traffic dispatching. The main problems analysis of the railway Ukraine, a review of its current state is performed. Developed formal model of task scheduling motion classification conflicts that arise when driving railway transport. Developed the scheme of information exchange systems, scheduling the movement developed simulation model transfer navigation data. Developed the operation scheme of the subsystem dispatching movement algorithm determining a plurality of conflicting impulses. Developed the model of traffic scheduling dispatch zones in parallel mode, developed a model of parallel processing, an algorithm for determining the efficiency of the parallel algorithm. Invited a formal presentation of multi-agent scheduling system movement algorithm for solving the problem of scheduling using multi-agent approach. The analysis of the economic efficiency of the information technology use in the traffic scheduling dispatch management of railway transport is performed. The results are implemented in the process of scheduling and correction the regional branch "Ukrainian Railways" timetable, computer firm "Saytoss" and in the educational process of Computer-Aided Management Systems Department of NTU "KhPI".
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Аркатов, Денис Борисович. "Моделі та інформаційна технологія диспетчеризації руху для залізничного транспорту в умовах часових обмежень". Thesis, НТУ "ХПІ", 2016. http://repository.kpi.kharkov.ua/handle/KhPI-Press/22743.
Full textAbstract:
Дисертація на здобуття наукового ступеня кандидата технічних наук за спеціальністю 05.13.06 – інформаційні технології. – Національний технічний університет "Харківський політехнічний інститут", Харків, 2016.
У дисертаційній роботі вирішена актуальна науково-практична задача підвищення безпеки руху та ефективності перевезень за рахунок мінімізації витрат на диспетчерське управління шляхом зниження часу обробки навігаційних даних та прийняття рішень на основі розробки моделей та інформаційної технології диспетчеризації залізничного транспорту. Проведено аналіз основних проблем залізниці України, огляд її сучасного стану. Розроблено формальну модель задачі диспетчеризації руху, запропоновано класифікацію ситуацій порушення умов безпеки руху, які виникають під час руху залізничного транспорту. Розроблено схему інформаційного обміну системи диспетчеризації руху та імітаційну модель передачі навігаційних даних. Запропоновано схему функціонування підсистеми диспетчеризації руху, розроблено алгоритм визначення множини потягів, що знаходяться в ситуації порушення умов безпеки руху. Розроблено модель диспетчеризації руху диспетчерських зон в паралельному режимі та модель паралельної обробки даних, запропоновано алгоритм визначення ефективності паралельного алгоритму. Запропоновано формальне представлення мультиагентної системи диспетчеризації руху, розроблено алгоритм вирішення задачі диспетчеризації з використанням мультиагентного підходу. Представлено аналіз економічної ефективності використання інформаційної технології диспетчеризації руху в диспетчерському управлінні залізничного транспорту. Результати впроваджено у діяльність ВП "Основ'янська колійно-машинна станція" регіональної філії "Південна залізниця" ПАТ "Українська залізниця", ТОВ "Сайтосс", а також у навчальний процес кафедри програмної інженерії та інформаційних технологій управління НТУ "ХПІ".<br>Thesis for a candidate degree in technical science, specialty 05.13.06 – Information Technologies. – National Technical University "Kharkiv Polytechnic Institute", Kharkiv, 2016.
In this thesis the topical scientific and practical problem is solved, which is improving road safety and transport efficiency by minimizing the costs of dispatching management by reducing the navigational data processing time and decision-making through the development of models and information technology of railway traffic dispatching. The main problems analysis of the railway Ukraine, a review of its current state is performed. Developed formal model of task scheduling motion classification conflicts that arise when driving railway transport. Developed the scheme of information exchange systems, scheduling the movement developed simulation model transfer navigation data. Developed the operation scheme of the subsystem dispatching movement algorithm determining a plurality of conflicting impulses. Developed the model of traffic scheduling dispatch zones in parallel mode, developed a model of parallel processing, an algorithm for determining the efficiency of the parallel algorithm. Invited a formal presentation of multi-agent scheduling system movement algorithm for solving the problem of scheduling using multi-agent approach. The analysis of the economic efficiency of the information technology use in the traffic scheduling dispatch management of railway transport is performed. The results are implemented in the process of scheduling and correction the regional branch "Ukrainian Railways" timetable, computer firm "Saytoss" and in the educational process of Computer-Aided Management Systems Department of NTU "KhPI".
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Warneke, Daniel [Verfasser], and Odej [Akademischer Betreuer] Kao. "Massively Parallel Data Processing on Infrastructure as a Service Platforms / Daniel Warneke. Betreuer: Odej Kao." Berlin : Universitätsbibliothek der Technischen Universität Berlin, 2011. http://d-nb.info/1016533292/34.
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Sonntag, Sören [Verfasser]. "Performance Evaluation of Parallel Packet-Processing Architectures Using SystemC-based Modeling and Refinement / Sören Sonntag." Aachen : Shaker, 2007. http://d-nb.info/1170527558/34.
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Coimbra, Andre Rodrigues. "Método automático para descoberta de funções de ordenação utilizando programação genética paralela em GPU." Universidade Federal de Goiás, 2014. http://repositorio.bc.ufg.br/tede/handle/tede/4525.
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Previous issue date: 2014-03-28<br>Ranking functions have a vital role in the performance of information retrieval systems
ensuring that documents more related to the user’s search need – represented as a query
– are shown in the top results, preventing the user from having to examine a range of
documents that are not really relevant.
Therefore, this work uses Genetic Programming (GP), an Evolutionary Computation
technique, to find ranking functions automaticaly and systematicaly. Moreover, in this
project the technique of GP was developed following a strategy that exploits parallelism
through graphics processing units.
Other known methods in the context of information retrieval as classification committees
and the Lazy strategy were combined with the proposed approach – called Finch. These
combinations were only feasible due to the GP nature and the use of parallelism.
The experimental results with the Finch, regarding the ranking functions quality, surpassed
the results of several strategies known in the literature. Considering the time performance,
significant gains were also achieved. The solution developed exploiting the
parallelism spends around twenty times less time than the solution using only the central
processing unit.<br>Funções de ordenação têm um papel vital no desempenho de sistemas de recuperação de
informação garantindo que os documentos mais relacionados com o desejo do usuário –
representado através de uma consulta – sejam trazidos no topo dos resultados, evitando
que o usuário tenha que analisar uma série de documentos que não sejam realmente
relevantes.
Assim, utiliza-se a Programação Genética (PG), uma técnica da Computação Evolucionária,
para descobrir de forma automática e sistemática funções de ordenação. Além disso,
neste trabalho a técnica de PG foi desenvolvida seguindo uma estratégia que explora o
paralelismo através de unidades gráficas de processamento.
Foram agregados ainda na abordagem proposta – denominada Finch – outros métodos
conhecidos no contexto de recuperação de informação como os comitês de classificação e
a estratégia Lazy. Sendo que essa complementação só foi viável devido a natureza da PG
e em virtude da utilização do paralelismo.
Os resultados experimentais encontrados com a Finch, em relação à qualidade das funções
de ordenação descobertas, superaram os resultados de diversas estratégias conhecidas
na literatura. Considerando o desempenho da abordagem em função do tempo, também
foram alcançados ganhos significativos. A solução desenvolvida explorando o paralelismo
gasta, em média, vinte vezes menos tempo que a solução utilizando somente a unidade
central de processamento.
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Höger, Mareike Ruth [Verfasser], Odej [Akademischer Betreuer] Kao, Odej [Gutachter] Kao, Ivona [Gutachter] Brandic, and Volker [Gutachter] Markl. "Fault tolerance in parallel data processing systems / Mareike Ruth Höger ; Gutachter: Odej Kao, Ivona Brandic, Volker Markl ; Betreuer: Odej Kao." Berlin : Technische Universität Berlin, 2019. http://d-nb.info/1198307935/34.
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Stotz, Hermann Wilhelm Richard [Verfasser], Harald [Akademischer Betreuer] Räcke, Heiko [Gutachter] Röglin, and Harald [Gutachter] Räcke. "Scheduling algorithms for parallel processing and buffering problems / Hermann Wilhelm Richard Stotz ; Gutachter: Heiko Röglin, Harald Räcke ; Betreuer: Harald Räcke." München : Universitätsbibliothek der TU München, 2020. http://d-nb.info/1240832648/34.
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Lohrmann, Björn [Verfasser], Odej [Akademischer Betreuer] Kao, Odej [Gutachter] Kao, Johann-Christoph [Gutachter] Freytag, and Kai-Uwe [Gutachter] Sattler. "Massively parallel stream processing with latency guarantees / Björn Lohrmann ; Gutachter: Odej Kao, Johann-Christoph Freytag, Kai-Uwe Sattler ; Betreuer: Odej Kao." Berlin : Technische Universität Berlin, 2016. http://d-nb.info/1156181100/34.
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Sulewski, Damian [Verfasser], Stefan [Akademischer Betreuer] Edelkamp, and Bernhard [Akademischer Betreuer] Steffen. "Large scale parallel state space search utilizing graphics processing units and solid state disks / Damian Sulewski. Betreuer: Stefan Edelkamp. Gutachter: Bernhard Steffen." Dortmund : Universitätsbibliothek Dortmund, 2012. http://d-nb.info/1098312694/34.
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Rödiger, Wolf-Steffen [Verfasser], Alfons [Akademischer Betreuer] [Gutachter] Kemper, Thomas [Gutachter] Neumann, and Gustavo [Gutachter] Alonso. "Scalable Distributed Query Processing in Parallel Main-Memory Database Systems / Wolf-Steffen Rödiger. Betreuer: Alfons Kemper. Gutachter: Thomas Neumann ; Alfons Kemper ; Gustavo Alonso." München : Universitätsbibliothek der TU München, 2016. http://d-nb.info/1104933675/34.
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Sofi, Tommaso Armeo. "General-Purpose Computing on Graphic Processing Unit (GPGPU): metodi e tecnologie per lo sviluppo di applicazioni." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2013. http://amslaurea.unibo.it/5299/.
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Microprocessori basati su singolo processore (CPU), hanno visto una rapida crescita di performances ed un abbattimento dei costi per circa venti anni. Questi microprocessori hanno portato una potenza di calcolo nell’ordine del GFLOPS (Giga Floating Point Operation per Second) sui PC Desktop e centinaia di GFLOPS su clusters di server. Questa ascesa ha portato nuove funzionalità nei programmi, migliori interfacce utente e tanti altri vantaggi. Tuttavia questa crescita ha subito un brusco rallentamento nel 2003 a causa di consumi energetici sempre più elevati e problemi di dissipazione termica, che hanno impedito incrementi di frequenza di clock. I limiti fisici del silicio erano sempre più vicini.
Per ovviare al problema i produttori di CPU (Central Processing Unit) hanno iniziato a progettare microprocessori multicore, scelta che ha avuto un impatto notevole sulla comunità degli sviluppatori, abituati a considerare il software come una serie di comandi sequenziali. Quindi i programmi che avevano sempre giovato di miglioramenti di prestazioni ad ogni nuova generazione di CPU, non hanno avuto incrementi di performance, in quanto essendo eseguiti su un solo core, non beneficiavano dell’intera potenza della CPU. Per sfruttare appieno la potenza delle nuove CPU la programmazione concorrente, precedentemente utilizzata solo su sistemi costosi o supercomputers, è diventata una pratica sempre più utilizzata dagli sviluppatori. Allo stesso tempo, l’industria videoludica ha conquistato una fetta di mercato notevole: solo nel 2013 verranno spesi quasi 100 miliardi di dollari fra hardware e software dedicati al gaming. Le software houses impegnate nello sviluppo di videogames, per rendere i loro titoli più accattivanti, puntano su motori grafici sempre più potenti e spesso scarsamente ottimizzati, rendendoli estremamente esosi in termini di performance. Per questo motivo i produttori di GPU (Graphic Processing Unit), specialmente nell’ultimo decennio, hanno dato vita ad una vera e propria rincorsa alle performances che li ha portati ad ottenere dei prodotti con capacità di calcolo vertiginose. Ma al contrario delle CPU che agli inizi del 2000 intrapresero la strada del multicore per continuare a favorire programmi sequenziali, le GPU sono diventate manycore, ovvero con centinaia e centinaia di piccoli cores che eseguono calcoli in parallelo. Questa immensa capacità di calcolo può essere utilizzata in altri campi applicativi? La risposta è si e l’obiettivo di questa tesi è proprio quello di constatare allo stato attuale, in che modo e con quale efficienza pùo un software generico, avvalersi dell’utilizzo della GPU invece della CPU.
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Mori, Alves da Silva Jones Yudi [Verfasser], Michael [Gutachter] Hübner, and Stephan [Gutachter] Wong. "Development of design framework for parallel data processing hardware architectures / Jones Yudi Mori Alves da Silva ; Gutachter: Michael Hübner, Stephan Wong ; Fakultät für Elektrotechnik und Informationstechnik." Bochum : Ruhr-Universität Bochum, 2018. http://d-nb.info/1154307999/34.
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Brauer, Falk. "Extraktion und Identifikation von Entitäten in Textdaten im Umfeld der Enterprise Search." Phd thesis, Universität Potsdam, 2010. http://opus.kobv.de/ubp/volltexte/2011/5140/.
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Die automatische Informationsextraktion (IE) aus unstrukturierten Texten ermöglicht völlig neue Wege, auf relevante Informationen zuzugreifen und deren Inhalte zu analysieren, die weit über bisherige Verfahren zur Stichwort-basierten Dokumentsuche hinausgehen. Die Entwicklung von Programmen zur Extraktion von maschinenlesbaren Daten aus Texten erfordert jedoch nach wie vor die Entwicklung von domänenspezifischen Extraktionsprogrammen.
Insbesondere im Bereich der Enterprise Search (der Informationssuche im Unternehmensumfeld), in dem eine große Menge von heterogenen Dokumenttypen existiert, ist es oft notwendig ad-hoc Programm-module zur Extraktion von geschäftsrelevanten Entitäten zu entwickeln, die mit generischen Modulen in monolithischen IE-Systemen kombiniert werden. Dieser Umstand ist insbesondere kritisch, da potentiell für jeden einzelnen Anwendungsfall ein von Grund auf neues IE-System entwickelt werden muss.
Die vorliegende Dissertation untersucht die effiziente Entwicklung und Ausführung von IE-Systemen im Kontext der Enterprise Search und effektive Methoden zur Ausnutzung bekannter strukturierter Daten im Unternehmenskontext für die Extraktion und Identifikation von geschäftsrelevanten Entitäten in Doku-menten. Grundlage der Arbeit ist eine neuartige Plattform zur Komposition von IE-Systemen auf Basis der Beschreibung des Datenflusses zwischen generischen und anwendungsspezifischen IE-Modulen. Die Plattform unterstützt insbesondere die Entwicklung und Wiederverwendung von generischen IE-Modulen und zeichnet sich durch eine höhere Flexibilität und Ausdrucksmächtigkeit im Vergleich zu vorherigen Methoden aus.
Ein in der Dissertation entwickeltes Verfahren zur Dokumentverarbeitung interpretiert den Daten-austausch zwischen IE-Modulen als Datenströme und ermöglicht damit eine weitgehende Parallelisierung von einzelnen Modulen. Die autonome Ausführung der Module führt zu einer wesentlichen Beschleu-nigung der Verarbeitung von Einzeldokumenten und verbesserten Antwortzeiten, z. B. für Extraktions-dienste. Bisherige Ansätze untersuchen lediglich die Steigerung des durchschnittlichen Dokumenten-durchsatzes durch verteilte Ausführung von Instanzen eines IE-Systems.
Die Informationsextraktion im Kontext der Enterprise Search unterscheidet sich z. B. von der Extraktion aus dem World Wide Web dadurch, dass in der Regel strukturierte Referenzdaten z. B. in Form von Unternehmensdatenbanken oder Terminologien zur Verfügung stehen, die oft auch die Beziehungen von Entitäten beschreiben. Entitäten im Unternehmensumfeld haben weiterhin bestimmte Charakteristiken: Eine Klasse von relevanten Entitäten folgt bestimmten Bildungsvorschriften, die nicht immer bekannt sind, auf die aber mit Hilfe von bekannten Beispielentitäten geschlossen werden kann, so dass unbekannte Entitäten extrahiert werden können. Die Bezeichner der anderen Klasse von Entitäten haben eher umschreibenden Charakter. Die korrespondierenden Umschreibungen in Texten können variieren, wodurch eine Identifikation derartiger Entitäten oft erschwert wird.
Zur effizienteren Entwicklung von IE-Systemen wird in der Dissertation ein Verfahren untersucht, das alleine anhand von Beispielentitäten effektive Reguläre Ausdrücke zur Extraktion von unbekannten Entitäten erlernt und damit den manuellen Aufwand in derartigen Anwendungsfällen minimiert. Verschiedene Generalisierungs- und Spezialisierungsheuristiken erkennen Muster auf verschiedenen Abstraktionsebenen und schaffen dadurch einen Ausgleich zwischen Genauigkeit und Vollständigkeit bei der Extraktion. Bekannte Regellernverfahren im Bereich der Informationsextraktion unterstützen die beschriebenen Problemstellungen nicht, sondern benötigen einen (annotierten) Dokumentenkorpus.
Eine Methode zur Identifikation von Entitäten, die durch Graph-strukturierte Referenzdaten vordefiniert sind, wird als dritter Schwerpunkt untersucht. Es werden Verfahren konzipiert, welche über einen exakten Zeichenkettenvergleich zwischen Text und Referenzdatensatz hinausgehen und Teilübereinstimmungen und Beziehungen zwischen Entitäten zur Identifikation und Disambiguierung heranziehen. Das in der Arbeit vorgestellte Verfahren ist bisherigen Ansätzen hinsichtlich der Genauigkeit und Vollständigkeit bei der Identifikation überlegen.<br>The automatic information extraction (IE) from unstructured texts enables new ways to access relevant information and analyze text contents, which goes beyond existing technologies for keyword-based search in document collections. However, the development of systems for extracting machine-readable data from text still requires the implementation of domain-specific extraction programs.
In particular in the field of enterprise search (the retrieval of information in the enterprise settings), in which a large amount of heterogeneous document types exists, it is often necessary to develop ad-hoc program-modules and to combine them with generic program components to extract by business relevant entities. This is particularly critical, as potentially for each individual application a new IE system must be developed from scratch.
In this work we examine efficient methods to develop and execute IE systems in the context of enterprise search and effective algorithms to exploit pre-existing structured data in the business context for the extraction and identification of business entities in documents. The basis of this work is a novel platform for composition of IE systems through the description of the data flow between generic and application-specific IE modules. The platform supports in particular the development and reuse of generic IE modules and is characterized by a higher flexibility as compared to previous methods.
A technique developed in this work interprets the document processing as data stream between IE modules and thus enables an extensive parallelization of individual modules. The autonomous execution of each module allows for a significant runtime improvement for individual documents and thus improves response times, e.g. for extraction services. Previous parallelization approaches focused only on an improved throughput for large document collections, e.g., by leveraging distributed instances of an IE system.
Information extraction in the context of enterprise search differs for instance from the extraction from the World Wide Web by the fact that usually a variety of structured reference data (corporate databases or terminologies) is available, which often describes the relationships among entities. Furthermore, entity names in a business environment usually follow special characteristics: On the one hand relevant entities such as product identifiers follow certain patterns that are not always known beforehand, but can be inferred using known sample entities, so that unknown entities can be extracted. On the other hand many designators have a more descriptive character (concatenation of descriptive words). The respective references in texts might differ due to the diversity of potential descriptions, often making the identification of such entities difficult.
To address IE applications in the presence of available structured data, we study in this work the inference of effective regular expressions from given sample entities. Various generalization and specialization heuristics are used to identify patterns at different syntactic abstraction levels and thus generate regular expressions which promise both high recall and precision. Compared to previous rule learning techniques in the field of information extraction, our technique does not require any annotated document corpus.
A method for the identification of entities that are predefined by graph structured reference data is examined as a third contribution. An algorithm is presented which goes beyond an exact string comparison between text and reference data set. It allows for an effective identification and disambiguation of potentially discovered entities by exploitation of approximate matching strategies. The method leverages further relationships among entities for identification and disambiguation. The method presented in this work is superior to previous approaches with regard to precision and recall.
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Lodaya, Bhaveen. "On-Board Memory Extension on Reconfigurable Integrated Circuits using External DDR3 Memory." Master's thesis, Universitätsbibliothek Chemnitz, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-233196.
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User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization.
One drawback of FPGA-based data exploitation is the limited memory capacity of reconfigurable integrated circuits. Large-scale Digital Signal Processor (DSP) FPGAs provide approximately 4MB on-board random access memory (RAM) which is not sufficient to buffer the broadband sensor and result data. Hence, additional external memory is connected to the FPGA to increase on-board storage capacities.
External memory devices like double data rate three synchronous dynamic random access memories (DDR3-SDRAM) provide very fast and wide bandwidth interfaces that represent a bottleneck when used in highly parallelized processing architectures. Independent processing modules are demanding concurrent read and write access.
Within the master thesis, a concept for the integration of an external DDR3- SDRAM into an FPGA-based parallelized processing architecture is developed and implemented. The solution realizes time division multiple access (TDMA) to the external memory and virtual, low-latency memory extension to the on-board buffer capabilities. The integration of the external RAM does not change the way how on-board buffers are used (control, data-fow).
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Lagarde, Matthieu, Philippe Gaussier, and Pierre Andry. "Apprentissage de nouveaux comportements: vers le développement épigénétique d'un robot autonome." Phd thesis, Université de Cergy Pontoise, 2010. http://tel.archives-ouvertes.fr/tel-00749761.
Full textAbstract:
La problématique de l'apprentissage de comportements sur un robot autonome soulève de nombreuses questions liées au contrôle moteur, à l'encodage du comportement, aux stratégies comportementales et à la sélection de l'action. Utiliser une approche développementale présente un intérêt tout particulier dans le cadre de la robotique autonome. Le comportement du robot repose sur des mécanismes de bas niveau dont les interactions permettent de faire émerger des comportements plus complexes. Le robot ne possède pas d'informations a priori sur ses caractéristiques physiques ou sur l'environnement, il doit apprendre sa propre dynamique sensori-motrice. J'ai débuté ma thèse par l'étude d'un modèle d'imitation bas niveau. Du point de vue du développement, l'imitation est présente dès la naissance et accompagne, sous de multiples formes, le développement du jeune enfant. Elle présente une fonction d'apprentissage et se révèle alors être un atout en terme de temps d'acquisition de comportements, ainsi qu'une fonction de communication participant à l'amorce et au maintien d'interactions non verbales et naturelles. De plus, même s'il n'y a pas de réelle intention d'imiter, l'observation d'un autre agent permet d'extraire suffisamment d'informations pour être capable de reproduire la tâche. Mon travail a donc dans un premier temps consisté à appliquer et tester un modèle développemental qui permet l'émergence de comportements d'imitation de bas niveau sur un robot autonome. Ce modèle est construit comme un homéostat qui tend à équilibrer par l'action ses informations perceptives frustres (détection du mouvement, détection de couleur, informations sur les angles des articulations d'un bras de robot). Ainsi, lorsqu'un humain bouge sa main dans le champ visuel du robot, l'ambigüité de la perception de ce dernier lui fait confondre la main de l'humain avec l'extrémité de son bras. De l'erreur qui en résulte émerge un comportement d'imitation immédiate des gestes de l'humain par action de l'homéostat. Bien sûr, un tel modèle implique que le robot soit capable d'associer au préalable les positions visuelles de son effecteur avec les informations proprioceptives de ses moteurs. Grace au comportement d'imitation, le robot réalise des mouvements qu'il peut ensuite apprendre pour construire des comportements plus complexes. Comment alors passer d'un simple mouvement à un geste plus complexe pouvant impliquer un objet ou un lieu ? Je propose une architecture qui permet à un robot d'apprendre un comportement sous forme de séquences temporelles complexes (avec répétition d'éléments) de mouvements. Deux modèles différents permettant l'apprentissage de séquences ont été développés et testés. Le premier apprend en ligne le timing de séquences temporelles simples. Ce modèle ne permettant pas d'apprendre des séquences complexes, le second modèle testé repose sur les propriétés d'un réservoir de dynamiques, il apprend en ligne des séquences complexes. A l'issue de ces travaux, une architecture apprenant le timing d'une séquence complexe a été proposée. Les tests en simulation et sur robot ont montré la nécessité d'ajouter un mécanisme de resynchronisation permettant de retrouver les bons états cachés pour permettre d'amorcer une séquence complexe par un état intermédiaire. Dans un troisième temps, mes travaux ont consisté à étudier comment deux stratégies sensorimotrices peuvent cohabiter dans le cadre d'une tâche de navigation. La première stratégie encode le comportement à partir d'informations spatiales alors que la seconde utilise des informations temporelles. Les deux architectures ont été testées indépendamment sur une même tâche. Ces deux stratégies ont ensuite été fusionnées et exécutées en parallèle. La fusion des réponses délivrées par les deux stratégies a été réalisée avec l'utilisation de champs de neurones dynamiques. Un mécanisme de "chunking" représentant l'état instantané du robot (le lieu courant avec l'action courante) permet de resynchroniser les dynamiques des séquences temporelles. En parallèle, un certain nombre de problème de programmation et de conception des réseaux de neurones sont apparus. En effet, nos réseaux peuvent compter plusieurs centaines de milliers de neurones. Il devient alors difficile de les exécuter sur une seule unité de calcul. Comment concevoir des architectures neuronales avec des contraintes de répartition de calcul, de communications réseau et de temps réel ? Une autre partie de mon travail a consisté à apporter des outils permettant la modélisation, la communication et l'exécution en temps réel d'architecture distribuées. Pour finir, dans le cadre du projet européen Feelix Growing, j'ai également participé à l'intégration de mes travaux avec ceux du laboratoire LASA de l'EPFL pour l'apprentissage de comportements complexes mêlant la navigation, le geste et l'objet. En conclusion, cette thèse m'a permis de développer à la fois de nouveaux modèles pour l'apprentissage de comportements - dans le temps et dans l'espace, de nouveaux outils pour maîtriser des réseaux de neurones de très grande taille et de discuter à travers les limitations du système actuel, les éléments importants pour un système de sélection de l'action.
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Oliveira, João Guilherme Rodrigues Marques de. "Workflow engine for parallel batch processing." Master's thesis, 2017. https://repositorio-aberto.up.pt/handle/10216/102704.
Full textAbstract:
In the context of a software platform that performs complex workflows to analyse large SAF-T files (Standard Audit File for Tax Purposes), the need to impose complex restrictions to the sequencing and concurrency of each task arises.The purpose of this work is to identify relevant restrictions that may need to be imposed on workflows, as well as distributing and monitoring their execution among any number of "slave'' machines, that perform the actual computational work of each task of the workflow.The final solution should improve both flexibility in workflow orchestration as well as performance improvements when running multiple workflows simultaneously.Besides analysing the existing system and eliciting its requirements, a survey of existing solutions and technologies is made in order to architect the final solution.Although this work aims to improve the existing system from which it arose, it should be developed in an agnostic manner, so as to be integrated with any system that requires the handling of complex computational workflows.
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Oliveira, João Guilherme Rodrigues Marques de. "Workflow engine for parallel batch processing." Dissertação, 2017. https://repositorio-aberto.up.pt/handle/10216/102704.
Full textAbstract:
In the context of a software platform that performs complex workflows to analyse large SAF-T files (Standard Audit File for Tax Purposes), the need to impose complex restrictions to the sequencing and concurrency of each task arises.The purpose of this work is to identify relevant restrictions that may need to be imposed on workflows, as well as distributing and monitoring their execution among any number of "slave'' machines, that perform the actual computational work of each task of the workflow.The final solution should improve both flexibility in workflow orchestration as well as performance improvements when running multiple workflows simultaneously.Besides analysing the existing system and eliciting its requirements, a survey of existing solutions and technologies is made in order to architect the final solution.Although this work aims to improve the existing system from which it arose, it should be developed in an agnostic manner, so as to be integrated with any system that requires the handling of complex computational workflows.
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Evans, Greg 1948. "Concurrent processing of visual and auditory information : an assessment of parallel versus sequential processing models / Greg Evans." 1994. http://hdl.handle.net/2440/18529.
Full textAbstract:
Bibliography : leaves 226-237.<br>xii, 237 leaves : ill. ; 30 cm.<br>Title page, contents and abstract only. The complete thesis in print form is available from the University Library.<br>Thesis (Ph.D.)--University of Adelaide, Dept. of Psychology, 1995
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Liu, Kevin H. "Skew characteristics and their effects on parallel relational query processing." Thesis, 1997. https://vuir.vu.edu.au/30101/.
Full textAbstract:
As queries grow increasingly complex and large data sets are becoming prevalent, Parallel Query Processing,
database sizes grow dramatically particularly in Decision Support Systems (DSS) , and OnLine
Analytic Processing Systems ( OIAP) which have recently emerged as important
database applications. In these systems, performance is a critical issue and speeding up the
system has always been an objective but the processing power of individual processors
can only handle a small fraction of current applications. As a result, parallel processing is
exploited to improve database systems performance. In the thesis we focus on relational
database systems and study skew characteristics and their effects on parallel query
processing.
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Britton, Matthew Scott. "Stochastic task scheduling in time-critical information delivery systems / Matthew Britton." Thesis, 2003. http://hdl.handle.net/2440/21899.
Full textAbstract:
"January 2003"<br>Includes bibliographical references (leaves 120-129)<br>x, 129 leaves : ill. ; 30 cm.<br>Presents performance analyses of dynamic, stochastic task scheduling policies for a real- time-communications system where tasks lose value as they are delayed in the system.<br>Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 2003