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Journal articles on the topic 'Parallel prefix'

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Published: 4 June 2021
Last updated: 18 February 2022

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1

Sergeev, I. S. "Minimal parallel prefix circuits." Moscow University Mathematics Bulletin 66, no. 5 (October 2011): 215–18. http://dx.doi.org/10.3103/s002713221105007x.

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2

Manohar, R., and J. A. Tierno. "Asynchronous parallel prefix computation." IEEE Transactions on Computers 47, no. 11 (1998): 1244–52. http://dx.doi.org/10.1109/12.736437.

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3

SAXENA, SANJEEV, P. C. P. BHATT, and V. C. PRASAD. "ON PARALLEL PREFIX COMPUTATION." Parallel Processing Letters 04, no. 04 (December 1994): 429–36. http://dx.doi.org/10.1142/s0129626494000399.

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We prove that prefix sums of n integers of at most b bits can be found on a COMMON CRCW PRAM in [Formula: see text] time with a linear time-processor product. The algorithm is optimally fast, for any polynomial number of processors. In particular, if [Formula: see text] the time taken is [Formula: see text]. This is a generalisation of previous result. The previous [Formula: see text] time algorithm was valid only for O(log n)-bit numbers. Application of this algorithm to r-way parallel merge sort algorithm is also considered. We also consider a more realistic PRAM variant, in which the word size, m, may be smaller than b (m≥log n). On this model, prefix sums can be found in [Formula: see text] optimal time.
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4

Reif, J. H. "Probabilistic parallel prefix computation." Computers & Mathematics with Applications 26, no. 1 (July 1993): 101–10. http://dx.doi.org/10.1016/0898-1221(93)90089-e.

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5

Kowsalya, P., M. Malathi, and Palaniappan Ramanathan. "Low Power Parallel Prefix Adder." Applied Mechanics and Materials 573 (June 2014): 194–200. http://dx.doi.org/10.4028/www.scientific.net/amm.573.194.

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Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of power delay product (PDP). The design is implemented and simulated by DSCH2 and MICROWIND tool .The simulation result reveal about 31%,40% and 50 % of power saving is attained and the number of transistors also reduced.
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6

Akshitha, Sanduri, Mrs P. Navitha, and Mrs D. Mamatha. "Fast Modular Multiplication using Parallel Prefix Adder." International Journal of Trend in Scientific Research and Development Volume-2, Issue-5 (August 31, 2018): 1770–74. http://dx.doi.org/10.31142/ijtsrd18170.

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7

Lu, Tan-Chun, Yu-Song Hou, and Rong-Jaye Chen. "A parallel Poisson generator using parallel prefix." Computers & Mathematics with Applications 31, no. 3 (February 1996): 33–42. http://dx.doi.org/10.1016/0898-1221(95)00204-9.

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8

Kruskal, Clyde P., Larry Rudolph, and Marc Snir. "The power of parallel prefix." IEEE Transactions on Computers C-34, no. 10 (October 1985): 965–68. http://dx.doi.org/10.1109/tc.1985.6312202.

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9

Carlson, David A., and Binay Sugla. "Limited width parallel prefix circuits." Journal of Supercomputing 4, no. 2 (June 1990): 107–29. http://dx.doi.org/10.1007/bf00127876.

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10

Breslauer, Dany. "Fast parallel string prefix-matching." Theoretical Computer Science 137, no. 2 (January 1995): 269–78. http://dx.doi.org/10.1016/0304-3975(94)00177-k.

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11

Chen, Rong-Jaye, and Yu-Song Hou. "Non-associative parallel prefix computation." Information Processing Letters 44, no. 2 (November 1992): 91–94. http://dx.doi.org/10.1016/0020-0190(92)90191-w.

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12

VANICHAYOBON, S., S. K. DHALL, S. LAKSHMIVARAHAN, and J. K. ANTONIO. "POWER-SPEED TRADE-OFF IN PARALLEL PREFIX CIRCUITS." Journal of Circuits, Systems and Computers 14, no. 01 (February 2005): 65–98. http://dx.doi.org/10.1142/s0218126605002179.

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Optimizing area and speed in parallel prefix circuits has been considered important for a long time. The issue of power consumption in these circuits, however, has not been addressed. This paper presents a comparative study of different parallel prefix circuits from the point of view of power–speed trade-off. An effective circuit capacitance model that is verified through PSpice simulations is used to investigate the power consumption in parallel prefix circuits. The model results in an analytical function for power consumption for each prefix circuit considered. The degrees of freedom studied include different parallel prefix circuits and voltage scaling. The results of the study were applied to evaluate power–speed trade-offs when different prefix circuits are used in Brent's parallel adder.5
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13

K, Nehru K., Nagarjuna T, and Somanaidu U. "Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 2 (July 1, 2018): 115. http://dx.doi.org/10.11591/ijres.v7.i2.pp115-123.

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<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>
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14

EĞECIOĞLU, ÖMER, and ASHOK SRINIVASAN. "OPTIMAL PARALLEL PREFIX ON MESH ARCHITECTURES." Parallel Algorithms and Applications 1, no. 3 (January 1993): 191–209. http://dx.doi.org/10.1080/10637199308915441.

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15

Poornima, N., and V. S. Kanchana Bhaaskaran. "Area Efficient Hybrid Parallel Prefix Adders." Procedia Materials Science 10 (2015): 371–80. http://dx.doi.org/10.1016/j.mspro.2015.06.069.

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16

Mansharamani, R. K. "Parallel Computing Using the Prefix Problem." Computer Journal 38, no. 3 (January 1, 1995): 264–65. http://dx.doi.org/10.1093/comjnl/38.3.264-a.

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17

Eǧecioǧlu, Ömer, and Çetin Kaya Koç. "Parallel prefix computation with few processors." Computers & Mathematics with Applications 24, no. 4 (August 1992): 77–84. http://dx.doi.org/10.1016/0898-1221(92)90009-7.

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18

El-Boghdadi, Hatem M. "Dynamic-width reconfigurable parallel prefix circuits." Journal of Supercomputing 71, no. 4 (January 1, 2015): 1177–95. http://dx.doi.org/10.1007/s11227-014-1270-2.

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19

JANA, PRASANTA K., and BHABANI P. SINHA. "AN IMPROVED PARALLEL PREFIX ALGORITHM ON OTIS-MESH." Parallel Processing Letters 16, no. 04 (December 2006): 429–40. http://dx.doi.org/10.1142/s0129626406002757.

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Wang and Sahni [4] reported two parallel algorithms for N-point prefix computation on an N-processor OTIS-Mesh optoelectronic computer. The overall time complexity for both SIMS and MIMD models of their first algorithm was shown to be (8 N1/4 - 1) electronic moves and 2 OTIS moves. This was further reduced to (7 N1/4 - 1) electronic moves and 2 OTIS moves in their second algorithm. We present here an improved parallel algorithm for N-point prefix computation on an N-processor OTIS-Mesh, which needs (5.5 N1/4 + 3) electronic moves and 2 OTIS moves. Our algorithm is based on the general theme of parallel prefix algorithm proposed in [4] but following the data distribution and local prefix computation similar to that of [1].
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20

SHEERAN, MARY. "Functional and dynamic programming in the design of parallel prefix networks." Journal of Functional Programming 21, no. 1 (December 6, 2010): 59–114. http://dx.doi.org/10.1017/s0956796810000304.

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AbstractA parallel prefix network of width n takes n inputs, a1, a2, . . ., an, and computes each yi = a1 ○ a2 ○ ⋅ ⋅ ⋅ ○ ai for 1 ≤ i ≤ n, for an associative operator ○. This is one of the fundamental problems in computer science, because it gives insight into how parallel computation can be used to solve an apparently sequential problem. As parallel programming becomes the dominant programming paradigm, parallel prefix or scan is proving to be a very important building block of parallel algorithms and applications. There are many different parallel prefix networks, with different properties such as number of operators, depth and allowed fanout from the operators. In this paper, ideas from functional programming are combined with search to enable a deep exploration of parallel prefix network design. Networks that improve on the best known previous results are generated. It is argued that precise modelling in a functional programming language, together with simple visualization of the networks, gives a new, more experimental, approach to parallel prefix network design, improving on the manual techniques typically employed in the literature. The programming idiom that marries search with higher order functions may well have wider application than the network generation described here.
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21

Lakshmipriya, S. "A Review on Implementation of Parallel Prefix Adders using FPGA’S." International Journal of Trend in Scientific Research and Development Volume-2, Issue-1 (December 31, 2017): 1304–6. http://dx.doi.org/10.31142/ijtsrd7165.

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22

Cury, Ch, and M. Nisanth. "Design of Parallel Prefix Adders using FPGAs." IOSR journal of VLSI and Signal Processing 4, no. 3 (2014): 45–51. http://dx.doi.org/10.9790/4200-04334551.

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23

Aluru, Srinivas, Natsuhiko Futamura, and Kishan Mehrotra. "Parallel biological sequence comparison using prefix computations." Journal of Parallel and Distributed Computing 63, no. 3 (March 2003): 264–72. http://dx.doi.org/10.1016/s0743-7315(03)00010-8.

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24

Dimitrakopoulos, G., and D. Nikolos. "High-speed parallel-prefix VLSI Ling adders." IEEE Transactions on Computers 54, no. 2 (February 2005): 225–31. http://dx.doi.org/10.1109/tc.2005.26.

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25

Mathias, Roy. "The Instability of Parallel Prefix Matrix Multiplication." SIAM Journal on Scientific Computing 16, no. 4 (July 1995): 956–73. http://dx.doi.org/10.1137/0916056.

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26

Lin, Yen-Chun, and Li-Ling Hung. "Fast problem-size-independent parallel prefix circuits." Journal of Parallel and Distributed Computing 69, no. 4 (April 2009): 382–88. http://dx.doi.org/10.1016/j.jpdc.2008.12.003.

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27

Kedem, Zvi M., Gad M. Landau, and Krishna V. Palem. "Parallel Suffix–Prefix-Matching Algorithm and Applications." SIAM Journal on Computing 25, no. 5 (October 1996): 998–1023. http://dx.doi.org/10.1137/s0097539792190157.

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28

Yang, Yajue, Yuanqing Wu, and Jia Pan. "Parallel Dynamics Computation Using Prefix Sum Operations." IEEE Robotics and Automation Letters 2, no. 3 (July 2017): 1296–303. http://dx.doi.org/10.1109/lra.2017.2666544.

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29

P.Chaitanya kumari, P. Chaitanya kumari. "Design of 32 bit Parallel Prefix Adders." IOSR Journal of Electronics and Communication Engineering 6, no. 1 (2013): 1–6. http://dx.doi.org/10.9790/2834-610106.

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30

Hagerup, Torben. "The parallel complexity of integer prefix summation." Information Processing Letters 56, no. 1 (October 1995): 59–64. http://dx.doi.org/10.1016/0020-0190(95)00119-w.

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31

Park, Jin Hwan, and H. K. Dai. "Reconfigurable hardware solution to parallel prefix computation." Journal of Supercomputing 43, no. 1 (May 8, 2007): 43–58. http://dx.doi.org/10.1007/s11227-007-0137-1.

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32

Cinque, L., and G. Bongiovanni. "Parallel prefix computation on a pyramid computer." Pattern Recognition Letters 16, no. 1 (January 1995): 19–22. http://dx.doi.org/10.1016/0167-8655(94)00067-d.

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33

Han, Yijie. "Parallel algorithms for computing linked list prefix." Journal of Parallel and Distributed Computing 6, no. 3 (June 1989): 537–57. http://dx.doi.org/10.1016/0743-7315(89)90005-1.

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34

KalaiKaviya, K., D. P. Balasubramanian, and S. Tamilselvan. "Design Of A Optimized Parallel Array Multiplier Using Parallel Prefix Adder." International Journal of Engineering and Manufacturing 3, no. 2 (September 16, 2013): 40–50. http://dx.doi.org/10.5815/ijem.2013.02.03.

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35

ŠUPOL, JAN, and BOŘIVOJ MELICHAR. "ARITHMETIC CODING IN PARALLEL." International Journal of Foundations of Computer Science 16, no. 06 (December 2005): 1207–17. http://dx.doi.org/10.1142/s0129054105003765.

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We present an EREW PRAM cost optimal parallel algorithm for arithmetic coding computation. We solve the problem in [Formula: see text] time using n/log n processors. Each part of the algorithm as well as a well-known parallel prefix computation forming a basis of the algorithm are clarified on simple examples.
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36

Abu Al-Haija, Qasem, Mohamad Musab Asad, Ibrahim Marouf, Ahmad Bakhuraibah, and Hesham Enshasy. "FPGA SYNTHESIS AND VALIDATION OF PARALLEL PREFIX ADDERS." Acta Electronica Malaysia 3, no. 2 (March 5, 2019): 31–36. http://dx.doi.org/10.26480/aem.02.2019.31.36.

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37

Cole, Richard, and Uzi Vishkin. "Faster optimal parallel prefix sums and list ranking." Information and Computation 81, no. 3 (June 1989): 334–52. http://dx.doi.org/10.1016/0890-5401(89)90036-9.

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38

Jana, Prasanta K., B. Damodara Naidu, Shailendra Kumar, Monish Arora, and Bhabani P. Sinha. "Parallel prefix computation on extended multi-mesh network." Information Processing Letters 84, no. 6 (December 2002): 295–303. http://dx.doi.org/10.1016/s0020-0190(02)00317-4.

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39

Lin, Yen-Chun, and Chin-Yu Su. "Faster optimal parallel prefix circuits: New algorithmic construction." Journal of Parallel and Distributed Computing 65, no. 12 (December 2005): 1585–95. http://dx.doi.org/10.1016/j.jpdc.2005.05.017.

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40

Divya, D., M. Bharathi, and C. Ruth Vinutha. "Parallel Prefix Adder Using Static Conventional Logic Gates." i-manager's Journal on Circuits and Systems 3, no. 4 (November 15, 2015): 42–47. http://dx.doi.org/10.26634/jcir.3.4.5930.

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41

Bund, Johannes, Christoph Lenzen, and Moti Medina. "Optimal Metastability-Containing Sorting via Parallel Prefix Computation." IEEE Transactions on Computers 69, no. 2 (February 1, 2020): 198–211. http://dx.doi.org/10.1109/tc.2019.2939818.

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42

Snir, Marc. "Depth-size trade-offs for parallel prefix computation." Journal of Algorithms 7, no. 2 (June 1986): 185–201. http://dx.doi.org/10.1016/0196-6774(86)90003-9.

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43

Datta, Amit, Mallika De, and Bhabani P. Sinha. "Fast Parallel Algorithm for Prefix Computation in Multi-Mesh Architecture." Parallel Processing Letters 27, no. 03n04 (December 2017): 1750009. http://dx.doi.org/10.1142/s0129626417500098.

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A parallel algorithm for prefix computation on [Formula: see text] data elements mapped on a Multi Mesh (MM) network of [Formula: see text] processing elements is presented here. The time required by the proposed algorithm is significantly less than that by any of the existing algorithms for prefix computation on mesh-like architectures due to the specific interconnection pattern used in the MM network. The proposed technique requires [Formula: see text] time for data communication and [Formula: see text] time for computation, when mapped on a MM network constituted by [Formula: see text] meshes, each of size [Formula: see text]. The data communication time in the proposed algorithm is less than the prefix sum algorithm proposed in extended Multi Mesh. To be precise, instead of [Formula: see text] communication time the proposed algorithm requires a data communication time of [Formula: see text] only. Moreover, the proposed parallel algorithm does not need any extra inter block links as used in the extended Multi Mesh.
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44

Gurusamy, L., Muhammad Kashif, and Norhuzaimin Julai. "Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library." Applied Mechanics and Materials 833 (April 2016): 149–56. http://dx.doi.org/10.4028/www.scientific.net/amm.833.149.

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This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction in comparison of the traditional Carry Look-Ahead Adder (CLA).
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45

Matsunaga, Taeko, Shinji Kimura, and Yusuke Matsunaga. "Framework for Parallel Prefix Adder Synthesis Considering Switching Activities." IPSJ Transactions on System LSI Design Methodology 2 (2009): 212–21. http://dx.doi.org/10.2197/ipsjtsldm.2.212.

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46

Jha, Sudhanshu Kumar. "An Improved Parallel Prefix Computation on 2D-Mesh Network." Procedia Technology 10 (2013): 919–26. http://dx.doi.org/10.1016/j.protcy.2013.12.438.

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47

Abdel-Hafeez, Saleh, Ann Gordon-Ross, and Behrooz Parhami. "Scalable Digital CMOS Comparator Using a Parallel Prefix Tree." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 11 (November 2013): 1989–98. http://dx.doi.org/10.1109/tvlsi.2012.2222453.

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48

Efstathiou, C., H. T. Vergos, and D. Nikolos. "Fast parallel-prefix modulo 2/sup n/+1 adders." IEEE Transactions on Computers 53, no. 9 (September 2004): 1211–16. http://dx.doi.org/10.1109/tc.2004.60.

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49

Rong Lin, K. Nakano, S. Olariu, and A. Y. Zomaya. "An efficient parallel prefix sums architecture with domino logic." IEEE Transactions on Parallel and Distributed Systems 14, no. 9 (September 2003): 922–31. http://dx.doi.org/10.1109/tpds.2003.1233714.

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50

shrivastava, Avinash, and Chandrahas sahu. "Performance Analysis of Parallel Prefix Adder Based on FPGA." International Journal of Engineering Trends and Technology 21, no. 6 (March 25, 2015): 281–86. http://dx.doi.org/10.14445/22315381/ijett-v21p251.

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