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Journal articles on the topic 'Parity generator'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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1

A.Anjana. "Even and Odd Parity Generator and Checker using the Reversible logic gates." International Journal of Computer Science and Engineering Communications 1, no. 1 (2013): 62–66. https://doi.org/10.5281/zenodo.821766.

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Digital data transmission is the mostly used in the communication. The data transmission from source to destination should be without loss of information. This is made possible by using the method of parity generator and parity checker. The parity checker and the parity generator are of two types they are even parity generator and parity checker, odd parity generator and checker. Reversible logic gates compremises various parameters in the data transmission. There are various reversible logic gates to meet the needs of the parity generator and parity checker. Reversible gates probably reduce t

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2

B.Y., Galadima G.S.M Galadanci S.M. Gana A. Tijjani M. Ibrahim. "QCA Based Design of Reversible Parity Generator and Parity Checker Circuits for Telecommunication." NIPES Journal of Science and Technology Research 5, no. 2 (2023): 331–43. https://doi.org/10.5281/zenodo.8070398.

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<em>Quantum-dot cellular automation (QCA) is a transistor-free technology used to implement nanoscale circuit designs. When compared to the widely used complementary metal oxide semiconductor (CMOS) technology, QCA circuits are faster, denser, and use less energy. It has some advantages in reversible logic, including its small size and low power dissipation. In this work, a model of a low-power 3-bit odd parity generator and checker circuit based on a reversible Feynman gate with 23 cells and 40 cells, respectively, is proposed. The proposed reversible odd parity generator and checker circuit

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3

Wahab, Musa, Wahyuni Dali Sri, and Irawaty Tolago Ade. "Design of Digital Parity Generator Layout using 0.7 micron Technology." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 5 (2018): 3550–59. https://doi.org/10.11591/ijece.v8i5.pp3550-3559.

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The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results

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Musa, Wahab, Sri Wahyuni Dali, and Ade Irawaty Tolago. "Design of Digital Parity Generator Layout Using 0.7 micron Technology." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 5 (2018): 3550. http://dx.doi.org/10.11591/ijece.v8i5.pp3550-3559.

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The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of

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5

Khakpour, Mahdi, Mohammad Gholami, and Shokoufeh Naghizadeh. "Parity generator and digital code converter in QCA nanotechnology." International Nano Letters 10, no. 1 (2019): 49–59. http://dx.doi.org/10.1007/s40089-019-00292-8.

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AbstractIn this paper, new structures for digital code converter circuits in quantum dot cellular automata (QCA) technology are presented. The basic structure of most of these circuits is the XOR gate, which is widely used in digital design. Therefore, in the proposed, the XOR gate will be presented which will be better than previous circuits in terms of cell number and delay. Then, using the proposed circuits for the XOR gate, new circuits for generating parity bit, Binary to Gray, Gray to binary and BCD to gray code converter are introduced. Proposal designs have an efficient implementation

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Huang, Zenghui, Shen Yin, and Hamid Reza Karimi. "Residual Generator-Based Controller Design via Process Measurements." Mathematical Problems in Engineering 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/290371.

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This paper deals with designing the controller of LTI system based on data-driven techniques. We propose a scheme embedding a residual generator into control loop based on realization of the Youla parameterization for advanced controller design. Basic idea of the proposed scheme is constructing the residual generator by using the solution of the Luenberger equations as well as the well-established relationship between diagnosis observer (DO) and the parity vector. Besides, the core of the above idea is straightly using the process measurements to obtain the parity space based on the Subspace I

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7

HAGHPARAST, MAJID, and KEIVAN NAVI. "NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS." International Journal of Quantum Information 09, no. 02 (2011): 723–38. http://dx.doi.org/10.1142/s0219749911007447.

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Reversible logic is an emerging area of research, having applications in nanotechnology, low power CMOS design, quantum computing, and DNA computing. In this paper, two different parity-preserving reversible error coding and detection circuits are studied. First we propose two new reversible Hamming code generator circuits. One of them is parity-preserve. We also propose a new parity-preserving reversible Hamming code error detector circuit. The proposed parity-preserving reversible Hamming code generator (PPHCG) and error detector circuits provide single error correction–double error detectio

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8

Han, Bingchen, Junyu Xu, Pengfei Chen, et al. "All-Optical Non-Inverted Parity Generator and Checker Based on Semiconductor Optical Amplifiers." Applied Sciences 11, no. 4 (2021): 1499. http://dx.doi.org/10.3390/app11041499.

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An all-optical non-inverted parity generator and checker based on semiconductor optical amplifiers (SOAs) are proposed with four-wave mixing (FWM) and cross-gain modulation (XGM) non-linear effects. A 2-bit parity generator and checker using by exclusive NOR (XNOR) and exclusive OR (XOR) gates are implemented by first SOA and second SOA with 10 Gb/s return-to-zero (RZ) code, respectively. The parity and check bits are provided by adjusting the center wavelength of the tunable optical bandpass filter (TOBPF). A saturable absorber (SA) is used to reduce the negative effect of small signal clock

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9

BINDU, MADDI. "Design and Implementation of High-Speed Universal Asynchronous Receiver and Transmitter (UART)." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–9. https://doi.org/10.55041/ijsrem40371.

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The Universal Asynchronous Receiver and Transmitter (UART) are described, which is essentially a serial data transfer protocol used in digital circuit applications. The UART transmitter architecture has a baud rate generator, a parity generator, a transmitter finite state machine (FSM), and a parallel in serial out (PISO) register. The UART receiver is composed of a baud rate generator, a negative edge detector, a parity checker, a receiver Finite State Machine (FSM), and a serial in parallel out (SIPO) register. The transmitter and the receiver have the same baud rate generator; therefore, th

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10

A. Zain, Adnan. "On Group Codes Over Elementary Abelian Groups." Sultan Qaboos University Journal for Science [SQUJS] 8, no. 2 (2003): 145. http://dx.doi.org/10.24200/squjs.vol8iss2pp145-151.

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For group codes over elementary Abelian groups we present definitions of the generator and the parity check matrices, which are matrices over the ring of endomorphism of the group. We also lift the theorem that relates the parity check and the generator matrices of linear codes over finite fields to group codes over elementary Abelian groups. Some new codes that are MDS, self-dual, and cyclic over the Abelian group with four elements are given.

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11

Das, Jadav Chandra, and Debashis De. "Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication." Frontiers of Information Technology & Electronic Engineering 17, no. 3 (2016): 224–36. http://dx.doi.org/10.1631/fitee.1500079.

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12

Sen, S., F. Capasso, A. Y. Cho, and D. L. Sivco. "Parity generator circuit using a multistate resonant tunnelling bipolar transistor." Electronics Letters 24, no. 24 (1988): 1506. http://dx.doi.org/10.1049/el:19881028.

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13

Gassoumi, Ismail, Lamjed Touil, Bouraoui Ouni, and Abdellatif Mtibaa. "An Ultra-Low Power Parity Generator Circuit Based on QCA Technology." Journal of Electrical and Computer Engineering 2019 (October 7, 2019): 1–8. http://dx.doi.org/10.1155/2019/1675169.

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Quantum-dot cellular automata (QCA) technology is one of the emerging technologies that can be used for replacing CMOS technology. It has attracted significant attention in the recent years due to its extremely low power dissipation, high operating frequency, and a small size. In this study, we demonstrate an n-bit parity generator circuit by utilizing QCA technology. Here, a novel XOR gate is used in the synthesis of the proposed circuit. The proposed gate is based on electrostatic interactions between cells to perform the desired function. The comparison results demonstrate that the designed

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14

You, Y. W., and J. C. Jeon. "Design of QCA 4-Bit Even Parity Generator Using Multilayer Structure." Advanced Science Letters 23, no. 10 (2017): 10107–11. http://dx.doi.org/10.1166/asl.2017.10398.

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15

Matsui, Hajime. "On generator matrices and parity check matrices of generalized integer codes." Designs, Codes and Cryptography 74, no. 3 (2013): 681–701. http://dx.doi.org/10.1007/s10623-013-9883-7.

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16

Bahar, Ali Newaz, Muhammad Shahin Uddin, Md Abdullah-Al-Shafi, Mohammad Maksudur Rahman Bhuiyan, and Kawsar Ahmed. "Designing efficient QCA even parity generator circuits with power dissipation analysis." Alexandria Engineering Journal 57, no. 4 (2018): 2475–84. http://dx.doi.org/10.1016/j.aej.2017.02.002.

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17

Ghosh, Amal K. "Parity generator and parity checker in the modified trinary number system using savart plate and spatial light modulator." Optoelectronics Letters 6, no. 5 (2010): 325–27. http://dx.doi.org/10.1007/s11801-010-0060-1.

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18

Fan, Daoqing, Yongchao Fan, Erkang Wang, and Shaojun Dong. "A simple, label-free, electrochemical DNA parity generator/checker for error detection during data transmission based on “aptamer-nanoclaw”-modulated protein steric hindrance." Chemical Science 9, no. 34 (2018): 6981–87. http://dx.doi.org/10.1039/c8sc02482k.

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19

Vittapu, Sravan K., Ravichand Sankuru, Ravi Bolimera, Kuruva Madhu Ramudu, Mekala Rameshwar Reddy, and Maddula Manasa Reddy. "Reversible logic-based parity generator circuit for nano communication network using QCA." Characterization and Application of Nanomaterials 7, no. 2 (2024): 6236. http://dx.doi.org/10.24294/can.v7i2.6236.

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An alternative to CMOS VLSI called Quantum Cellular Automata (QCA) is presently being researched. Although a few basic logical circuits and devices have been examined, very little, if any, research has been done on the architecture of QCA device systems. In the context of nano communication networks, data transmission that is both dependable and efficient is still critical. The technology known as Quantum Dot Cellular Automata (QCA) has shown great promise in the development of nano-scale circuits because of its extremely low power consumption and rapid functioning. This study introduces a uni

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20

A., Raja, Mukherjee K., and N. Roy J. "Design of all-optical parity bit generator and checker using semiconductor material based devices." Journal of Indian Chemical Society Vol. 97, No. 12c, Dec 2020 (2020): 2919–28. https://doi.org/10.5281/zenodo.5654709.

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Department of Physics, Kazi Nazrul University, Asansol-713 340, West Bengal, India Department of Physics, B. B. College, Asansol-713 303, West Bengal, India Centre for Organic Spintronics and Optoelectronics Devices (COSOD), Kazi Nazrul University, Asansol-713 340, West Bengal, India <em>E-mail:</em> klmukherjee003@gmail.com <em>Manuscript received online 02 December 2020, accepted 22 December 2020</em> In this communication, we are trying to design a new all-optical parity bit generator and parity checker operating in ultra high speed using four-wave mixing (FWM) and cross-polarization modula

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21

Lakhani, A. A., R. C. Potter, and H. S. Hier. "Eleven-bit parity generator with a single, vertically integrated resonant tunnelling device." Electronics Letters 24, no. 11 (1988): 681–83. http://dx.doi.org/10.1049/el:19880461.

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22

Ghalamdoost Pirbazari, Shahab, Alireza Souri, Reza Faghih Mirzaee, and Sam Jabbehdari. "Multi valued parity generator based on Sudoku tables: properties and detection probability." IET Communications 14, no. 14 (2020): 2377–86. http://dx.doi.org/10.1049/iet-com.2019.0247.

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23

Kalaimani, G., L. M. Merlin Livingston, and C. Senthil Singh. "RETRACTED: Apprehension of parity generator through array of Mach–Zehnder modulation process." Microprocessors and Microsystems 74 (April 2020): 103003. http://dx.doi.org/10.1016/j.micpro.2020.103003.

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24

Matsui, Hajime. "On generator and parity-check polynomial matrices of generalized quasi-cyclic codes." Finite Fields and Their Applications 34 (July 2015): 280–304. http://dx.doi.org/10.1016/j.ffa.2015.02.003.

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25

Lu, Yanbo, Xinji Liu, and Shutao Xia. "On the Single-Parity Locally Repairable Codes with Multiple Repairable Groups." Information 9, no. 11 (2018): 265. http://dx.doi.org/10.3390/info9110265.

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Locally repairable codes (LRCs) are a new family of erasure codes used in distributed storage systems which have attracted a great deal of interest in recent years. For an [ n , k , d ] linear code, if a code symbol can be repaired by t disjoint groups of other code symbols, where each group contains at most r code symbols, it is said to have availability- ( r , t ) . Single-parity LRCs are LRCs with a constraint that each repairable group contains exactly one parity symbol. For an [ n , k , d ] single-parity LRC with availability- ( r , t ) for the information symbols (single-parity LRCs), th

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26

Revathy, M., and R. Saravanan. "A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications." Scientific World Journal 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/327357.

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Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated betwe

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27

Fadlil, Abdul, Imam Riadi, and Achmad Nugrahantoro. "Kombinasi Sinkronisasi Jaringan Syaraf Tiruan dan Vigenere Cipher untuk Optimasi Keamanan Informasi." Digital Zone: Jurnal Teknologi Informasi dan Komunikasi 11, no. 1 (2020): 81–95. http://dx.doi.org/10.31849/digitalzone.v11i1.3945.

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Kriptografi pengubahan pesan asli menjadi disamarkan berguna menjaga kerahasiaan, integritas, keaslian, autentikasi pesan ketika proses komunikasi. Kriptografi klasik dengan subtitusi polialfabetik Vigenere memiliki tabel alphabet 26 baris yang relatif sederhana menjamin kerahasiaan. Kini pendekatan pembelajaran mesin Jaringan Syaraf Tiruan (JST) menjadi solusi layak untuk kriptografi dengan membentuk kunci rahasia dalam bobot jaringan sulit terpecahkan. Kunci dihasilkan dari bidirectional learning, dua pohon paritas saling tersinkronisasi dengan paramater hidden neuron, input neuron dan bobot

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28

Falsafain, Hossein, and Sayyed Rasoul Mousavi. "A Generator-Matrix-Based Approach for Adaptively Generating Cut-Inducing Redundant Parity Checks." IEEE Communications Letters 20, no. 4 (2016): 640–43. http://dx.doi.org/10.1109/lcomm.2016.2530706.

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29

Oenning, T. R., and Jaekyun Moon. "A low-density generator matrix interpretation of parallel concatenated single bit parity codes." IEEE Transactions on Magnetics 37, no. 2 (2001): 737–41. http://dx.doi.org/10.1109/20.917609.

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30

Rakshit, Jayanta Kumar, Jitendra Nath Roy, and Tanay Chattopadhyay. "Design of micro-ring resonator based all-optical parity generator and checker circuit." Optics Communications 303 (August 2013): 30–37. http://dx.doi.org/10.1016/j.optcom.2013.03.025.

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31

Vieira, Luiz G. L., Luiz F. M. Vieira, Marcos A. M. Vieira, and Omar P. Vilela Neto. "Gray‐code adder with parity generator – a novel quantum‐dot cellular automata implementation." IET Circuits, Devices & Systems 14, no. 2 (2020): 243–50. http://dx.doi.org/10.1049/iet-cds.2019.0003.

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32

Fan, Daoqing, Erkang Wang, and Shaojun Dong. "A DNA-based parity generator/checker for error detection through data transmission with visual readout and an output-correction function." Chemical Science 8, no. 3 (2017): 1888–95. http://dx.doi.org/10.1039/c6sc04056j.

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The first DNA-based molecular parity generator/checker, used for error detection through data transmission with fluorescent and visual readouts, has been constructed. The erroneous transmission can be readily distinguished by the naked eye using the G-quadruplex DNAzyme as a signal reporter of the visual outputs.

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33

Bälter, Magnus, Shiming Li, Jesper R. Nilsson, Joakim Andréasson, and Uwe Pischel. "An All-Photonic Molecule-Based Parity Generator/Checker for Error Detection in Data Transmission." Journal of the American Chemical Society 135, no. 28 (2013): 10230–33. http://dx.doi.org/10.1021/ja403828z.

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34

Jiang, Yuchen, Shen Yin, and Okyay Kaynak. "Optimized Design of Parity Relation-Based Residual Generator for Fault Detection: Data-Driven Approaches." IEEE Transactions on Industrial Informatics 17, no. 2 (2021): 1449–58. http://dx.doi.org/10.1109/tii.2020.2987840.

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35

Samanta, Debajyoti, and Sourangshu Mukhopadhyay. "All-optical method of developing parity generator and checker with polarization encoded light signal." Journal of Optics 41, no. 3 (2012): 167–72. http://dx.doi.org/10.1007/s12596-012-0080-2.

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36

Pahari, Nirmalya. "All optical even and odd parity bit generator and checker with optical nonlinear material." Journal of Optics 46, no. 3 (2016): 336–41. http://dx.doi.org/10.1007/s12596-016-0377-7.

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37

Kotb, Amer, Kyriakos E. Zoiros, Chunlei Guo, and Wei Chen. "All-Optical 4-Bit Parity Generator and Checker Utilizing Carrier Reservoir Semiconductor Optical Amplifiers." Electronics 13, no. 12 (2024): 2314. http://dx.doi.org/10.3390/electronics13122314.

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This research explores the forefront of all-optical data processing systems through the utilization of carrier reservoir semiconductor optical amplifiers (CR-SOAs). Recent advancements have showcased the successful design and implementation of CR-SOA-based combinational systems, incorporating pivotal elements like half adders, half subtractors, digital-to-analog converters, latches, header recognition, and header processors. These breakthroughs signify a significant stride towards the realization of faster and more efficient optical logic systems. This study delves into the distinctive charact

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38

Choi, Taeseung. "Proper relativistic position operators in 1+1 and 2+1 dimensions." International Journal of Modern Physics A 35, no. 18 (2020): 2050084. http://dx.doi.org/10.1142/s0217751x20500840.

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We have revisited the Dirac theory in [Formula: see text] and [Formula: see text] dimensions by using the covariant representation of the parity-extended Poincaré group in their native dimensions. The parity operator plays a crucial role in deriving wave equations in both theories. We studied two position operators, a canonical one and a covariant one that becomes the particle position operator projected onto the particle subspace. In [Formula: see text] dimensions the particle position operator, not the canonical position operator, provides the conserved Lorentz generator. The mass moment def

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39

ZBERECKI, K., P. MAGIERSKI, P. H. HEENEN, and N. SCHUNCK. "QUANTUM FLUCTUATIONS AND STABILITY OF TETRAHEDRAL DEFORMATIONS IN ATOMIC NUCLEI." International Journal of Modern Physics E 16, no. 02 (2007): 533–40. http://dx.doi.org/10.1142/s021830130700596x.

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The possible existence of stable axial octupole and tetrahedral deformations is investigated in 80 Zr and 98 Zr . HFBCS calculations with parity projection have been performed for various parametrizations of the Skyrme energy functional. The correlation and excitation energies of negative parity states associated with shape fluctuations have been obtained using the generator coordinate method (GCM). The results indicate that in these nuclei both the axial octupole and tetrahedral deformations are of dynamic character and possess similar characteristics. Various Skyrme forces give consistent re

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40

Chen, Haotian, Hongjun Lv, Zhang Zhang, Xin Cheng, and Guangjun Xie. "Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata." Journal of Circuits, Systems and Computers 28, no. 08 (2019): 1950141. http://dx.doi.org/10.1142/s021812661950141x.

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Recently reported quantum-dot cellular automata (QCA) exclusive-OR gate designs are usually made with the AND–OR–INVERTER method in which it is difficult to optimize the XOR gate. This paper presents a novel low-power exclusive-OR (XOR) gate which is mainly based on cell-level format. Compared with the previous XOR gates, the proposed XOR gate performs in a different manner. This XOR gate design is accomplished by the intercellular effects method. For better performance comparison with previous relevant works, 4-, 8-, 16- and 32-bit parity generators are implemented in this paper. The simulati

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41

Kumar, Santosh, Chanderkanta, and Angela Amphawan. "Design of parity generator and checker circuit using electro-optic effect of Mach–Zehnder interferometers." Optics Communications 364 (April 2016): 195–224. http://dx.doi.org/10.1016/j.optcom.2015.11.054.

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42

Purohit, Gaurav, Kota Solomon Raju, and Vinod Kumar Chaubey. "XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware." International Journal of Reconfigurable Computing 2016 (2016): 1–8. http://dx.doi.org/10.1155/2016/9128683.

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This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW) implementation of new architecture uses Lookup Table (LUT) for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and im

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43

Farkaš, Peter, and Frank Schindler. "Run length limited error control codes construction based on one control matrix property." Journal of Electrical Engineering 68, no. 4 (2017): 322–24. http://dx.doi.org/10.1515/jee-2017-0046.

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AbstractIn this manuscript a simple method is presented for constructing run length limited error control codes from linear binary block codes. The run length limited properties are obtained via addition of a carefully chosen fixed binary vector - a modifier to all codewords without introducing any additional redundancy. Modifier selection is based on a specific property, which can be found in some of the linear binary block codes control matrices. Similar known methods are based on properties of generator matrices. However some codes are specified via control matrices, for example low density

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44

Agrawal, Prateek, S. R. P. Sinha, Neeraj Kumar Misra, and Subodh Wairya. "Design of Quantum Dot Cellular Automata Based Parity Generator and Checker with Minimum Clocks and Latency." International Journal of Modern Education and Computer Science 8, no. 8 (2016): 11–20. http://dx.doi.org/10.5815/ijmecs.2016.08.02.

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45

Bosu, Surajit, and Baibaswata Bhattacharjee. "All-optical frequency encoded dibit-based parity generator using reflective semiconductor optical amplifier with simulative verification." Facta universitatis - series: Electronics and Energetics 35, no. 1 (2022): 29–41. http://dx.doi.org/10.2298/fuee2201029b.

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High-speed signal computation and communication are an essential part of modern communication that increases optical necessity. Therefore, researchers developed different types of digital devices in the all-optical domain. Due to the versatile gain medium of reflective semiconductor optical amplifiers (RSOAs), it has various important applications in passive optical networks. In comparison with semiconductor optical amplifier (SOA), RSOAs exhibit better gain performance because of their double pass property. Therefore, RSOA shows better switching properties. In this communication, co-propagati

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46

Singh, Lokendra, Amna Bedi, and Santosh Kumar. "Modeling of all-optical even and odd parity generator circuits using metal-insulator-metal plasmonic waveguides." Photonic Sensors 7, no. 2 (2017): 182–92. http://dx.doi.org/10.1007/s13320-017-0365-9.

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47

Skyba, O., I. Domanov, and V. Kravchenko. "INVESTIGATION OF RISKS OF INFLUENCE OF THE RESULTS OF THE OPERATION DIVISION ON THE QUALITY OF PSEUDO-RANDOM VALUE GENERATORS EMBEDDED IN THE SOFTWARE." Наукові праці Державного науково-дослідного інституту випробувань і сертифікації озброєння та військової техніки, no. 8 (June 29, 2021): 126–33. http://dx.doi.org/10.37701/dndivsovt.8.2021.13.

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The article is devoted to certain approaches that concerned a checking random values obtained from the generator of random (pseudorandom) values. The article provides the results of a practical research of the numbers which are obtained during the division operation. The research was directed to find out the ratio of even and odd numbers in a quotients and remainders in the results of performing of the division operation. The analysis was carried out due to the fact that the remainder and quotient of division is widely used in various algorithms of software tools intended for generating

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48

Mahmood, Farhan Mosleh, Sahib Hasan Fadhil, and Majeed Azeez Ruaa. "Design and implementation of log domain decoder." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1454–568. https://doi.org/10.11591/ijece.v10i2.pp1454-1568.

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Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very clo

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49

Al-shar', Basim Yousef. "Delay and Performance Estimation for a 4-bit Even Parity Bit Generator Using the Logical Effort Model." International Review on Computers and Software (IRECOS) 10, no. 8 (2015): 814. http://dx.doi.org/10.15866/irecos.v10i8.6279.

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Zhang, Mu, Zulin Wang, Zhe Liu, Qin Huang, and Shuai Yuan. "Density optimisation of generator matrices of quasi-cyclic low-density parity-check codes and their rank analysis." IET Communications 8, no. 14 (2014): 2547–55. http://dx.doi.org/10.1049/iet-com.2014.0178.

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