Relevant bibliographies by topics / Pass transistor logic based adders

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Academic literature on the topic 'Pass transistor logic based adders'

Author: Grafiati
Published: 2 June 2025
Last updated: 5 July 2025

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Journal articles on the topic "Pass transistor logic based adders"

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Yin, Ningyuan, Wanyuan Pan, Yihe Yu, Chengcheng Tang, and Zhiyi Yu. "Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier." Electronics 12, no. 15 (2023): 3209. http://dx.doi.org/10.3390/electronics12153209.

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With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.
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Rajitha, J. "Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits." International Journal for Research in Applied Science and Engineering Technology 12, no. 2 (2024): 1042–48. http://dx.doi.org/10.22214/ijraset.2024.58495.

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Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.
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Chaitanya, S.* Abhishek B. S. Harshavardhan S. Karthik S. Manju T. M. "Design and Analysis of Adders Using Pass Transistor Logic for Multipliers." International Journal of Scientific Research and Technology 2, no. 5 (2025): 326–37. https://doi.org/10.5281/zenodo.15421140.

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This paper demonstrates the design and optimization of a Multiplier using pass transistor logic with half and full adders in 90 nm and 45 nm CMOS technology. The design methodology utilizes fewer transistors and low-power pass transistor logic to improve system efficiency. Implementation and simulation proved these designs to be superior than traditional CMOS designs in terms of area, delay, power dissipation, and energy efficiency. Optimized adders in the multiplier framework thus provide compact, power efficient multiplier design. A comparison to conventional designs shows significant reductions of power consumption, transistor count and delay and is therefore attractive for low-power, high-performance applications. This work contributes to VLSI design by addressing the major speed, area, and power trade-offs in digital systems. The optimized Multiplier is best suited for modern-day applications such as image and signal processing. The application area focuses on high-performance, high-energy efficiency, and clearly points out the advantages pass transistor logic can provide during digital circuit design to innovatively develop low-power, fast multipliers.
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Zhang, Qi, Yuping Wu, and Lan Chen. "A Subthreshold Bootstrapped SAPTL-Based Adder Design." Electronics 8, no. 10 (2019): 1161. http://dx.doi.org/10.3390/electronics8101161.

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This paper proposes a 16 bit subthreshold adder design using bootstrapped sense amplifier-based pass transistor logic (bootstrapped SAPTL) to overcome serious performance degradation and enhance the immunity to process variations in the subthreshold region. Through employing a bootstrapped sense amplifier including a voltage boosting part and adopting an adder architecture based on bootstrapped SAPTL, significant improvements in performance and energy efficiency can be achieved. A case study of 16 bit adders in SMIC 130 nm technology demonstrated that the proposed adder outperformed other works in terms of performance, energy consumption, and energy efficiency. Furthermore, the statistical results of the Monte Carlo analysis proved the proposed adder’s significant enhancement of robustness against process and temperature variations. At 0.3 V (TT corner, 25 °C), the proposed 16 bit adder achieved improvements of 72% in performance and 8% in energy savings, as well as a 74% reduction in energy-delay production as compared with the current design.
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Barla, Prashanth, Vinod Kumar Joshi, and Somashekara Bhat. "Design and evaluation of hybrid SHE+STT-MTJ/CMOS full adder based on LIM architecture." IOP Conference Series: Materials Science and Engineering 1187, no. 1 (2021): 012015. http://dx.doi.org/10.1088/1757-899x/1187/1/012015.

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Abstract This work aimed at developing a full adder using hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) based on the logic-in-memory architecture (LIM). LIM has emerged as the most promising alternative to the standard von-Neumann architecture in the impeding post-CMOS era. Performance of the hybrid full adder is evaluated in terms of power, delay, power delay product (PDP), and device count. These results are compared with the existing double pass transistor logic-based clocked CMOS (DPTL-C2MOS) full adder. Further, Monte-Carlo simulations on both variants of full adders were conducted to study their performance. Simulation results reveal that the hybrid full adder is superior to the DPTL-C2MOS full adder and can be used in low power and high throughput computing systems in the near future.
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Yu, Yihe, Wanyuan Pan, Chengcheng Tang, Ningyuan Yin, and Zhiyi Yu. "Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model." Electronics 13, no. 7 (2024): 1284. http://dx.doi.org/10.3390/electronics13071284.

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The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.
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Raju, Hajare, and Lakshminarayana C. "Design and software characterization of finFET based full adders." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 1 (2019): 51–60. https://doi.org/10.11591/ijres.v8.i1.pp51-60.

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Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.
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Hu, Jian Ping, Xiao Ying Yu, and Bin Bin Liu. "Manufacturing and Testing of Adiabatic Array Multiplier for Micro Power Digital Systems." Key Engineering Materials 460-461 (January 2011): 473–78. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.473.

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Power-efficient multipliers are essential for micro systems, where low-power signal processing hardware is demanded. This paper presents an adiabatic array multiplier based on PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits. It is composed of a multiplier array containing partial product generators and 1-bit (half and full) adders, and a final carry-lookahead adder. For comparison, a conventional array multiplier is also implemented. Full-custom layouts are drawn, and HSPICE simulations are carried out using the net-list extracted from their layout. The adiabatic and conventional array multipliers have been embedded in a test chip, which have been fabricated with Chartered 0.35um process and tested to verify its function.
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Gnilenko, Alexey. "LAYOUT DESIGN OF 4-BIT RIPPLE CARRY ADDER BASED ON PASS TRANSISTOR LOGIC." System technologies 1, no. 126 (2020): 46–53. http://dx.doi.org/10.34185/1562-9945-1-126-2020-05.

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The full adder is a key element of any arithmetic logic units used in microprocessor systems. For microprocessor components created for modern mobile digital devices, compact layout design on the silicone chip is of great importance. In this paper an area effective layout design on the chip is proposed for 4-bit ripple carry adder based on pass transistor logic. The full adder is simulated using EDA tool and output signal waveforms are obtained to demonstrate the functionality of the design. It is shown that 1-bit full adder based on pass transistor logic and composed of two 3T XOR gates and one 2T multiplexer allows us to obtain area effective layout design on the chip for 4-bit ripple carry adder providing acceptable characteristics for output signals.
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Rajasekhar, K., B. Sandhya, G. Srinivas, and N. Manogna. "Performance of Different Full Adder Structures for Optimized Design." International Journal of Advance Research and Innovation 8, no. 2 (2020): 74–80. http://dx.doi.org/10.51976/ijari.822013.

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Design of high performance and energy efficient digital systems are one of the most important research areas in VLSI system design which is suitable for real-time applications. One of the functional elements used in complex arithmetic circuits is an adder. To design an energy efficient adder one-bit full adder cell is designed based on adiabatic logic. The proposed ALFA cell is designed using adiabatic logic which results with the negligible amount of exchange of energy with the surrounding environment. Therefore, the application circuits based on this logic will have negligible energy loss due to heat dissipation. It requires 24 transistors to get the true and complimentary arithmetic sum and carry output. The proposed adiabatic logic based full adder (ALFA) cell processes the three single bit inputs and provides the output as sum, carry, sum bar and carry bar in a single architecture. The proposed ALFA cell reduces the power consumption by 98.49%, 90.93%, and 89.37%, respectively, when compared to CMOS full adder, 14T pass-transistor logic (PTL) with transmission gate (TG) full adder and 16T PTL with TG full adder.
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Dissertations / Theses on the topic "Pass transistor logic based adders"

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Hsu, Chih-Cheng, and 許志成. "Automatic Optimization in Pass-Transistor-Based Logic Synthesizer." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/86877104888035726165.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>88<br>In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs little executing time for searching the best result and we can quickly gate it.
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Cho, Hamm-Min, and 卓瀚民. "Mixing Pass-Transistor Logic with CMOS Logic for Low-Power Cell- Based Designs." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/83489899657484360995.

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碩士<br>國立中正大學<br>電機工程學系<br>86<br>Owing to the demand of the portable products small area and low- power are the main considerations in cell-based IC design. In this thesis we try to propose a methodology to combine pass- transistor logic and complementary CMOS logic to reduce power consumption. We first identify the types of logic functions suited for each individual logic style. Then we replace certain complementary CMOS cells in the cell library with pass- transistor cells. The modified cell library is used in conjunction with a logic restructuring algorithm to promote the use of pass-transistor logic in general combinational circuit. Empirical results using MCNC LGSynth'91 benchmark circuits show that an average of 13.48% power reduction can be attained through the use of the proposed method.
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Chen, Dai-Yen, and 陳達彥. "Logic/Circuit Synthesizer Based on Low-Complexity Pass-Transistor Cell Library." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/15156757388339666671.

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碩士<br>國立中山大學<br>資訊工程研究所<br>87<br>In this thesis, A pass-transistor-based cell library containing four types of cells is designed and the corresponding logic/circuit synthesizer is developed for logic mapping of any combinational and dynamic circuits. There are four driven capability selects for each type of cells. The format of input is Boolean functions with expressions of sum of product and we can input several functions for hardware sharing at the same time. It provides several optional modes such as high density、high performance、dynamic logic circuit, etc. . It also does optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. Due to the small number of cells in library, it is easy to migrate to a new process technology.
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Wen, Chia-Sheng, and 溫家聖. "Logic Synthesis of High-Performance Combinational Circuits Based on Pass-Transistor Cell Library." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/69965336703238055475.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>91<br>This thesis proposes a new variable-order prediction method to predict the Shannon expansion order during the BDD tree generator. Combining this method with the original minimum width method, we can generator a better BDD tree to be used in our pass-transistor logic synthesizer. Also we propose two partitioning methods to reduce the length of the critical paths. The first method can effectively reduce the critical path delay at the cost of much higher area cost. The second method explores the common factors in the Boolean functions to reduce the critical path delay with reasonably increased area cost. Furthermore, we discuss the methods of inserting regenerating inverters/buffers along the path in BDD tree by selecting inverter cells and MUX cells of proper driving strength to optimize the area/cost/power performance. Finally, the automatic layout generation is considered to produce the physical layout more efficiently compared with that using commericial automatic place-and-route tools.
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Book chapters on the topic "Pass transistor logic based adders"

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Raj, Sumit, Utkarsh Chaurasia, Aayush Bahukhandi, and Poornima Mittal. "Hybrid Approximate Adders Using Pass Transistor Logic and Transmission Gate." In Advances in Intelligent Systems and Computing. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-4369-9_28.

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Babu, Hafiz Md Hasan. "Voltage-Mode Pass Transistor-Based Multi-Valued Multiple-Output Logic Circuits." In VLSI Circuits and Embedded Systems. CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-10.

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Ni, Haiyan, Xiaolei Sheng, and Jianping Hu. "Voltage Scaling for Adiabatic Register File Based on Complementary Pass-Transistor Adiabatic Logic." In Lecture Notes in Electrical Engineering. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19706-2_6.

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Tripathi, Sweta, Anum Khan, and Subodh Wairya. "Performance Evaluation of Master–Slave D Flip Flop Based on Charge Retention Feedback Pass Transistor Logic in Nanotechnology." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-2761-3_38.

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Conference papers on the topic "Pass transistor logic based adders"

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S, Kusuma H., H. M. Kalpana, and Ravi H. K. "Design and Comparative Analysis of Half and Full Adders Using CMOS and Pass Transistor Logic Styles." In 2025 3rd International Conference on Smart Systems for applications in Electrical Sciences (ICSSES). IEEE, 2025. https://doi.org/10.1109/icsses64899.2025.11010034.

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Sardroudi, Farzin Mahboob, Mehdi Habibi, and Mohammad Hossein Moaiyeri. "Design of Long Signal Path Ternary Computational Blocks Using Dynamic and Pass Transistor Logic Based on Carbon Nanotube Field Effect Transistors." In 2024 6th Iranian International Conference on Microelectronics (IICM). IEEE, 2024. https://doi.org/10.1109/iicm65053.2024.10824662.

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R, Durai Balaji, D. S. Shylu Sam, Manoj G, et al. "Design of Low Power Pass Transistor Logic Based Adders for Multiplier in 90nm CMOS Process." In 2023 4th International Conference on Signal Processing and Communication (ICSPC). IEEE, 2023. http://dx.doi.org/10.1109/icspc57692.2023.10125717.

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Kamsani, Noor Ain, Veeraiyah Thangasamy, Shaiful Jahari Hashim, Zubaida Yusoff, Muhammad Faiz Bukhori, and Mohd Nizar Hamidon. "A low power multiplexer based pass transistor logic full adder." In 2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM). IEEE, 2015. http://dx.doi.org/10.1109/rsm.2015.7354994.

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B, Veena M., Suhana Khanum N, and Soundaryya D. H. "XNOR-XOR based Full Adder Using Double Pass Transistor Logic." In 2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS). IEEE, 2023. http://dx.doi.org/10.1109/icaecis58353.2023.10169925.

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Lin, Jin-Fa, Yin-Tsung Hwang, and Ming-Hwa Sheu. "Low power 10-transistor full adder design based on degenerate pass transistor logic." In 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6272074.

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Reddy, G. Karthik. "Low power-area Pass Transistor Logic based ALU design using low power full adder design." In 2015 IEEE 9th International Conference on Intelligent Systems and Control (ISCO). IEEE, 2015. http://dx.doi.org/10.1109/isco.2015.7282289.

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Parihar, Rajesh, Nidhi Tiwari, Aditya Mandloi, and Binod Kumar. "An implementation of 1-bit low power full adder based on multiplexer and pass transistor logic." In 2014 International Conference on Information Communication and Embedded Systems (ICICES). IEEE, 2014. http://dx.doi.org/10.1109/icices.2014.7034071.

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Dang, Fangyuan, Yuan Wang, Yuequan Liu, Song Jia, and Xing Zhang. "Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation." In 2015 IEEE 11th International Conference on ASIC (ASICON ). IEEE, 2015. http://dx.doi.org/10.1109/asicon.2015.7517075.

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Hasan, Khaled, Sidrat Muntaha Nur Pranto, Shuvankar Biswas, Fajla Rabby, Md Atiqur Rahman, and Md Anwarul Abedin. "Design of Pass Transistor-Based Low-Power Approximate Adders for DSP Application." In 2023 26th International Conference on Computer and Information Technology (ICCIT). IEEE, 2023. http://dx.doi.org/10.1109/iccit60459.2023.10441300.

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