Journal articles on the topic 'Pass transistor logic based adders'
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Yin, Ningyuan, Wanyuan Pan, Yihe Yu, Chengcheng Tang, and Zhiyi Yu. "Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier." Electronics 12, no. 15 (2023): 3209. http://dx.doi.org/10.3390/electronics12153209.
Full textRajitha, J. "Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits." International Journal for Research in Applied Science and Engineering Technology 12, no. 2 (2024): 1042–48. http://dx.doi.org/10.22214/ijraset.2024.58495.
Full textChaitanya, S.* Abhishek B. S. Harshavardhan S. Karthik S. Manju T. M. "Design and Analysis of Adders Using Pass Transistor Logic for Multipliers." International Journal of Scientific Research and Technology 2, no. 5 (2025): 326–37. https://doi.org/10.5281/zenodo.15421140.
Full textZhang, Qi, Yuping Wu, and Lan Chen. "A Subthreshold Bootstrapped SAPTL-Based Adder Design." Electronics 8, no. 10 (2019): 1161. http://dx.doi.org/10.3390/electronics8101161.
Full textBarla, Prashanth, Vinod Kumar Joshi, and Somashekara Bhat. "Design and evaluation of hybrid SHE+STT-MTJ/CMOS full adder based on LIM architecture." IOP Conference Series: Materials Science and Engineering 1187, no. 1 (2021): 012015. http://dx.doi.org/10.1088/1757-899x/1187/1/012015.
Full textYu, Yihe, Wanyuan Pan, Chengcheng Tang, Ningyuan Yin, and Zhiyi Yu. "Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model." Electronics 13, no. 7 (2024): 1284. http://dx.doi.org/10.3390/electronics13071284.
Full textRaju, Hajare, and Lakshminarayana C. "Design and software characterization of finFET based full adders." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 1 (2019): 51–60. https://doi.org/10.11591/ijres.v8.i1.pp51-60.
Full textHu, Jian Ping, Xiao Ying Yu, and Bin Bin Liu. "Manufacturing and Testing of Adiabatic Array Multiplier for Micro Power Digital Systems." Key Engineering Materials 460-461 (January 2011): 473–78. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.473.
Full textGnilenko, Alexey. "LAYOUT DESIGN OF 4-BIT RIPPLE CARRY ADDER BASED ON PASS TRANSISTOR LOGIC." System technologies 1, no. 126 (2020): 46–53. http://dx.doi.org/10.34185/1562-9945-1-126-2020-05.
Full textRajasekhar, K., B. Sandhya, G. Srinivas, and N. Manogna. "Performance of Different Full Adder Structures for Optimized Design." International Journal of Advance Research and Innovation 8, no. 2 (2020): 74–80. http://dx.doi.org/10.51976/ijari.822013.
Full textRamana Murthy, G., C. Senthilpari, P. Velrajkumar, and Lim Tien Sze. "Monte-Carlo analysis of a new 6-T full-adder cell for power and propagation delay optimizations in 180 nm process." Engineering Computations 31, no. 2 (2014): 149–59. http://dx.doi.org/10.1108/ec-01-2013-0023.
Full textAbdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim, and Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology." Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.
Full textShah, Ambika Prasad, Rajat Kumar Jain, and Vaibhav Neema. "A Novel Energy Efficient High-Speed 10-Transistor Full Adder Cell Based on Pass Transistor Logic." Journal of Nanoelectronics and Optoelectronics 12, no. 5 (2017): 499–504. http://dx.doi.org/10.1166/jno.2017.2030.
Full textKumar, Raushan, Sahadev Roy, and C. T. Bhunia. "Low-Power High-Speed Double Gate 1-bit Full Adder Cell." International Journal of Electronics and Telecommunications 62, no. 4 (2016): 329–34. http://dx.doi.org/10.1515/eletel-2016-0045.
Full textMehrabani, Yavar Safaei, Reza Faghih Mirzaee, and Mohammad Eshghi. "A novel low-energy CNFET-based full adder cell using pass-transistor logic." International Journal of High Performance Systems Architecture 5, no. 4 (2015): 193. http://dx.doi.org/10.1504/ijhpsa.2015.072846.
Full textV, Thamizharasan, and Ramya M. "Investigation on Power, Delay and Area optimization of XOR Gate." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 19 (February 24, 2021): 297–304. http://dx.doi.org/10.37394/23201.2020.19.32.
Full textTirumalasetty, Venkata Rao, K. Babulu, and G. Appala Naidu. "Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design." WSEAS TRANSACTIONS ON SYSTEMS 23 (April 9, 2024): 141–48. http://dx.doi.org/10.37394/23202.2024.23.16.
Full textManchala, Venkat Subba Rao, Satyajeet Sahoo, and G. Ramana Murthy. "Design of Hybrid Full Adder using 6T-XOR-Cell for High Speed Processor Designs Applications." International Journal on Recent and Innovation Trends in Computing and Communication 10, no. 1s (2022): 329–36. http://dx.doi.org/10.17762/ijritcc.v10i1s.5900.
Full textS, Sriram Sundar, and Mahendran G. "CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications." Integration 95 (March 2024): 102132. http://dx.doi.org/10.1016/j.vlsi.2023.102132.
Full textBhattacharjee, Pritam, and Alak Majumder. "A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950108. http://dx.doi.org/10.1142/s0218126619501081.
Full textHAMDI, Belgacem, Khaled Ben Khalifa, and Aymen FRADI. "HYBRID-CMOS LOGIC STYLE DESIGN FOR FAST SELF-CHECKING ADDERS DATA PATHS." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 10, no. 6 (2013): 1771–78. http://dx.doi.org/10.24297/ijct.v10i6.7025.
Full textMeenaakshiSundari, R. P. "Implementation of Low Power CMOS Full Adders Using Pass Transistor Logic." IOSR Journal of VLSI and Signal Processing 2, no. 5 (2013): 38–43. http://dx.doi.org/10.9790/4200-0253843.
Full textRao Tirumalasetty, Venkata, C. V. Mohan Krishna, K. Sai Sree Tanmaie, T. Lakshmi Naveena, and Ch Jonathan. "A novel design of high performance1-bit adder circuit at deep sub-micron technology." International Journal of Engineering & Technology 7, no. 1.1 (2017): 660. http://dx.doi.org/10.14419/ijet.v7i1.1.10822.
Full textRebecca Florance, D., B. Prabhakar, and Manoj Kumar Mishra. "Design and Implementation of ALU Using Graphene Nanoribbon Field-Effect Transistor and Fin Field-Effect Transistor." Journal of Nanomaterials 2022 (July 1, 2022): 1–17. http://dx.doi.org/10.1155/2022/3487853.
Full textOno, Y., H. Inokawa, and Y. Takahashi. "Binary adders of multigate single-electron transistors: specific design using pass-transistor logic." IEEE Transactions on Nanotechnology 1, no. 2 (2002): 93–99. http://dx.doi.org/10.1109/tnano.2002.804743.
Full textSHUKLA, SOUMITRA, BAHNIMAN GHOSH, and MOHAMMAD WASEEM AKRAM. "1-BIT FULL ADDER IMPLEMENTATION USING SINGLE SPIN LOGIC PARADIGM." SPIN 02, no. 02 (2012): 1250012. http://dx.doi.org/10.1142/s2010324712500129.
Full textSarada Musala. "Analysis of Energy Efficient Differential Fault Tolerant Adders with Minimized Nonlinearities." Communications on Applied Nonlinear Analysis 32, no. 5s (2024): 69–77. https://doi.org/10.52783/cana.v32.2968.
Full textHsiao, Shen-Fu, Jia-Siang Yeh, and Da-Yen Chen. "High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic." VLSI Design 15, no. 1 (2002): 417–26. http://dx.doi.org/10.1080/1065514021000054736.
Full textVallem, Dr Sharmila, G. Tejaswi, Hrithik Sidharth, and Shilpa Reddy. "High Performance, Low Power Wallace Tree Multiplier." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 2 (2023): 20–25. http://dx.doi.org/10.35940/ijrte.b7685.0712223.
Full textDr., Sharmila Vallem, Tejaswi G., Sidharth Hrithik, and Reddy Shilpa. "High Performance, Low Power Wallace Tree Multiplier." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 2 (2023): 20–25. https://doi.org/10.35940/ijrte.B7685.0712223.
Full textDatta, Rajesh Kumar. "A Pass Transistor based Multifunction Gate Design." Indian Journal of VLSI Design 3, no. 2 (2023): 5–8. http://dx.doi.org/10.54105/ijvlsid.b1222.093223.
Full textRajesh, Kumar Datta. "A Pass Transistor based Multifunction Gate Design." Indian Journal of VLSI Design (IJVLSID) 3, no. 2 (2023): 5–8. https://doi.org/10.54105/ijvlsid.B1222.093223.
Full textHatefinasab, Seyedehsomayeh. "Carbon Nanotube Field Effect Transistor-Based Hybrid Full Adders Using Gate-Diffusion Input Structure." Journal of Nanoelectronics and Optoelectronics 14, no. 11 (2019): 1512–22. http://dx.doi.org/10.1166/jno.2019.2661.
Full textSrilakshmi, K., A. V. S. Karthikeya Chowdary, D. Lakshmi Soumya, Ch Hemasri, and G. Pavan Kumar. "Performance Analysis of High Speed Low Power BCD Adder using CMOS and Dynamic logic." Indian Journal Of Science And Technology 18, no. 21 (2025): 1703–15. https://doi.org/10.17485/ijst/v18i21.700.
Full textYUAN, SHOUCAI, and YAMEI LIU. "DUAL THRESHOLD VOLTAGE DOMINO ADDER DESIGN WITH PASS TRANSISTOR LOGIC USING STANDBY SWITCH FOR REDUCING SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 03 (2014): 1450043. http://dx.doi.org/10.1142/s0218126614500431.
Full textParameshwara, M. C., and H. C. Srinivasaiah. "Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications." Journal of Circuits, Systems and Computers 26, no. 01 (2016): 1750014. http://dx.doi.org/10.1142/s0218126617500141.
Full textTsung-Te Liu, L. P. Alarcon, M. D. Pierson, and J. M. Rabaey. "Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 7 (2009): 883–92. http://dx.doi.org/10.1109/tvlsi.2008.2012054.
Full textMurthy, G. Ramana, C. Senthilpari, P. Velrajkumar, and T. S. Lim. "Monte-Carlo Analysis of a New 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process." Applied Mechanics and Materials 284-287 (January 2013): 2580–89. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2580.
Full textBobba, Ramyabanu, and Pooja Illa. "XOR Based Carry Select Adder for Area and Delay." International Journal of Innovative Science and Research Technology 5, no. 6 (2020): 1615–21. http://dx.doi.org/10.38124/ijisrt20jun1117.
Full textPathak, Anjali. "Advanced Ternary Addition Circuits Leveraging Carbon Nanotube Field-Effect Transistors." International Journal for Research in Applied Science and Engineering Technology 13, no. 7 (2025): 562–70. https://doi.org/10.22214/ijraset.2025.73036.
Full textEt.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.
Full textK Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.
Full textB.Paulchamy, K.Kalpana, and J.Jaya. "An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 2605–11. https://doi.org/10.35940/ijeat.C5311.029320.
Full textSuguna, T., and M. Janaki Rani. "Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications." International Journal of Interactive Mobile Technologies (iJIM) 14, no. 05 (2020): 73. http://dx.doi.org/10.3991/ijim.v14i05.13343.
Full textC., Venkataiah, Mallikarjuna Rao Y., Manjula Jayamma, et al. "Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits." E3S Web of Conferences 391 (2023): 01221. http://dx.doi.org/10.1051/e3sconf/202339101221.
Full textAvedillo, María J., José M. Quintana, and Raúl Jiménez-Naharro. "Pass-transistor based implementations of threshold logic gates for WOS filtering." Microelectronics Journal 35, no. 11 (2004): 869–73. http://dx.doi.org/10.1016/j.mejo.2004.07.006.
Full textBhuvaneswari, Thangavel, Vishnuvajjula Charan Prasad, and Ajay Kumar Singh. "Reversed signal propagation BDD based low-power pass-transistor logic synthesis." IEEJ Transactions on Electrical and Electronic Engineering 8, S1 (2013): S66—S71. http://dx.doi.org/10.1002/tee.21920.
Full textJiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.
Full textPandey, Neeta, Kirti Gupta, and Bharat Choudhary. "New Proposal for MCML Based Three-Input Logic Implementation." VLSI Design 2016 (September 19, 2016): 1–10. http://dx.doi.org/10.1155/2016/8712768.
Full textHemanth, Badri Sai, and M. Sathish Kumar. "Low power, less area, and highly efficient hybrid 1-bit full adder." Journal of Physics: Conference Series 2571, no. 1 (2023): 012026. http://dx.doi.org/10.1088/1742-6596/2571/1/012026.
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