Relevant bibliographies by topics / Pass transistors logic

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Pass transistors logic'

Author: Grafiati
Published: 5 June 2025
Last updated: 24 June 2025

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Journal articles on the topic "Pass transistors logic"

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Hu, Xuan, Amy S. Abraham, Jean Anne C. Incorvia, and Joseph S. Friedman. "Hybrid Pass Transistor Logic With Ambipolar Transistors." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 1 (2021): 301–10. http://dx.doi.org/10.1109/tcsi.2020.3034042.

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Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.
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B S, Vinayashree, and Santhosh Babu K C. "Layout Design of Row Decoder using Cadence." International Journal for Research in Applied Science and Engineering Technology 10, no. 8 (2022): 461–68. http://dx.doi.org/10.22214/ijraset.2022.46214.

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Abstract: Logic circuits, data transport circuits, and analogue to digital conversions all frequently employ decoders. For the line decoders, a mixed logic design approach incorporating transmission gate logic, pass transistor logic, and complementary metaloxide semiconductor (CMOS) technology is employed to achieve the desired performance and operation. A unique topology is proposed for the 2 to 4 decoders, which calls for a topology with fourteen transistors to reduce operating power and transistor count and a topology with fifteen transistors to achieve high power and low delay performance. For a total of four new designs, standard and inverting decoders are created for each situation. All of the suggested decoders have a low transistor count in comparison to their traditional CMOS architectures. Last but not least, a number of suggested solutions demonstrate a notable improvement in operating power and propagation latency, exceeding CMOS in virtually all instances
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Rao Tirumalasetty, Venkata, C. V. Mohan Krishna, K. Sai Sree Tanmaie, T. Lakshmi Naveena, and Ch Jonathan. "A novel design of high performance1-bit adder circuit at deep sub-micron technology." International Journal of Engineering & Technology 7, no. 1.1 (2017): 660. http://dx.doi.org/10.14419/ijet.v7i1.1.10822.

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In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.
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Yin, Ningyuan, Wanyuan Pan, Yihe Yu, Chengcheng Tang, and Zhiyi Yu. "Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier." Electronics 12, no. 15 (2023): 3209. http://dx.doi.org/10.3390/electronics12153209.

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With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.
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Pandey, Neeta, Damini Garg, Kirti Gupta, and Bharat Choudhary. "Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style." Journal of Engineering 2016 (2016): 1–10. http://dx.doi.org/10.1155/2016/8027150.

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This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.
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Chaitanya, S.* Abhishek B. S. Harshavardhan S. Karthik S. Manju T. M. "Design and Analysis of Adders Using Pass Transistor Logic for Multipliers." International Journal of Scientific Research and Technology 2, no. 5 (2025): 326–37. https://doi.org/10.5281/zenodo.15421140.

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This paper demonstrates the design and optimization of a Multiplier using pass transistor logic with half and full adders in 90 nm and 45 nm CMOS technology. The design methodology utilizes fewer transistors and low-power pass transistor logic to improve system efficiency. Implementation and simulation proved these designs to be superior than traditional CMOS designs in terms of area, delay, power dissipation, and energy efficiency. Optimized adders in the multiplier framework thus provide compact, power efficient multiplier design. A comparison to conventional designs shows significant reductions of power consumption, transistor count and delay and is therefore attractive for low-power, high-performance applications. This work contributes to VLSI design by addressing the major speed, area, and power trade-offs in digital systems. The optimized Multiplier is best suited for modern-day applications such as image and signal processing. The application area focuses on high-performance, high-energy efficiency, and clearly points out the advantages pass transistor logic can provide during digital circuit design to innovatively develop low-power, fast multipliers.
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Lamani, Deepa Suranam, and Dr H. V. Ravish Aradhya. "Design of Low Power 64-Bit Hybrid Full Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 8 (2023): 2200–2205. http://dx.doi.org/10.22214/ijraset.2023.55554.

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Abstract: In the realm of Computer Science, integrated circuits (ICs) have propelled microprocessor and digital signal processor development, hinging on the 1-bit full adder's significance for mathematical tasks. To amplify overall efficiency, enhancing this adder is pivotal. As demand surges for power-efficient devices like smartphones and MP3 players, maintaining a balance between speed, size, and power usage becomes imperative. Engineers tackle this challenge while bridging battery technology gaps. We propose advanced 1-bit full adder designs, evaluated via Cadence Virtuoso. A hybrid version merges Pass-Transistor Logic (PTL), Transmission Gates (TGs), and static CMOS logic. An optimized alternative incorporates efficient 3T-XOR logic. The comparative study considers crucial metrics: the existing FA’s 8.83µW power vs. the proposed's 8.49µW; the proposed's shorter delay of 64.53ps vs. the existing FA’s 83.1ps (18 vs. 22 transistors). At 64 bits, the existing FA’s consumes 66.8µW with a 470.94ps delay (1408 transistors), while the proposed maintains 35.05µW, 64.53ps, and fewer transistors (1152). In summary, the proposed adder excels in efficiency, delay, and transistor use for energy-efficient arithmetic operations.
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Hameed, Isam Salah, Salah Alkurwy, and Heba Hadi Ali. "Implementation of Pass Transistor Logic and C2MOS Linear Feedback Shift Register (LFSR) Circuit using FPGA and PSpice." International Journal of Electrical and Electronics Research 13, no. 1 (2025): 164–70. https://doi.org/10.37391/ijeer.130121.

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In this paper, a 4-bit Linear Feedback Shift Register (LFSR) is implemented based on a well-designed architecture combining using Pass-Transistor (PT) and Clock Complementary Metal Oxide Semiconductor (C2MOS) logic techniques. The D-flip flop registers and the XOR gates are the main parts of the propose LFSR. Number of transistors along with the speed of LFSR were positively enhanced since the exploited logic design techniques tends to blend the flavor of NMOS and PMOS devices. The PSpice and Field Programmable Gate Array (FPGA) based on Hardware Description Language (HDL) are the two different LFSR implementation environments. It has been observed that LFSR performance was effectively improved in terms of size and speed. Therefore, paper’s main aim refers to decreasing in number of transistors as well as speeding up LFSR circuit. A minimum clock time of 5ns was recorded under clearly correct LFSR output patterns. The LFSR circuit Based CMOS techniques can reduce the exploited transistors up to 43% of the conventional C2MOS logic. Besides, the number of transistors being reduced reflects the achieved circuit’s size reduction. It was concluded that paying attention to the design of the main LFSR circuit parts contributes mainly in the enhancement of the whole circuit performance.
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B., Jeevan, and Sivani K. "Heterogeneous Logic: a High Performance and Low Power Non-CMOS 4-1 Multiplexer." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2021): 3237–43. https://doi.org/10.35940/ijeat.C6201.029320.

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A novel non-CMOS 4-1 multiplexer using heterogeneous logic style is presented in this brief. The heterogeneous logic design uses the combination of three basic logic styles such as Dual Value Logic (DVL), Transmission Gate Logic (TGL) and Simple Pass Transistor Logic (SPTL). The design uses only two stacking transistors in between the supply rails. Only 16 transistors are required for the actual logic function in the proposed state-of-the-art design. Number of transistors is reduced by distinctly choosing DVL and TGL in the first stage as per the input combination. Later stage of the multiplexer is constructed using SPTL. A required logic style is chosen at first and second stage in accordance with input bit combination to minimize the number of transistors, enhance the speed of logic transition and reduce the average power dissipation. The design and simulation analysis of proposed circuit is carried out at 22nm technology using Pyxis Schematic and Pyxis Simulator. Comparison of wide-ranging simulated results of proposed design, CMOS tree multiplexer and CMOS NOR multiplexer at various supply voltages and frequencies on same technology node manifests that the performance of proposed heterogeneous multiplexer is better in terms of speed and power dissipation. At minimum possible supply voltage of 0.8V and at moderate frequency of 1GHz, the proposed multiplexer achieves, reduced power dissipation of 17.3% and reduced in delay of 9.14%. The count of transistors including inverters is also less compared to CMOS tree type and CMOS NOR type multiplexers. However, robustness of mixed logic style designs is to be improved compared to CMOS designs.
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Dissertations / Theses on the topic "Pass transistors logic"

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Garg, Rajesh. "Generalized buffering of pass transistor logic (PTL) stages using Boolean division and don't cares." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5906.

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Pass Transistor Logic (PTL) is a well known approach for implementing digital circuits. In order to handle larger designs and also to ensure that the total number of series devices in the resulting circuit is bounded, partitioned Reduced Ordered Binary Decision Diagrams (ROBDDs) can be used to generate the PTL circuit. The output signals of each partitioned block typically needs to be buffered. In this thesis, a new methodology is presented to perform generalized buffering of the outputs of PTL blocks. By performing the Boolean division of each PTL block using different gates in a library, we select the gate that results in the largest reduction in the height of the PTL block. In this manner, these gates serve the function of buffering the outputs of the PTL blocks, while also reducing the height and delay of the PTL block. PTL synthesis with generalized buffering was implemented in two different ways. In the first approach, Boolean division was used to perform generalized buffering. In the second approach, compatible observability don't cares (CODCs) were utilized in tandem with Boolean division to simplify the ROBDDs and to reduce the logic in PTL structure. Also CODCs were computed in two different manners: one using full simplify to compute complete CODCs and another using, approximate CODCs (ACODCs). Over a number of examples, on an average, generalized buffering without CODCs results in a 24% reduction in delay, and a 3% improvement in circuit area, compared to a traditional buffered PTL implementation. When ACODCs were used, the delay was reduced by 29%, and the total area was reduced by 5% compared to traditional buffering. With complete CODCs, the delay and area reduction compared to traditional buffering was 28% and 6% respectively. Therefore, results show that generalized buffering provides better implementation of the circuits than the traditional buffering method.
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Henry, Michael B. "Emerging Power-Gating Techniques for Low Power Digital Circuits." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/29627.

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As transistor sizes scale down and levels of integration increase, leakage power has become a critical problem in modern low-power microprocessors. This is especially true for ultra-low-voltage (ULV) circuits, where high levels of leakage force designers to chose relatively high threshold voltages, which limits performance. In this thesis, an industry-standard technique known as power-gating is explored, whereby transistors are used to disconnect the power from idle portions of a chip. Present power-gating implementations suffer from limitations including non-zero off-state leakage, which can aggregate to a large amount of wasted energy during long idle periods, and high energy overhead, which limits its use to long-term system-wide sleep modes. As this thesis will show however, by vastly increasing the effectiveness of power-gating through the use of emerging technologies, and by implementing aggressive hardware-oriented power-gating policies, leakage in microprocessors can be eliminated to a large extent. This allows the threshold voltage to be lowered, leading to ULV microprocessors with both low switching energy and high performance. The first emerging technology investigated is the Nanoelectromechnical-Systems (NEMS) switch, which is a CMOS-compatible mechanical relay with near-infinite off-resistance and low on-resistance. When used for power-gating, this switch completely eliminates off-state leakage, yet is compact enough to be contained on die. This has tremendous benefits for applications with long sleep times. For example, a NEMS-power-gated architecture performing an FFT per hour consumes 30 times less power than a transistor-power-gated architecture. Additionally, the low on-resistance can lower power-gating area overhead by 36-83\%. The second technology targets the high energy overhead associated with powering a circuit on and off. This thesis demonstrates that a new logic style specifically designed for ULV operation, Sense Amplifier Pass Transistor Logic (SAPTL), requires power-gates that are 8-10 times smaller, and consumes up to 15 times less boot-up energy, compared to static-CMOS. These abilities enable effective power-gating of an SAPTL circuit, even for very short idle periods. Microprocessor simulations demonstrate that a fine-grained power-gating policy, along with this drastically lower overhead, can result in up to a 44\% drop in energy. Encompassing these investigations is an energy estimation framework built around a cycle-accurate microprocessor simulator, which allows a wide range of circuit and power-gating parameters to be optimized. This framework implements two hardware-based power-gating schedulers that are completely invisible to the OS, and have extremely low hardware overhead, allowing for a large number of power-gated regions. All together, this thesis represents the most complete and forward-looking study on power-gating in the ULV region. The results demonstrate that aggressive power-gating allows designers to leverage the very low switching energy of ULV operation, while achieving performance levels that can greatly expand the capabilities of energy-constrained systems.<br>Ph. D.
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Ragavan, Rengarajan. "Reconfigurable FSM for Ultra-Low Power Wireless Sensor Network Nodes." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100121.

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Wireless sensor networks (WSN) play an important role in today’s monitoring and controlsystems like environmental monitoring, military surveillance, industrial sensing and control, smarthome systems and tracking systems. As the application of WSN grows by leaps and bounds, there is anincreasing demand in placing a larger number of sensors and controllers to meet the requirements. Theincreased number of sensors necessitates flexibility in the functioning of nodes. Nodes in wirelesssensor networks should be capable of being dynamically reconfigured to perform various tasks is theneed of the hour.In order to achieve flexibility in node functionality, it is common to adopt reconfigurablearchitecture for WSN nodes. FPGA-based architectures are popular reconfigurable architectures bywhich WSN nodes can be programmed to take up different roles across time. Area and power are themajor overheads in FPGA based architectures, where interconnect consumes more power and area thanlogic cells. The contemporary WSN standard requires longer battery life and micro size nodes for easyplacement and maintenance-free operation for years together.Three solutions have been studied and evaluated to approach this problem: 1) Homogenousembedded FPGA platform, 2) Power gated reconfigurable finite state machines and 3) Pass transistorlogic (PTL) based reconfigurable finite state machines. Embedded FPGA is a CMOS 65nm customdeveloped small homogenous FPGA which holds the functionality of the WSN nodes and it will bedynamically reconfigured from time to time to change the functionality of the node. In Power gatedreconfigurable FSM architecture, the functionality of the node is expressed in the form of finite statemachines, which will be implemented in a LUT based power gated design. In PTL based reconfigurablefinite state machine architecture, the finite state machines are completely realized using PTL basedcustom designed sets of library components. Low power configuration memory is used to dynamicallyreconfigure the design with various FSMs at different times.
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WANG, JIA-LONG, and 王家龍. "Area-optimal pass transistor logic minimization." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/79027637899409777660.

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VEN-CHIEH, HSIEH, and 謝文傑. "A New Logic Synthesis and Optimization Procedure Using Pass-Transistor Logic." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/96660896455884414515.

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碩士<br>淡江大學<br>電機工程學系<br>88<br>At logic design level, a proper choice of a circuit style for implementing combinational logic is very important. Many kinds of logic styles using pass-transistor circuit have been proposed with the objective to improve the performance of static CMOS logic. And the advantages present by pass-transistor logic have been proved in many cases from 2-input XOR gate to Multiplier. But when compares to classical NAND/NOR or some other simple logic gate, functions can be realized with better performance and smaller area by using static CMOS logic. The result a logic style may provide high performance only in some specific logic functions may confuse someone in logic style selecting. So a formulation of universal rules for optimal logic style, which provide high performance for arbitrary logic function, is needed. Moreover, the static CMOS logic network structure can be seems as a special case of the pass-transistor logic network that pass variables are only power lines. Thus, it is possible to develop a new logic style combine the advantages of both static CMOS logic and pass-transistor logic for arbitrary logic function and high performance applications. The objective of this work is to propose a new logic circuit synthesis and optimization procedure for arbitrary logic function implementation. Follow the synthesis and optimization procedures, a high performance new circuit which is low power consumption, low power-delay product, area efficient and high robustness against transistor downsizing and voltage scaling will produced.
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Chen, Jian-Hung, and 陳建宏. "Low Power and High Speed Logic Synthesis with Pass Transistor Logic." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/59671970997835239984.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>89<br>In this thesis, a pass-transistor logic synthesizer is developed for logic mapping of any combinational circuits based on only two types of cells: 2-to-1 multiplexors and inverters. The input contains several sum-of-product Boolean function expressions. Our synthesizer will consider the hardware sharing among these Boolean functions in order to save area. The output of our synthesizer is pass-transistor-based circuits with optimized transistor width in terms of user-specified speed and power performance measurement. During optimization, the Elmore RC delay model is used to estimate the critical path delay and the power is characterized by the switching of all the internal nodes. The final outputs are HSPICE netlists and Verilog gate-level code that allow more detailed timing simulation and automatic placement-routing.
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Chen, Shi Zong, and 陳世宗. "Sirup: single rail up-down pass-transistor-logic." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/65632113048817408437.

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Hsu, Chih-Cheng, and 許志成. "Automatic Optimization in Pass-Transistor-Based Logic Synthesizer." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/86877104888035726165.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>88<br>In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs little executing time for searching the best result and we can quickly gate it.
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Teng-Yuan, Lin, and 林鼎源. "Analysis and Applications of Pass-Transistor/ CMOS Collaborated Logic." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/09404824821994602851.

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碩士<br>大同工學院<br>電機工程研究所<br>86<br>This thesis focuses on the analysis and application of PCCL. The PCCL is especially used in low-power VLSI and a universal gate. We try to implement a set of logic functions and discuss the waveforms attenuated by pass-transistors. We discuss the technique improved by inverter-restoring and the waveform can be restored to at 500 MHz operation frequency. We try to replace the level-restoring circuit of PCCL by inverter-latch one. Finally, we don't implement by BDD, but implement by AND and OR gates of convWe simulate the critical-path waveform by HSPICE. The process parameters adopt the UMC 0.5 process for education. In the fixed process, The result of power-delay-product improves to nearly 1/3 compared with CMOS logic-style in high process.
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Cho, Hamm-Min, and 卓瀚民. "Mixing Pass-Transistor Logic with CMOS Logic for Low-Power Cell- Based Designs." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/83489899657484360995.

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碩士<br>國立中正大學<br>電機工程學系<br>86<br>Owing to the demand of the portable products small area and low- power are the main considerations in cell-based IC design. In this thesis we try to propose a methodology to combine pass- transistor logic and complementary CMOS logic to reduce power consumption. We first identify the types of logic functions suited for each individual logic style. Then we replace certain complementary CMOS cells in the cell library with pass- transistor cells. The modified cell library is used in conjunction with a logic restructuring algorithm to promote the use of pass-transistor logic in general combinational circuit. Empirical results using MCNC LGSynth'91 benchmark circuits show that an average of 13.48% power reduction can be attained through the use of the proposed method.
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Books on the topic "Pass transistors logic"

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Mokhlesi, Jamileh. Design automation for differential pass-transistor logic. National Library of Canada, 1994.

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Mittal, Manish. Application of GaAS differential pass transistor logic in high speed digital circuits. National Library of Canada = Bibliothèque nationale du Canada, 1992.

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Pasternak, John Henry. High-speed differential pass-transistor logic. 1991.

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Pasternak, John Henry. CMOS pass-transistor logic design for VLSI. 1987.

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Book chapters on the topic "Pass transistors logic"

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Munteanu, Mihai, Peter A. Ivey, Luke Seed, Marios Psilogeorgopoulos, Neil Powell, and Istvan Bogdan. "Single Ended Pass-Transistor Logic." In VLSI: Systems on a Chip. Springer US, 2000. http://dx.doi.org/10.1007/978-0-387-35498-9_19.

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Babu, Hafiz Md Hasan. "Easily Testable PLAs Using Pass Transistor Logic." In VLSI Circuits and Embedded Systems. CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-16.

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Babu, Hafiz Md Hasan. "Multiple-Valued Flip-Flops Using Pass Transistor Logic." In VLSI Circuits and Embedded Systems. CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-9.

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Hu, Jianping, Xiaoyan Luo, and Li Su. "A New Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Evaluation Trees." In 2011 International Conference in Electrics, Communication and Automatic Control Proceedings. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8849-2_224.

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Raj, Sumit, Utkarsh Chaurasia, Aayush Bahukhandi, and Poornima Mittal. "Hybrid Approximate Adders Using Pass Transistor Logic and Transmission Gate." In Advances in Intelligent Systems and Computing. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-4369-9_28.

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Manju, C. S., N. Poovizhi, and R. Rajkumar. "Power Efficient Pulse Triggered Flip-Flop Design Using Pass Transistor Logic." In Emerging Trends in Computing and Expert Technology. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32150-5_5.

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Kanoujia, Sandhya, Rishav Kumar, and P. Karuppanan. "Low Power Radix-4 Booth Multiplier Design Using Pass Transistor Logic." In VLSI, Communication and Signal Processing. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0973-5_26.

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Babu, Hafiz Md Hasan. "Voltage-Mode Pass Transistor-Based Multi-Valued Multiple-Output Logic Circuits." In VLSI Circuits and Embedded Systems. CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-10.

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Ni, Haiyan, Xiaolei Sheng, and Jianping Hu. "Voltage Scaling for Adiabatic Register File Based on Complementary Pass-Transistor Adiabatic Logic." In Lecture Notes in Electrical Engineering. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19706-2_6.

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Hang, Guoqiang, Yang Yang, Xiaohui Hu, and Hongli Zhu. "Application of Neuron-MOS and Pass Transistor to Voltage-Mode Ternary Logic Circuit." In Electrical, Information Engineering and Mechatronics 2011. Springer London, 2012. http://dx.doi.org/10.1007/978-1-4471-2467-2_249.

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Conference papers on the topic "Pass transistors logic"

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Cheragh, Ghazal Mahmoudpoori, Palak Gupta, Gabriel Cadilha Marques, Giovanni Matei, and Jasmin Aghassi-Hagmann. "Pass Logic-Gates Based on Electrolyte-Gated Field-Effect Transistors with Metal Oxide Channels." In 2024 IEEE International Flexible Electronics Technology Conference (IFETC). IEEE, 2024. https://doi.org/10.1109/ifetc61155.2024.10771882.

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Sardroudi, Farzin Mahboob, Mehdi Habibi, and Mohammad Hossein Moaiyeri. "Design of Long Signal Path Ternary Computational Blocks Using Dynamic and Pass Transistor Logic Based on Carbon Nanotube Field Effect Transistors." In 2024 6th Iranian International Conference on Microelectronics (IICM). IEEE, 2024. https://doi.org/10.1109/iicm65053.2024.10824662.

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Chowdhury, Paramita, Arnesh Halder, Ankit Mahata, Anshu Das, Molla Safidur Rahaman, and Sunipa Roy. "Designing and Utilizing of Novel Pass Transistor Logic for Low Power CMOS Full Adder." In 2025 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI). IEEE, 2025. https://doi.org/10.1109/iatmsi64286.2025.10984669.

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S, Kusuma H., H. M. Kalpana, and Ravi H. K. "Design and Comparative Analysis of Half and Full Adders Using CMOS and Pass Transistor Logic Styles." In 2025 3rd International Conference on Smart Systems for applications in Electrical Sciences (ICSSES). IEEE, 2025. https://doi.org/10.1109/icsses64899.2025.11010034.

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Qin, Zhaoxing, Kunihiro Oshima, Kazunori Kuribara, and Takashi Sato. "OPTL: Robust and Area-Efficient Pass Gate Logic for Organic Transistors." In 2023 IEEE International Conference on Flexible and Printable Sensors and Systems (FLEPS). IEEE, 2023. http://dx.doi.org/10.1109/fleps57599.2023.10220369.

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Dickson, Kristofor, George Lange, Keith Serrels, et al. "Differential Laser Voltage Probe—A New Approach to a Fundamental Technique." In ISTFA 2022. ASM International, 2022. http://dx.doi.org/10.31399/asm.cp.istfa2022p0144.

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Abstract:
Abstract Laser Voltage Probing (LVP) is an essential Failure Analysis (FA) technique that has been widely adopted by the industry. Waveforms that are collected allow for the analyst to understand various internal failure modes related to timing or abnormal circuit behavior. As technology nodes shrink to the point where multiple transistors reside within the diffraction-limited laser spot size, interpretation of the waveforms can become extremely difficult. In this paper we discuss some of the evolving challenges faced by LVP and propose a new technique known as Differential LVP (dLVP) that can be used to debug marginal failing devices that exhibit a pass/fail boundary in their shmoo plot. We demonstrate how separate pass and fail LVP waveforms can be collected simultaneously and compared to immediately identify whether logic is corrupted and when the corruption occurs. The benefits of this new technique are many. They include guarantees of equivalent pass vs. fail data independent of crosstalk, system noise, stage drift, probe placement, temperature effects, or the diffraction-limited resolution of the probe system. Implementing dLVP into existing tools could extend their effective lifetimes and improve their efficacy related to the demands posed by the debug of 5nm technologies and smaller geometries. We anticipate that fully integrated and evolved dLVP will complement workhorse FA applications such as Laser Assisted Device Alteration (LADA) and Soft Defect Localization (SDL) analysis. Wherein those techniques map timing marginalities propagating to, and observed by, a capture flop, dLVP can extend such capabilities by identifying the first instance of corrupted logic inside the flop and map the corruption all the way to the chip output pin.
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Oliver, Lara D., Krishnendu Chakrabarty, and Hisham Z. Massoud. "Dual-threshold pass-transistor logic design." In the 19th ACM Great Lakes symposium. ACM Press, 2009. http://dx.doi.org/10.1145/1531542.1531610.

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Zhou, Hai, and Adnan Aziz. "Buffer minimization in pass transistor logic." In the 2000 international symposium. ACM Press, 2000. http://dx.doi.org/10.1145/332357.332384.

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Buch, Narayan, Newton, and Sangiovanni-Vincentelli. "Logic synthesis for large pass transistor circuits." In Proceedings of IEEE International Conference on Computer Aided Design (ICCAD). IEEE, 1997. http://dx.doi.org/10.1109/iccad.1997.643609.

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Tai-Hung Liu, M. K. Ganai, A. Aziz, and J. L. Burns. "Performance driven synthesis for pass-transistor logic." In Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013). IEEE, 1999. http://dx.doi.org/10.1109/icvd.1999.745184.

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