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1
Garg, Rajesh. "Generalized buffering of pass transistor logic (PTL) stages using Boolean division and don't cares." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5906.
Full textAbstract:
Pass Transistor Logic (PTL) is a well known approach for implementing digital circuits.
In order to handle larger designs and also to ensure that the total number of series
devices in the resulting circuit is bounded, partitioned Reduced Ordered Binary Decision
Diagrams (ROBDDs) can be used to generate the PTL circuit. The output signals of each
partitioned block typically needs to be buffered. In this thesis, a new methodology is presented
to perform generalized buffering of the outputs of PTL blocks. By performing the
Boolean division of each PTL block using different gates in a library, we select the gate
that results in the largest reduction in the height of the PTL block. In this manner, these
gates serve the function of buffering the outputs of the PTL blocks, while also reducing the
height and delay of the PTL block.
PTL synthesis with generalized buffering was implemented in two different ways. In
the first approach, Boolean division was used to perform generalized buffering. In the second
approach, compatible observability don't cares (CODCs) were utilized in tandem with
Boolean division to simplify the ROBDDs and to reduce the logic in PTL structure. Also
CODCs were computed in two different manners: one using full simplify to compute
complete CODCs and another using, approximate CODCs (ACODCs).
Over a number of examples, on an average, generalized buffering without CODCs
results in a 24% reduction in delay, and a 3% improvement in circuit area, compared to
a traditional buffered PTL implementation. When ACODCs were used, the delay was reduced by 29%, and the total area was reduced by 5% compared to traditional buffering.
With complete CODCs, the delay and area reduction compared to traditional buffering
was 28% and 6% respectively. Therefore, results show that generalized buffering provides
better implementation of the circuits than the traditional buffering method.
2
Henry, Michael B. "Emerging Power-Gating Techniques for Low Power Digital Circuits." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/29627.
Full textAbstract:
As transistor sizes scale down and levels of integration increase, leakage power has become a critical problem in modern low-power microprocessors. This is especially true for ultra-low-voltage (ULV) circuits, where high levels of leakage force designers to chose relatively high threshold voltages, which limits performance. In this thesis, an industry-standard technique known as power-gating is explored, whereby transistors are used to disconnect the power from idle portions of a chip. Present power-gating implementations suffer from limitations including non-zero off-state leakage, which can aggregate to a large amount of wasted energy during long idle periods, and high energy overhead, which limits its use to long-term system-wide sleep modes. As this thesis will show however, by vastly increasing the effectiveness of power-gating through the use of emerging technologies, and by implementing aggressive hardware-oriented power-gating policies, leakage in microprocessors can be eliminated to a large extent. This allows the threshold voltage to be lowered, leading to ULV microprocessors with both low switching energy and high performance.
The first emerging technology investigated is the Nanoelectromechnical-Systems (NEMS) switch, which is a CMOS-compatible mechanical relay with near-infinite off-resistance and low on-resistance. When used for power-gating, this switch completely eliminates off-state leakage, yet is compact enough to be contained on die. This has tremendous benefits for applications with long sleep times. For example, a NEMS-power-gated architecture performing an FFT per hour consumes 30 times less power than a transistor-power-gated architecture. Additionally, the low on-resistance can lower power-gating area overhead by 36-83\%.
The second technology targets the high energy overhead associated with powering a circuit on and off. This thesis demonstrates that a new logic style specifically designed for ULV operation, Sense Amplifier Pass Transistor Logic (SAPTL), requires power-gates that are 8-10 times smaller, and consumes up to 15 times less boot-up energy, compared to static-CMOS. These abilities enable effective power-gating of an SAPTL circuit, even for very short idle periods. Microprocessor simulations demonstrate that a fine-grained power-gating policy, along with this drastically lower overhead, can result in up to a 44\% drop in energy.
Encompassing these investigations is an energy estimation framework built around a cycle-accurate microprocessor simulator, which allows a wide range of circuit and power-gating parameters to be optimized. This framework implements two hardware-based power-gating schedulers that are completely invisible to the OS, and have extremely low hardware overhead, allowing for a large number of power-gated regions. All together, this thesis represents the most complete and forward-looking study on power-gating in the ULV region. The results demonstrate that aggressive power-gating allows designers to leverage the very low switching energy of ULV operation, while achieving performance levels that can greatly expand the capabilities of energy-constrained systems.<br>Ph. D.
3
Ragavan, Rengarajan. "Reconfigurable FSM for Ultra-Low Power Wireless Sensor Network Nodes." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100121.
Full textAbstract:
Wireless sensor networks (WSN) play an important role in today’s monitoring and controlsystems like environmental monitoring, military surveillance, industrial sensing and control, smarthome systems and tracking systems. As the application of WSN grows by leaps and bounds, there is anincreasing demand in placing a larger number of sensors and controllers to meet the requirements. Theincreased number of sensors necessitates flexibility in the functioning of nodes. Nodes in wirelesssensor networks should be capable of being dynamically reconfigured to perform various tasks is theneed of the hour.In order to achieve flexibility in node functionality, it is common to adopt reconfigurablearchitecture for WSN nodes. FPGA-based architectures are popular reconfigurable architectures bywhich WSN nodes can be programmed to take up different roles across time. Area and power are themajor overheads in FPGA based architectures, where interconnect consumes more power and area thanlogic cells. The contemporary WSN standard requires longer battery life and micro size nodes for easyplacement and maintenance-free operation for years together.Three solutions have been studied and evaluated to approach this problem: 1) Homogenousembedded FPGA platform, 2) Power gated reconfigurable finite state machines and 3) Pass transistorlogic (PTL) based reconfigurable finite state machines. Embedded FPGA is a CMOS 65nm customdeveloped small homogenous FPGA which holds the functionality of the WSN nodes and it will bedynamically reconfigured from time to time to change the functionality of the node. In Power gatedreconfigurable FSM architecture, the functionality of the node is expressed in the form of finite statemachines, which will be implemented in a LUT based power gated design. In PTL based reconfigurablefinite state machine architecture, the finite state machines are completely realized using PTL basedcustom designed sets of library components. Low power configuration memory is used to dynamicallyreconfigure the design with various FSMs at different times.
4
WANG, JIA-LONG, and 王家龍. "Area-optimal pass transistor logic minimization." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/79027637899409777660.
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5
VEN-CHIEH, HSIEH, and 謝文傑. "A New Logic Synthesis and Optimization Procedure Using Pass-Transistor Logic." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/96660896455884414515.
Full textAbstract:
碩士<br>淡江大學<br>電機工程學系<br>88<br>At logic design level, a proper choice of a circuit style for implementing combinational logic is very important. Many kinds of logic styles using pass-transistor circuit have been proposed with the objective to improve the performance of static CMOS logic. And the advantages present by pass-transistor logic have been proved in many cases from 2-input XOR gate to Multiplier. But when compares to classical NAND/NOR or some other simple logic gate, functions can be realized with better performance and smaller area by using static CMOS logic. The result a logic style may provide high performance only in some specific logic functions may confuse someone in logic style selecting. So a formulation of universal rules for optimal logic style, which provide high performance for arbitrary logic function, is needed.
Moreover, the static CMOS logic network structure can be seems as a special case of the pass-transistor logic network that pass variables are only power lines. Thus, it is possible to develop a new logic style combine the advantages of both static CMOS logic and pass-transistor logic for arbitrary logic function and high performance applications.
The objective of this work is to propose a new logic circuit synthesis and optimization procedure for arbitrary logic function implementation. Follow the synthesis and optimization procedures, a high performance new circuit which is low power consumption, low power-delay product, area efficient and high robustness against transistor downsizing and voltage scaling will produced.
6
Chen, Jian-Hung, and 陳建宏. "Low Power and High Speed Logic Synthesis with Pass Transistor Logic." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/59671970997835239984.
Full textAbstract:
碩士<br>國立中山大學<br>資訊工程學系研究所<br>89<br>In this thesis, a pass-transistor logic synthesizer is developed for logic mapping of any combinational circuits based on only two types of cells: 2-to-1 multiplexors and inverters. The input contains several sum-of-product Boolean function expressions. Our synthesizer will consider the hardware sharing among these Boolean functions in order to save area. The output of our synthesizer is pass-transistor-based circuits with optimized transistor width in terms of user-specified speed and power performance measurement. During optimization, the Elmore RC delay model is used to estimate the critical path delay and the power is characterized by the switching of all the internal nodes. The final outputs are HSPICE netlists and Verilog gate-level code that allow more detailed timing simulation and automatic placement-routing.
7
Chen, Shi Zong, and 陳世宗. "Sirup: single rail up-down pass-transistor-logic." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/65632113048817408437.
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Hsu, Chih-Cheng, and 許志成. "Automatic Optimization in Pass-Transistor-Based Logic Synthesizer." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/86877104888035726165.
Full textAbstract:
碩士<br>國立中山大學<br>資訊工程學系研究所<br>88<br>In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs little executing time for searching the best result and we can quickly gate it.
9
Teng-Yuan, Lin, and 林鼎源. "Analysis and Applications of Pass-Transistor/ CMOS Collaborated Logic." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/09404824821994602851.
Full textAbstract:
碩士<br>大同工學院<br>電機工程研究所<br>86<br>This thesis focuses on the analysis and application of PCCL. The PCCL is especially used in low-power VLSI and a universal gate. We try to implement a set of logic functions and discuss the waveforms attenuated by pass-transistors. We discuss the technique improved by inverter-restoring and the waveform can be restored to at 500 MHz operation frequency. We try to replace the level-restoring circuit of PCCL by inverter-latch one. Finally, we don't implement by BDD, but implement by AND and OR gates of convWe simulate the critical-path waveform by HSPICE. The process parameters adopt the UMC 0.5 process for education. In the fixed process, The result of power-delay-product improves to nearly 1/3 compared with CMOS logic-style in high process.
10
Cho, Hamm-Min, and 卓瀚民. "Mixing Pass-Transistor Logic with CMOS Logic for Low-Power Cell- Based Designs." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/83489899657484360995.
Full textAbstract:
碩士<br>國立中正大學<br>電機工程學系<br>86<br>Owing to the demand of the portable products small area and low-
power are the main considerations in cell-based IC design. In
this thesis we try to propose a methodology to combine pass-
transistor logic and complementary CMOS logic to reduce power
consumption. We first identify the types of logic functions
suited for each individual logic style. Then we replace certain
complementary CMOS cells in the cell library with pass-
transistor cells. The modified cell library is used in
conjunction with a logic restructuring algorithm to promote the
use of pass-transistor logic in general combinational circuit.
Empirical results using MCNC LGSynth'91 benchmark circuits show
that an average of 13.48% power reduction can be attained
through the use of the proposed method.
11
Li, Yu-Cheng, and 李育晟. "Low Power Divider Design Using Pass Transistor Logic Circuit Scheme." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/24911630754490373033.
Full textAbstract:
碩士<br>朝陽科技大學<br>資訊與通訊系<br>104<br>An increasing demand of communication mobile, the demand for larger data transmission and operation speed has grown significantly over time. It forces the system to process at a faster operation speed, and function more efficiently. However, it could translate into issues that involve higher power consumption and over-heating. As a result, suppressing and controlling the operation power at a higher operation frequency has become a crucial subject of study. Universal communication system involves high-speed dividers and it is primarily scheme in TSPC (True-Single-Phase-Clocking) and E-TSPC (Extend- True-Single-Phase). There are underlying flaws in these two scheme designs. TSPC scheme is not able to operate at high speed. On the other hand, E-TSPC scheme consumes higher power consumption at lower operation frequency due to DC power consumption problem.
In this work, we proposed a low power divider design. This design adopts Pass Transistor Logic style (PTL) scheme, it effectively lowers the circuit complexity as well as power consumption of the design and achieves better power-delay-product (PDP) performance. We also presented a novel simulation method to measure the performances of the circuits more accurately. According to the results, in comparison with the traditional TSPC and E-TSPC, the proposed method is more suitable for lower power applications. Finally, the chip measured results did claims proposed design.
12
Chien, Hung-Chun, and 簡鴻駿. "A Full Adder Realized by Bootstrapped Pass Transistor Logic Structure." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/33594552186358259766.
Full textAbstract:
碩士<br>南台科技大學<br>電子工程系<br>95<br>We use ALU broadly in VLSI such as Digital Signal Processor (DSP), Image Processor, and Microprocessor. Adder, subtractor, and multiplicer, which are included full adder, are the most common operation units in ALU. We can use software to do most calculation but not use hardware. The most basic circuit doing calculation in the computer is binary adder. For example, we can use of addition to do subtracting, continuous adding to do multiplication, and continuous subtracting to do division. Thus, adder is very important in the ALU and also can influence the performance of system.
VLSI design has already entering into a portable SOC century, so low power consumption has become an important problem. We proposed three brand new full adders which is low power and realized in Bootstrapped Pass Transistor Logic. We also design a new XOR-XNOR, used in our full adder, which can generate full swing signal at the same time.
We proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder. We also use Hspice to simulate the performance of the circuit and also tapeout our circuit in TSMC 0.35μm Mixed-Signal 2P4M Polycide 3.3/5V process. After comparing with other circuit, we can find that our circuit is low power and high speed.
13
Tsai, Cheng-Hsuan, and 蔡政軒. "Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/55551706681576129798.
Full textAbstract:
碩士<br>國立中山大學<br>資訊工程學系研究所<br>98<br>The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. The advantage of PTL is higher speed, smaller area and lower power for some particular circuits such as XOR. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this thesis, we develop a novel PTL synthesizer that can efficiently generate PTL-based circuits. We proposed a new synthesis method (hybrid PTL/CMOS Library design) that has multiple driving strengths and multiple threshold voltages to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flow employs the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS logic cells. Thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow.
14
Yang, Yuling. "Design of high performance multiple-input pass-transistor-logic XOR circuits." Thesis, 2003. http://spectrum.library.concordia.ca/2129/1/MQ77726.pdf.
Full textAbstract:
XOR gates are basic building blocks in the design of almost all kinds of digital circuits for signal processing, generation and control. The performance of the XOR gates can be a factor determining the performance of the complete circuits. In particular, XOR gates with a large number of inputs, which are often used for parallel processing, may make a major contribution to the delay of the circuits. Some reduction of the delay can be achieved but usually at the expense of the power dissipation. In this thesis, a comprehensive study of the XOR gate design is presented. Based on the study, an approach of designing multiple-input pass-transistor-logic XOR gates is proposed. This approach consists of two aspects. On one hand, the imperfect high-voltage levels, resulting from the imperfect voltage transmission by single-MOS switches, at some selected intermediated circuit nodes are used to reduce the signal swing so that the power dissipation can be minimized. On the other hand, the voltages at some circuit nodes are compensated to maximize the current capacity in order to reduce the delay. Thus, the XOR gates can be designed to have a significant higher performance, in terms of speed, than other pass-transistor-logic XOR gates and the power dissipation of the circuits can also be lowered. An example of application of this design approach is also presented in this thesis
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Chen, Dai-Yen, and 陳達彥. "Logic/Circuit Synthesizer Based on Low-Complexity Pass-Transistor Cell Library." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/15156757388339666671.
Full textAbstract:
碩士<br>國立中山大學<br>資訊工程研究所<br>87<br>In this thesis, A pass-transistor-based cell library containing four types of cells is designed and the corresponding logic/circuit synthesizer is developed for logic mapping of any combinational and dynamic circuits. There are four driven capability selects for each type of cells. The format of input is Boolean functions with expressions of sum of product and we can input several functions for hardware sharing at the same time. It provides several optional modes such as high density、high performance、dynamic logic circuit, etc. . It also does optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. Due to the small number of cells in library, it is easy to migrate to a new process technology.
16
Liu, Yi-Yu, and 劉一宇. "Low Power Driven Pass Transistor Logic Synthesis by Binary Decision Diagrams." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/11833238090918998559.
Full textAbstract:
碩士<br>國立清華大學<br>資訊工程學系<br>88<br>In this paper, we present methods to synthesize low power Pass Transistor Logic (PTL) cell. Given that the power consumption of a PTL cell includes power consumed at the gate terminal and source/drain capacitance when current flows from power/ground to output, we will translate finding a low power PTL cell to finding an OBDD with some defined cost function. This cost function includes the minimization of occurrence of variables with high transition probability and the minimization of the expected path length of an OBDD. To compute the cost function efficiently, three methods will be proposed to calculate the expected path length of Ordered Binary Decision Diagrams (OBDD).
17
Wen, Chia-Sheng, and 溫家聖. "Logic Synthesis of High-Performance Combinational Circuits Based on Pass-Transistor Cell Library." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/69965336703238055475.
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碩士<br>國立中山大學<br>資訊工程學系研究所<br>91<br>This thesis proposes a new variable-order prediction method to predict the Shannon expansion order during the BDD tree generator. Combining this method with the original minimum width method, we can generator a better BDD tree to be used in our pass-transistor logic synthesizer. Also we propose two partitioning methods to reduce the length of the critical paths. The first method can effectively reduce the critical path delay at the cost of much higher area cost. The second method explores the common factors in the Boolean functions to reduce the critical path delay with reasonably increased area cost. Furthermore, we discuss the methods of inserting regenerating inverters/buffers along the path in BDD tree by selecting inverter cells and MUX cells of proper driving strength to optimize the area/cost/power performance. Finally, the automatic layout generation is considered to produce the physical layout more efficiently compared with that using commericial automatic place-and-route tools.
18
Lu, Chih-hung, and 呂志宏. "A New Current-Sensing Complementary Pass-Transistor Logic for Low-Voltage Low-Power Applications." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/87368718272694349914.
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碩士<br>國立交通大學<br>電子研究所<br>83<br>In this thesis,we had developed a new circuit, it is called
Current-Sensing Complementary Pass-Transistor Logic(CSCPTL). By
applying the advantages of pass-transistor and the fast sensing
characteristic in low voltage swing, the proposed new circuit
has advantages on low-volateg low-power operation. As the
portable personal computer and consu,er electronic system needs
is getting critical, the new circuit has a fast operation speed
under 1.2V supply voltage with compared to the complementary
pass transistor logic(CPL), which is know to have the most
potential in low-voltage low-power digital circuit design. The
operational principles and fan-in characteristics are given and
complex logic implementation capability and low-voltage driving
ability are all given in this thesis. To be an example, the
logic synthesis of the pass-transistor logic is also given in
this thesis. To verify the circuit performance, an experimental
chip fabricated by CIC, NSC in 0.8um SPDM CMOS process has been
measured and the resulrs verifying the simulation results.
19
Liao, Yi-Yi, and 廖以義. "The Design of Low-Power Current-Sensing Complementary Pass- Transistor Logic and It's Application for Low-Voltage High-Speed Multiplier." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/03087688244714051905.
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Liow, Yu-Yee, and 廖以義. "The Design of Low-Power Current-Sensing Complementary Pass- Transistor Logic and It's Application for Low-Voltage High-Speed Multiplier." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/49651992329882673659.
Full textAbstract:
碩士<br>淡江大學<br>電機工程學系<br>84<br>Recently, power dissipation is becoming an important constraint
in portable e-lectronic systems. In this thesis, a new low-power
current-sensing complement-ary pass-transistor logic (LCSCPTL)
is proposed and analyzed. Since the curre-nt-sensing scheme can
yield a faster sensing speed under small voltage swingthan the
voltage-sensing scheme, the new logic circuit can be used in the
low-voltage low-power digital system for high speed
applications. It is shown thatthe LCSCPTL has an operation speed
about 2.2 to 2.6 times faster than the CPL,which is known to
have a great potential in low-voltage low-power digital app-
lications. Moreover,the LCSCPTL has less power dissipation than
the CPL. Thesefeatures make the LCSCPTL very promising in the
applications of low-power low-voltage high-speed applications.
The LCSCPTL can be operated at 1.2V withoutchanging the
conventional 5V CMOS process. In order to verify the new
circuitis practicable and exact.In this thesis,the LCSCPTL
circuit is applied to imp-lement an 8bit x 8bit parallel
multiplier. It uses the Baugh-Wooley algorithmto achieve 2's-
complement multiplication. It's operation voltage is at 1.2V.
The design of experimental chip is based upon the CMOS 0.8 um
SPDM process of TSMC,which is provided by the Chip
Implementation Center(CIC) of National Science Council (NSC).
The chip design, simulation, layout, verification are included.
The measurement results of the experimental chip of the LCSCPTL
logic gates and the CPL logic gates are also shown. It consists
with the simulation results.
21
Tsai, Ming-Yu, and 蔡明諭. "An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/09027930047814983581.
Full textAbstract:
博士<br>國立中山大學<br>資訊工程學系研究所<br>98<br>The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this dissertation, we develop two novel PTL synthesizers that can efficiently generate PTL-based circuits. One is based on pure PTL cells; the other mixes CMOS and PTL cells in the standard cell library to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated to design large SoC systems as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flows employ the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS cells, thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow. In this dissertation, we also discuss PTL-based designs of some fundamental hardware components. Furthermore, the proposed PTL cell library is used to synthesize large processor systems in applications of computer arithmetic and 3D graphics.