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Hu, Xuan, Amy S. Abraham, Jean Anne C. Incorvia, and Joseph S. Friedman. "Hybrid Pass Transistor Logic With Ambipolar Transistors." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 1 (2021): 301–10. http://dx.doi.org/10.1109/tcsi.2020.3034042.
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Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.
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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.
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B S, Vinayashree, and Santhosh Babu K C. "Layout Design of Row Decoder using Cadence." International Journal for Research in Applied Science and Engineering Technology 10, no. 8 (2022): 461–68. http://dx.doi.org/10.22214/ijraset.2022.46214.
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Abstract: Logic circuits, data transport circuits, and analogue to digital conversions all frequently employ decoders. For the line decoders, a mixed logic design approach incorporating transmission gate logic, pass transistor logic, and complementary metaloxide semiconductor (CMOS) technology is employed to achieve the desired performance and operation. A unique topology is proposed for the 2 to 4 decoders, which calls for a topology with fourteen transistors to reduce operating power and transistor count and a topology with fifteen transistors to achieve high power and low delay performance. For a total of four new designs, standard and inverting decoders are created for each situation. All of the suggested decoders have a low transistor count in comparison to their traditional CMOS architectures. Last but not least, a number of suggested solutions demonstrate a notable improvement in operating power and propagation latency, exceeding CMOS in virtually all instances
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Rao Tirumalasetty, Venkata, C. V. Mohan Krishna, K. Sai Sree Tanmaie, T. Lakshmi Naveena, and Ch Jonathan. "A novel design of high performance1-bit adder circuit at deep sub-micron technology." International Journal of Engineering & Technology 7, no. 1.1 (2017): 660. http://dx.doi.org/10.14419/ijet.v7i1.1.10822.
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In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.
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Yin, Ningyuan, Wanyuan Pan, Yihe Yu, Chengcheng Tang, and Zhiyi Yu. "Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier." Electronics 12, no. 15 (2023): 3209. http://dx.doi.org/10.3390/electronics12153209.
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With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.
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Pandey, Neeta, Damini Garg, Kirti Gupta, and Bharat Choudhary. "Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style." Journal of Engineering 2016 (2016): 1–10. http://dx.doi.org/10.1155/2016/8027150.
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This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.
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Chaitanya, S.* Abhishek B. S. Harshavardhan S. Karthik S. Manju T. M. "Design and Analysis of Adders Using Pass Transistor Logic for Multipliers." International Journal of Scientific Research and Technology 2, no. 5 (2025): 326–37. https://doi.org/10.5281/zenodo.15421140.
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This paper demonstrates the design and optimization of a Multiplier using pass transistor logic with half and full adders in 90 nm and 45 nm CMOS technology. The design methodology utilizes fewer transistors and low-power pass transistor logic to improve system efficiency. Implementation and simulation proved these designs to be superior than traditional CMOS designs in terms of area, delay, power dissipation, and energy efficiency. Optimized adders in the multiplier framework thus provide compact, power efficient multiplier design. A comparison to conventional designs shows significant reductions of power consumption, transistor count and delay and is therefore attractive for low-power, high-performance applications. This work contributes to VLSI design by addressing the major speed, area, and power trade-offs in digital systems. The optimized Multiplier is best suited for modern-day applications such as image and signal processing. The application area focuses on high-performance, high-energy efficiency, and clearly points out the advantages pass transistor logic can provide during digital circuit design to innovatively develop low-power, fast multipliers.
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Lamani, Deepa Suranam, and Dr H. V. Ravish Aradhya. "Design of Low Power 64-Bit Hybrid Full Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 8 (2023): 2200–2205. http://dx.doi.org/10.22214/ijraset.2023.55554.
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Abstract: In the realm of Computer Science, integrated circuits (ICs) have propelled microprocessor and digital signal processor development, hinging on the 1-bit full adder's significance for mathematical tasks. To amplify overall efficiency, enhancing this adder is pivotal. As demand surges for power-efficient devices like smartphones and MP3 players, maintaining a balance between speed, size, and power usage becomes imperative. Engineers tackle this challenge while bridging battery technology gaps. We propose advanced 1-bit full adder designs, evaluated via Cadence Virtuoso. A hybrid version merges Pass-Transistor Logic (PTL), Transmission Gates (TGs), and static CMOS logic. An optimized alternative incorporates efficient 3T-XOR logic. The comparative study considers crucial metrics: the existing FA’s 8.83µW power vs. the proposed's 8.49µW; the proposed's shorter delay of 64.53ps vs. the existing FA’s 83.1ps (18 vs. 22 transistors). At 64 bits, the existing FA’s consumes 66.8µW with a 470.94ps delay (1408 transistors), while the proposed maintains 35.05µW, 64.53ps, and fewer transistors (1152). In summary, the proposed adder excels in efficiency, delay, and transistor use for energy-efficient arithmetic operations.
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Hameed, Isam Salah, Salah Alkurwy, and Heba Hadi Ali. "Implementation of Pass Transistor Logic and C2MOS Linear Feedback Shift Register (LFSR) Circuit using FPGA and PSpice." International Journal of Electrical and Electronics Research 13, no. 1 (2025): 164–70. https://doi.org/10.37391/ijeer.130121.
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In this paper, a 4-bit Linear Feedback Shift Register (LFSR) is implemented based on a well-designed architecture combining using Pass-Transistor (PT) and Clock Complementary Metal Oxide Semiconductor (C2MOS) logic techniques. The D-flip flop registers and the XOR gates are the main parts of the propose LFSR. Number of transistors along with the speed of LFSR were positively enhanced since the exploited logic design techniques tends to blend the flavor of NMOS and PMOS devices. The PSpice and Field Programmable Gate Array (FPGA) based on Hardware Description Language (HDL) are the two different LFSR implementation environments. It has been observed that LFSR performance was effectively improved in terms of size and speed. Therefore, paper’s main aim refers to decreasing in number of transistors as well as speeding up LFSR circuit. A minimum clock time of 5ns was recorded under clearly correct LFSR output patterns. The LFSR circuit Based CMOS techniques can reduce the exploited transistors up to 43% of the conventional C2MOS logic. Besides, the number of transistors being reduced reflects the achieved circuit’s size reduction. It was concluded that paying attention to the design of the main LFSR circuit parts contributes mainly in the enhancement of the whole circuit performance.
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B., Jeevan, and Sivani K. "Heterogeneous Logic: a High Performance and Low Power Non-CMOS 4-1 Multiplexer." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2021): 3237–43. https://doi.org/10.35940/ijeat.C6201.029320.
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A novel non-CMOS 4-1 multiplexer using heterogeneous logic style is presented in this brief. The heterogeneous logic design uses the combination of three basic logic styles such as Dual Value Logic (DVL), Transmission Gate Logic (TGL) and Simple Pass Transistor Logic (SPTL). The design uses only two stacking transistors in between the supply rails. Only 16 transistors are required for the actual logic function in the proposed state-of-the-art design. Number of transistors is reduced by distinctly choosing DVL and TGL in the first stage as per the input combination. Later stage of the multiplexer is constructed using SPTL. A required logic style is chosen at first and second stage in accordance with input bit combination to minimize the number of transistors, enhance the speed of logic transition and reduce the average power dissipation. The design and simulation analysis of proposed circuit is carried out at 22nm technology using Pyxis Schematic and Pyxis Simulator. Comparison of wide-ranging simulated results of proposed design, CMOS tree multiplexer and CMOS NOR multiplexer at various supply voltages and frequencies on same technology node manifests that the performance of proposed heterogeneous multiplexer is better in terms of speed and power dissipation. At minimum possible supply voltage of 0.8V and at moderate frequency of 1GHz, the proposed multiplexer achieves, reduced power dissipation of 17.3% and reduced in delay of 9.14%. The count of transistors including inverters is also less compared to CMOS tree type and CMOS NOR type multiplexers. However, robustness of mixed logic style designs is to be improved compared to CMOS designs.
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Lu, Bin Bin, and Jian Ping Hu. "Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques." Applied Mechanics and Materials 39 (November 2010): 55–60. http://dx.doi.org/10.4028/www.scientific.net/amm.39.55.
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With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.
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Arunabala, Dr C. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed." International Journal of Innovative Technology and Exploring Engineering 10, no. 5 (2021): 87–92. http://dx.doi.org/10.35940/ijitee.e8660.0310521.
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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor count optimized such that the constraints get optimized results. By using the AND, OR, XOR, 4X1 MUX and full adder modules with reduced transistor count we designed the one bit ALU. With one bit ALU we designed 4 bit ALU and compared the outcomes with conventional 4 bit ALU design so that the proposed 4 bit ALU design has optimized transistor count, area, power, delay and power delay product (PDP). Simulations are verified through 130nm mentor graphics tool.
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Dr.C.Arunabala*, Ch.Jyothirmayi, N. S. V. Sreeja.T D, Burra Hrithika Suma, Udumula Reddy, and I.R.AnushaDevi. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 10, no. 5 (2021): 87–92. https://doi.org/10.35940/ijitee.E8660.0310521.
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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor count optimized such that the constraints get optimized results. By using the AND, OR, XOR, 4X1 MUX and full adder modules with reduced transistor count we designed the one bit ALU. With one bit ALU we designed 4 bit ALU and compared the outcomes with conventional 4 bit ALU design so that the proposed 4 bit ALU design has optimized transistor count, area, power, delay and power delay product (PDP). Simulations are verified through 130nm mentor graphics tool.
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B.Paulchamy, K.Kalpana, and J.Jaya. "An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 2605–11. https://doi.org/10.35940/ijeat.C5311.029320.
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Multiplies is an important component in Digital Signal Processing (DSP) and communication systems. It is utilized in signal and image processing applications including convolution, Fast Fourier Transform (FFT) and correlation. Therefore, it is necessary to develop a multiplier with power efficient and speed to reduce the cost of the system. Vedic multiplier has been introduced to solve the problems of existing multiplier. It is based on 16 algorithms. These algorithms use algebra, arithmetic operations and geometry. Urdhva Tiryabhyam is widely employed formula which provides high speed and efficient. Vedic multiplies generates partial sums and products in single step. It has been designed using pass transistor logic which reduces the number of components utilized to build logic gates by removing unwanted transistors. This paper design a vedic multiplier with FinFET based pass transistor logic. The developed multiplies provides better performance and suitable for high speed applications. 2x2 and 4x4 vedic multipliers are developed and executed 180nm approach with Tanner EDA Tool 3.0.
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Et.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.
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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.
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K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.
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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.
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Musala, Sarada, P. Durga Vasavi, Avireni Srinivasulu, and Cristian Ravariu. "A Novel Quaternary Half Subtractor Using 2:1 Multiplexer." International Journal of Applied Sciences & Development 4 (January 29, 2025): 1–7. https://doi.org/10.37394/232029.2025.4.1.
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Multiple-valued logic (MVL) is a logic in which there are more than two truth values. MVL is used due to difficulty in interconnection problems in binary system. Carbon nanotube field-effect transistors (CNTFET) is used to design the Quaternary Half Subtractor (QHS) circuit. Sub blocks of Module (0210), Module (1021), Module (2102), Module (3210) using three supply voltage devices and Quaternary Multiplexer 2:1 using pass transistor have designed in this paper. Therefore, compared to existing designs, less no. of transistors are needed. Comparing proposed Half subtractor using 4:1 MUX modules to current one’s reveals that the 2:1 multiplexer-based method leads in lower power usage. These proposed designs have proven to work satisfactorily under a variety of operating situations, including power, delay, and power delay product (PDP).
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Devnath, Bappy Chandra, and Satyendra N. Biswas. "Low Power Full Adder Design Using PTM Transistor Model." Carpathian Journal of Electronic and Computer Engineering 12, no. 2 (2019): 15–20. http://dx.doi.org/10.2478/cjece-2019-0011.
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Abstract At present the processing power of the digital electronic chip is enormous and that has been possible because of the continuous improvement of the design methodology and fabrication technology. So, the data processing capability of the chip is increased significantly. Data processing in the electronic chip means the arithmetic operation on that data. For that reason, ALU is present in any processor. Full adder is one of the critical components of arithmetic unit. Improvement of the full adder is necessary for improving the computational performance of a chip. In order to design an efficient full adder, designer should choose an appropriate logic style. In this research, two new model of full-adder circuits are designed and analyzed using Pass Transistor logic in order to reduce power consumption and increase operational speed. The first proposed adder consists of 8 transistors and the second one consists of 10 transistors. LTSPICE is employed for simulating the proposed circuits using16nm low power high-k strained silicon transistor model. The overall performance of the proposed adder circuits and comparative results demonstrate the superiority of the proposed model.
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Hu, Jian Ping, Xiao Ying Yu, and Xiao Lei Sheng. "An Adiabatic Register Based on Dual Threshold Leakage Reduction Technique." Advanced Materials Research 121-122 (June 2010): 148–53. http://dx.doi.org/10.4028/www.scientific.net/amr.121-122.148.
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This paper introduces a leakage reduction technique using dual threshold CMOS in CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The leakage current source of the CPAL circuits is analyzed under nanometer CMOS processes. A 32 X 32 CPAL register file is demonstrated using the proposed dual threshold technique. In the proposed register file, the logic gates on critical path use low threshold transistors, while the other logic gates use dual threshold technique to reduce their leakage dissipations. All circuits are verified using HSPICE in different processes, threshold voltages, and operation frequencies, and BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are obviously reduced both in active mode and idle mode.
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Ono, Y., H. Inokawa, and Y. Takahashi. "Binary adders of multigate single-electron transistors: specific design using pass-transistor logic." IEEE Transactions on Nanotechnology 1, no. 2 (2002): 93–99. http://dx.doi.org/10.1109/tnano.2002.804743.
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SENTHILPARI, C., K. DIWAKAR, and AJAY KUMAR SINGH. "LOW POWER, LOW LATENCY, HIGH THROUGHPUT 16-BIT CSA ADDER USING NONCLOCKED PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 18, no. 03 (2009): 581–96. http://dx.doi.org/10.1142/s0218126609005277.
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As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming major obstacles for circuit design in the nanoscale technologies. Due to increased density of transistors in integrated circuits and higher frequencies of operation, power consumption, propagation delay, PDP, and area is reaching the lower limits. We have designed 16-bit adder circuit by Carry-Select Adder (CSA) using different pass-transistor logic. The adder cells are designed by DSCH3 CAD tools and layout are generated by Microwind 3 VLSI CAD tools. Using CSA technique, the power dissipation, PDP, area, transistor count, are calculated from the layout cell of proposed 16-bit adder for Ultra Deep Submicron feature size of 120, 90, 70, and 50 nm. The UDSM signal parameters are calculated such as signal to noise ratio (SNR), energy per instruction (EPI), Latency, and throughput using layout parameter analysis of BSIM 4. The simulated results show that the CPL is dominant in terms of power dissipation, propagation delay, PDP, and area among the other pass gate logics. Our CPL circuit dominates in terms of EPI, SNR, throughput, and latency in signal parameters analysis. The proposed CPL adder circuit is compared with reported results and found that our CPL circuit gives better performance.
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Sehrawat, Arjun, Vandana Khanna, and Kushal Jindal. "Comparative Study of CMOS Logic and Modified GDI Technique for Basic Logic Gates and Code Convertor." International Journal of Advance Research and Innovation 9, no. 3 (2021): 70–85. http://dx.doi.org/10.51976/ijari.932111.
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For designing low power digital circuits with better reliability and performance along with less propagation delay, Gate Diffusion Input (GDI) is one such technique. It also significantly reduces the area and delay of a circuit. It is a low power technique which requires a smaller number of transistors to achieve desired outputs with lower design complexity as compared to CMOS logic or Pass Transistor Logic. In a basic GDI cell, 3 terminals namely Gate, Source and Drain are treated as inputs. In this work, circuits like logic gates, and Binary to Gray code convertor have been designed using CMOS logic and a Modified GDI technique. Also, the power dissipation of all these circuits have been calculated and compared for CMOS and Modified GDI. The designing and simulations have been done on Cadence Virtuoso tool in 90 nm technology and power supply voltage has been taken as 1 V.
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Rajesh, Kumar Datta. "A Pass Transistor based Multifunction Gate Design." Indian Journal of VLSI Design (IJVLSID) 3, no. 2 (2023): 5–8. https://doi.org/10.54105/ijvlsid.B1222.093223.
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This study introduces a gate design that uses pass transistor switches and enables the implementation of all necessary logic gates with a single structure. This gate design can be used for efficient circuit resizing and creating secure obfuscated circuits. This work also presents simulation results that demonstrate the effectiveness of the gate in performing various logic gate operations.
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Hu, Jian Ping, and Yu Zhang. "Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction." Advanced Materials Research 159 (December 2010): 180–85. http://dx.doi.org/10.4028/www.scientific.net/amr.159.180.
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Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. To decrease leakage power dissipations is becoming more and more important in low-power nanometer circuits. This paper proposes a gate-length biasing technique for complementary pass-transistor adiabatic logic (CPAL) circuits to reduce sub-threshold leakage dissipations. The flip-flops based on CPAL circuits with gate-length biasing techniques are presented. A traffic light controller using two-phase CPAL with gate-length biasing technique is demonstrated at 45nm CMOS process. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE. Simulation results show that the CPAL traffic light controller with the gate-length biasing technique attains 20% to 5% energy savings compared with the one using the original gate length 25MHz to 200MHz.
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Venkat, D., Tanya Mendez, Rashmi Samanth, and Subramanya G. Nayak. "Novel Design of Ripple Carry Adder using High Speed 12T Hybrid MOS Transistors." Journal of Physics: Conference Series 2571, no. 1 (2023): 012025. http://dx.doi.org/10.1088/1742-6596/2571/1/012025.
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Abstract This paper designs and extends a high speed full adder using 12 MOS Transistors to a ripple carry adder (RCA). The proposed design reduces delay and is effective for Power Delay Product (PDP). Using both complementary MOSFET (CMOS) logic and complementary pass transistor logic(CPL), a new 6T XNOR full adder(FA) is created. CPL is used in the design for Carry and Sum logic in order to minimise circuit delay. The proposed work has a delay of 11.86 ps and a PDP of 0.368fj. By using a newly proposed single bit adder, a 4-bit Ripple Carry Adder(RCA) is designed with 1.2 v supply yielding a power of 572.063uw, delay 0.32ns and PDP 183.06 fj. The outcomes obtained are compared with existing models. For characterstics of speed and PDP, the proposed model outperforms existing models significantly. The circuit was designed in 90nm GPDK technology by using the CADENCE VIRTUOSO TOOL.
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Jain, Prateek, and Amit Joshi. "Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration." Journal of Circuits, Systems and Computers 27, no. 06 (2018): 1850092. http://dx.doi.org/10.1142/s0218126618500925.
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An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.
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Rajasekhar, K., B. Sandhya, G. Srinivas, and N. Manogna. "Performance of Different Full Adder Structures for Optimized Design." International Journal of Advance Research and Innovation 8, no. 2 (2020): 74–80. http://dx.doi.org/10.51976/ijari.822013.
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Design of high performance and energy efficient digital systems are one of the most important research areas in VLSI system design which is suitable for real-time applications. One of the functional elements used in complex arithmetic circuits is an adder. To design an energy efficient adder one-bit full adder cell is designed based on adiabatic logic. The proposed ALFA cell is designed using adiabatic logic which results with the negligible amount of exchange of energy with the surrounding environment. Therefore, the application circuits based on this logic will have negligible energy loss due to heat dissipation. It requires 24 transistors to get the true and complimentary arithmetic sum and carry output. The proposed adiabatic logic based full adder (ALFA) cell processes the three single bit inputs and provides the output as sum, carry, sum bar and carry bar in a single architecture. The proposed ALFA cell reduces the power consumption by 98.49%, 90.93%, and 89.37%, respectively, when compared to CMOS full adder, 14T pass-transistor logic (PTL) with transmission gate (TG) full adder and 16T PTL with TG full adder.
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NG, K. W., and K. T. LAU. "A NOVEL ADIABATIC REGISTER FILE DESIGN." Journal of Circuits, Systems and Computers 10, no. 01n02 (2000): 67–76. http://dx.doi.org/10.1142/s0218126600000032.
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A novel 8-word × 16-bit adiabatic register file is designed. The adiabatic circuits are based on the Pass-transistor Adiabatic Logic with NMOS pull-down configuration (PAL-2N). Using adiabatic switching technique, the power consumption of the register file is significantly reduced as the energy transferred to the large capacitance buses is mostly recovered. HSPICE simulation results have shown power savings of more than 77% as compared to the conventional CMOS implementation. Although the proposed register file is designed with only one read port and one write port, multiple read and/or write ports can be easily constructed by adding additional read and/or write port transistors.
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Rajitha, J. "Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits." International Journal for Research in Applied Science and Engineering Technology 12, no. 2 (2024): 1042–48. http://dx.doi.org/10.22214/ijraset.2024.58495.
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Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.
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Neeraj, Jain, Gour Puran, and Shrman Brahmi. "A High Speed Low Power Adder in Multi Output Domino Logic." International Journal of Computer Applications 105, no. 7 (2014): 30–33. https://doi.org/10.5281/zenodo.33240.
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Speed and power is the major constraint in modern digital design so it is required to design the high speed, less number of transistors as a prime consideration. The low power carry look ahead adder using static CMOS transmission gate logic that overcomes the limitation of series connected pass transistors in the carry propagation path. In this approach it is required to find the longest critical paths in the multi-bit adders and then shortening the path to reduce the total critical path delay. The design simulation on microwind layout tool shows the worst-case delay in ns and total power consumption in microwatt range.
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YUAN, SHOUCAI, and YAMEI LIU. "DUAL THRESHOLD VOLTAGE DOMINO ADDER DESIGN WITH PASS TRANSISTOR LOGIC USING STANDBY SWITCH FOR REDUCING SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 03 (2014): 1450043. http://dx.doi.org/10.1142/s0218126614500431.
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Standby switch can strongly turn off all the high threshold voltage transistors, which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 output during its precharge phase without affecting circuits operation in its evaluation and standby phase. The required process for dual threshold voltage circuit configuration involves only one additional ion implant step to provide an extra threshold voltage. SPICE simulation for our proposed circuits is made using a 0.18 μm CMOS processes from TSMC, with 10 fF capacitive loads in all output nodes, and parameters for typical process corner at 25°C. Layout is designed, wafer is fabricate and measured. The measurement results of fabricated chips are listed and verify that our designed 8-bit carry look-ahead adders (CLAs) reduced power consumption and propagation delay time by more than 15% and around 20%, respectively, when compared with the prior work.
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Srivastava, Pawan, and Dr Ram Chandra Singh Chauhan. "Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology." Journal of University of Shanghai for Science and Technology 23, no. 11 (2021): 184–97. http://dx.doi.org/10.51201/jusst/21/10879.
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A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.
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Singamsetti, Mrudula, and Sarada Musala. "A Full swing Ex-OR/Ex-NOR Gate Circuit Using Pass Transistor Logic with Five Transistors." International Journal of Engineering Trends and Technology 11, no. 6 (2014): 277–83. http://dx.doi.org/10.14445/22315381/ijett-v11p253.
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Ganesh, Racha, K. Lal Kishore, and P. Srinivasa Rao. "Performance Analysis of Hybrid Comparator using 45nm Technology." CVR Journal of Science and Technology 25, no. 1 (2024): 15–23. http://dx.doi.org/10.32377/cvrjst2503.
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In the present real-time world, due to the improvements and innovations of System on Chip (SoC) applications, there is a requirement to integrate multiple technology design topologies. The electronic system design is classified as analog, digital, and mixed-signal design. The comparator is the major building block used in the datapath of System on Chip (SoC) application device. The usage of these devices depends on not only functionality but also on the non-functionality parameters considering different performance estimation metrics. The nonfunctional performance metrics for a transistor level design depends on the number of transistors, switching activities of logic level voltages and delay between input and outputs. These performance metrics are improved by considering the multiple logic families for multiple output generations instead of using a single logic family topology. The comparator is the major component in the arithmetic circuits for SoC applications and can be realized by using various design topologies. The vividly used topologies are Conventional CMOS logic, Pass Transistor Logic (PTL), Gate Diffusion Input (GDI) Logic, Stacking technique, Quantum-dot cellular automata, etc. The selection of the design topology for the comparator is made based on the non-functional parameters. The performance of non-functional parameters is improved by combining the topology architectures of different design techniques. In this paper, the comparator is designed using conventional CMOS logic, PTL, GDI, and a hybridized topology for best performance and the same is implemented using 45nm technology. These circuits are designed by using Cadence Virtuoso Electronic Design Automation (EDA) design tools. Non-functional performance parameters are analyzed for different topologies. Index Terms: VLSI Design, Comparator, Datapath, EDA tools, CMOS Logic, GDI Logic, PTL Logic.
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Kumar, Raushan, Sahadev Roy, and C. T. Bhunia. "Low-Power High-Speed Double Gate 1-bit Full Adder Cell." International Journal of Electronics and Telecommunications 62, no. 4 (2016): 329–34. http://dx.doi.org/10.1515/eletel-2016-0045.
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Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.
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Mathiazhagan, V., N. P. Ananthamoorthy, and C. Venkatesh. "Design and Implementation of Enhanced Edge Triggered Flip-Flop for Low Power Dissipation." Journal of Nanoelectronics and Optoelectronics 17, no. 9 (2022): 1261–73. http://dx.doi.org/10.1166/jno.2022.3291.
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Power consumption in integrated circuits is one of the prominent aspects of the design methodologies that affect cost and efficiency. It holds a prominent role in the design and fabrication of Integrated Circuits (ICs). Power consumption in ICs increases largely due to clock diffusion techniques and Flip-Flops (FFs) since they consume a huge amount of power to carry out internal transitions. Various researchers have proposed different flip-flop circuit designs for reducing power consumption in clocking systems. When integrated circuits are operating at high frequency, the clock functions are usually managed using clocked transistors. The increased number of clocked transistors increases power consumption which is a major challenge. This research aims to minimize the power consumption in flip-flops by lowering the number of clock transistors. This paper presents the design of an enhanced Dual Edge Triggered Flip-Flop (2EdTFF) based on ultra-low-power robust pass-transistor logic (PTL) for power consumption reduction. The proposed PTL-based 2EdTFF is implemented and simulated. The results of the simulation analysis show that the transistor count and layout area are reduced for minimizing power consumption. The average power utilization of the proposed approach is 3.69 μW for a power activity of 50%, 25%, and 12.5%. The power utilization of the proposed approach is reduced by 12.6% compared to TGFF, 5.5%, and 6.6% compared to S-TCRFF and TCRFF. Comparative analysis shows that the proposed approach achieves better power reduction with better D-to-Q delay and Power-Delay-Product (PDP) performance.
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Ding, Li, Zhiyong Zhang, Tian Pei, et al. "Carbon Nanotube Field-Effect Transistors for Use as Pass Transistors in Integrated Logic Gates and Full Subtractor Circuits." ACS Nano 6, no. 5 (2012): 4013–19. http://dx.doi.org/10.1021/nn300320j.
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Abdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim, and Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology." Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.
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The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.
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Murthy, G. Ramana, C. Senthilpari, P. Velrajkumar, and T. S. Lim. "Monte-Carlo Analysis of a New 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process." Applied Mechanics and Materials 284-287 (January 2013): 2580–89. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2580.
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This paper presents a 1-bit full adder by using as few as six transistors per bit in its design. It is designed with a combination of multiplexing control input and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-transistor adder cell. The design adopts Multiplexing with Control input technique to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, the proposed full adder is evaluated along with four existing full adders via extensive BSIM4 simulation. The simulation results, 180nm process models, indicate that the proposed design has lowest energy consumption per addition along with the performance edge in both speed and energy consumption makes it suitable for low power and high speed embedded processor applications.
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Senthilpari, Chinnaiyan, Rosalind Deena, and Lee Lini. "Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders." F1000Research 11 (January 5, 2022): 7. http://dx.doi.org/10.12688/f1000research.73404.1.
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Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.
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Senthilpari, Chinnaiyan, Rosalind Deena, and Lee Lini. "Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders." F1000Research 11 (November 14, 2022): 7. http://dx.doi.org/10.12688/f1000research.73404.2.
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Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.
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Kuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan, and Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques." Journal of Signal Processing 8, no. 2 (2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.
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Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.
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Sovetov, S. I., and S. F. Tyurin. "Method for synthesizing a logic element that implements several functions simultaneously." Russian Technological Journal 11, no. 3 (2023): 46–55. http://dx.doi.org/10.32362/2500-316x-2023-11-3-46-55.
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Objectives. The basic element of a field-programmable gate array is a lookup table (LUT). While in canonical normal form LUTs generally implement only one logical function for a given configuration, in this case, there is always an inactive pass transistor element. Moreover, using a single LUT for a single function reduces system-on-a-chip (SoC) scalability. Therefore, the purpose of the present work is to develop a LUT structure for implementing several logic functions simultaneously on inactive transmitting transistors.Methods. The evolution of LUT structure is presented for three variables, in which the number of simultaneously implemented functions increases. To implement additional functions, the logical device was decomposed with a different number of variables. The structures were modeled in the Multisim electrical simulation system.Results. The presented simulation of more than two logic functions on inactive parts of the LUT shows the simultaneous operation of two and four logic functions. The complexity for a different number of variables and number of implemented functions is compared.Conclusions. The simulation results demonstrate the operability of LUT structures in which several logical functions are performed. Thus, when implementing additional functions in the new structure, a smaller number of transmitting transistors is required as compared to a conventional LUT, thus increasing device functionality. The presented solution can be used to increase the number of simultaneously implemented functions of the same variables, which can be important e.g., when implementing code transformations.
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Siddaiah, Premananda Belegehalli, Sahithi Narsepalli, Sanya Mittal, and Abdur Rehman. "Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider." Journal of Electrical Engineering 74, no. 5 (2023): 403–12. http://dx.doi.org/10.2478/jee-2023-0048.
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Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.
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Charu, Smitha C., and B. Ramesh K. "Design and Development of Half Adder Using Various Technologies." Recent Trends in Analog Design and Digital Devices 4, no. 3 (2022): 1–5. https://doi.org/10.5281/zenodo.6344926.
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<em>In this paper, we will be investigating and analysing various techniques for implementing a half adder circuit with the least number of transistors. In digital electronics half adder combinational circuit used to add two numbers. It is a number arithmetic circuit that plays out the arithmetic activity of adding two single-bit words. The half adder procedure, plan of half adder utilizing AVL innovation, plan of a 3-T Half Adder, NMOS pass transistors rationale plan of half adder utilizing 2:1 MUX, half adder circuit plan with CMOS NAND gates, half adder circuit plan with CMOS transmission logic gates in cadence virtuoso. In this part, think about half adder circuit plan procedures and analyse different boundaries of half adder circuit configuration utilized different circuit plan strategies. Customary methods required less number steering assets. A 3-T half-adder circuit performs with less postponement, rapid, little format region, less power utilization and hitter productivity and exactness.</em>
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Gujjula, Ramana Reddy, Chitra Perumal, Prakash Kodali, and Bodapati Venkata Rajanna. "Design and analysis of dual-mode numerically controlled oscillators based controlled oscillator frequency modulation." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 5 (2022): 4935. http://dx.doi.org/10.11591/ijece.v12i5.pp4935-4943.
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In this paper, the design and analysis of dual-mode numerically controlled oscillators (NCO) based controlled oscillator frequency Modulation is implemented. Initially, input is given to the analog to digital (ADC) converter. This will change the input from analog to digital converter. After that, the pulse skipping mode (PSM) logic and proportional integral (PI) are applied to the converted data. After applying PSM logic, data is directly transferred to the connection block. The proportional and integral block will transfer the data will be decoded using the decoder. After decoding the values, it is saved using a modulo accumulator. After that, it is converted from one hot residue (OHR) to binary converter. The converted data is saved in the register. Now both data will pass through the gate driver circuit and output will be obtained finally. From simulation results, it can observe that the usage of metal oxide semiconductor field effect transistors (MOSFETs) and total nodes are very less in dual-mode NCO-based controlled oscillator frequency modulation.
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Wang, Xiangjing, Li Zhu, Chunsheng Chen, et al. "Freestanding multi-gate IZO-based neuromorphic transistors on composite electrolyte membranes." Flexible and Printed Electronics 6, no. 4 (2021): 044008. http://dx.doi.org/10.1088/2058-8585/ac4203.
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Abstract Brain-inspired neuromorphic computing would bring a breakthrough to the classical computing paradigm through its massive parallelism and potential low power consumption advantages. Introduction of flexibility may bring vitality to this area by expanding its application areas to such as wearable and implantable electronics. At present, the development of flexible neuromorphic devices makes it a choice with wide prospect for next-generation wearable artificial neuromorphic computing. In this study, a freestanding graphene oxide/polyvinyl alcohol composite solid electrolyte membrane is utilized as the gate dielectric and support material, and indium-zinc-oxide (IZO) neuromorphic transistors are fabricated on such membrane. Based on the in-plane gate modulation, many key synaptic plasticity behaviors have been successfully emulated, including excitatory postsynaptic current, paired-pulse facilitation, high-pass filtering, and spatiotemporal signal processing. Moreover, transition of the spiking logic and the superlinear and sublinear dendritic integration function are realized. Our results indicate that these freestanding IZO-based neuromorphic transistors may of great significance for future flexible anthropomorphic robots, wearable bionic perception.
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Ramana, Reddy Gujjula, Perumal Chitra, Kodali Prakash, and Venkata Rajanna Bodapati. "Design and analysis of dual-mode numerically controlled oscillators based controlled oscillator frequency modulation." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 5 (2022): 4935–43. https://doi.org/10.11591/ijece.v12i5.pp4935-4943.
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In this paper, the design and analysis of dual-mode numerically controlled oscillators (NCO) based controlled oscillator frequency Modulation is implemented. Initially, input is given to the analog to digital converter (ADC) converter. This will change the input from analog to digital converter. After that, the pulse skipping mode (PSM) logic and proportional integral (PI) are applied to the converted data. After applying PSM logic, data is directly transferred to the connection block. The proportional and integral block will transfer the data will be decoded using the decoder. After decoding the values, it is saved using a modulo accumulator. After that, it is converted from one hot residue (OHR) to binary converter. The converted data is saved in the register. Now both data will pass through the gate driver circuit and output will be obtained finally. From simulation results, it can observe that the usage of metal oxide semiconductor field effect transistors (MOSFETs) and total nodes are very less in dual-mode NCO-based controlled oscillator frequency modulation.
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Zhao, Yage, Zhongshan Xu, Huawei Tang, et al. "Compact Modeling of Advanced Gate-All-Around Nanosheet FETs Using Artificial Neural Network." Micromachines 15, no. 2 (2024): 218. http://dx.doi.org/10.3390/mi15020218.
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As the architecture of logic devices is evolving towards gate-all-around (GAA) structure, research efforts on advanced transistors are increasingly desired. In order to rapidly perform accurate compact modeling for these ultra-scaled transistors with the capability to cover dimensional variations, neural networks are considered. In this paper, a compact model generation methodology based on artificial neural network (ANN) is developed for GAA nanosheet FETs (NSFETs) at advanced technology nodes. The DC and AC characteristics of GAA NSFETs with various physical gate lengths (Lg), nanosheet widths (Wsh) and thicknesses (Tsh), as well as different gate voltages (Vgs) and drain voltages (Vds) are obtained through TCAD simulations. Subsequently, a high-precision ANN model architecture is evaluated. A systematical study on the impacts of ANN size, activation function, learning rate, and epoch (the times of complete pass through the entire training dataset) on the accuracy of ANN models is conducted, and a shallow neural network configuration for generating optimal ANN models is proposed. The results clearly show that the optimized ANN model can reproduce the DC and AC characteristics of NSFETs very accurately with a fitting error (MSE) of 0.01.
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Tirumalasetty, Venkata Rao, K. Babulu, and G. Appala Naidu. "Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design." WSEAS TRANSACTIONS ON SYSTEMS 23 (April 9, 2024): 141–48. http://dx.doi.org/10.37394/23202.2024.23.16.
Full textAbstract:
CNTFETs are a shows potential choice for traditional CMOS technology due to their potential for lesser power consumption and superior performance. In the present paper, a new 1-bit hybrid full adder has been deliberated and proposed using both pass transistor (PT) and transmission gate logics (TGL), which utilizes a total of 16 transistors. The combination of PT and TGL can lead to improved power efficiency, reduced delay, and enhanced circuit performance in various VLSI applications. For 0.9 V supply voltage at 32-nm CNTFET technology, the power consumption is 0.0748 μW, which is to be an exceptionally low value with a lesser delay of 7.586 Ps and the power-delay-product (PDP) of 0.5674 aJ. The results obtained from this analysis demonstrate the power efficiency, speed, and overall performance of the proposed full adder design. The combination of 32-nm CNTFET technology, deliberate circuit design choices, and the use of specific logic elements (CMOS inverters and strong transmission gates) contributes to the reported characteristics. Using a 0.9 V supply voltage and 32-nm Stanford CNTFET Model technology, the suggested 1-bit adder circuit's concert was investigated using the Mentor Graphics Tool. Finally, using the proposed 1-bit full adder circuit, an N-bit ripple carry adder (N=8, 16 & 32) is implemented and demonstrated. The Simulation results of the 8-bit RCA with a power consumption of 0.373 μW, the delay is 16.852 Ps and the PDP is 6.2857 aJ. These results show that proposed RCA’s have better performance compared to the already reported designs in terms of performance, speed, and power economy.