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Journal articles on the topic 'PCM memory'

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Published: 7 July 2024

Last updated: 7 July 2024

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Arjomand, Mohammad, Amin Jadidi, Mahmut T. Kandemir, Anand Sivasubramaniam, and Chita R. Das. "HL-PCM: MLC PCM Main Memory with Accelerated Read." IEEE Transactions on Parallel and Distributed Systems 28, no. 11 (2017): 3188–200. http://dx.doi.org/10.1109/tpds.2017.2705125.

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Priya, Bhukya Krishna, and N. Ramasubramanian. "Improving the Lifetime of Phase Change Memory by Shadow Dynamic Random Access Memory." International Journal of Service Science, Management, Engineering, and Technology 12, no. 2 (2021): 154–68. http://dx.doi.org/10.4018/ijssmet.2021030109.

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Emerging NVM are replacing the conventional memory technologies due to their huge cell density and low energy consumption. Restricted writes is one of the major drawbacks to adopt PCM memories in real-time environments. The non-uniform writes and process variations can damage the memory cell with intensive writes, as PCM memory cells are having restricted write endurance. To prolong the lifetime of a PCM, an extra DRAM shadow memory has been added to store the writes that comes to the PCM and to level out the wearing that occurs on the PCM. An extra address directory will store the address of data written to the DRAM and a counter is used to count the number of times the blocks are written into. Based upon the counter values, the data will be written from DRAM to the PCM. The data is written to the DRAM from the PCM, based on the data requirement. Experimental results show the reduction in overall writes in a PCM, which in turn improves the lifetime of a PCM by 5% with less hardware and power overhead.

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Macyna, Wojciech, and Michal Kukowski. "Adaptive Merging on Phase Change Memory." Fundamenta Informaticae 188, no. 2 (2023): 103–26. http://dx.doi.org/10.3233/fi-222144.

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Indexing is a well-known database technique used to facilitate data access and speed up query processing. Nevertheless, the construction and modification of indexes are very expensive. In traditional approaches, all records in the database table are equally covered by the index. It is not effective, since some records may be queried very often and some never. To avoid this problem, adaptive merging has been introduced. The key idea is to create an index adaptively and incrementally as a side-product of query processing. As a result, the database table is indexed partially depending on the query workload. This paper faces the problem of adaptive merging for phase change memory (PCM). The most important features of this memory type are limited write endurance and high write latency. As a consequence, adaptive merging should be investigated from the scratch. We solve this problem in two steps. First, we apply several PCM optimization techniques to the traditional adaptive merging approach. We prove that the proposed method (eAM) outperforms a traditional approach by 60%. After that, we invent the framework for adaptive merging (PAM) and propose a new variant of the PCM-optimized index. It further improves the system performance by 20% for databases where search queries interleave with data modifications.

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Jabarov, Elkhan, Byung-Won On, Gyu Choi, and Myong-Soon Park. "R-Tree for phase change memory." Computer Science and Information Systems 14, no. 2 (2017): 347–67. http://dx.doi.org/10.2298/csis160620008j.

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Nowadays, many applications use spatial data for instance-location information, so storing spatial data is important.We suggest using R -Tree over PCM. Our objective is to design a PCM-sensitive R -Tree that can store spatial data as well as improve the endurance problem. Initially, we examine how R -Tree causes endurance problems in PCM, and we then optimize it for PCM. We propose doubling the leaf node size, writing a split node to a blank node, updating parent nodes only once and not merging the nodes after deletion when the minimum fill factor requirement does not meet. Based on our experimental results while using benchmark dataset, the number of write operations to PCM in average decreased by 56 times by using the proposed R -Tree. Moreover, the proposed R -Tree scheme improves the performance in terms of processing time in average 23% compared to R -Tree.

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Hong, Jeong Beom, Young Sik Lee, Yong Wook Kim, and Tae Hee Han. "Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory." Electronics 9, no. 4 (2020): 626. http://dx.doi.org/10.3390/electronics9040626.

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Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where the reliability depends on the data pattern, a tri-level-cell (3LC) PCM has significantly higher performance and lifetime than a four-level-cell (4LC) PCM. However, a storage density is limited by binary-to-ternary data mapping. This paper introduces error-vulnerable pattern-aware binary-to-ternary data mapping utilizing 3LC PCM without an error-correction code (ECC) to enhance the storage density. To mitigate the storage density loss caused by the 3LC PCM, a two-way encoding is applied. The performance degradation is minimized through parallel encoding. The experimental results demonstrate that the proposed method improves the storage density by 17.9%. Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.

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Ding, Feilong, Baokang Peng, Xi Li, et al. "A review of compact modeling for phase change memory." Journal of Semiconductors 43, no. 2 (2022): 023101. http://dx.doi.org/10.1088/1674-4926/43/2/023101.

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Abstract Phase change memory (PCM) attracts wide attention for the memory-centric computing and neuromorphic computing. For circuit and system designs, PCM compact models are mandatory and their status are reviewed in this work. Macro models and physics-based models have been proposed in different stages of the PCM technology developments. Compact modeling of PCM is indeed more complex than the transistor modeling due to their multi-physics nature including electrical, thermal and phase transition dynamics as well as their interactions. Realizations of the PCM operations including threshold switching, set and reset programming in these models are diverse, which also differs from the perspective of circuit simulations. For the purpose of efficient and reliable designs of the PCM technology, open issues and challenges of the compact modeling are also discussed.

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Tang, Pu, Jing Xiao, and Ming Tao. "Thermal Crosstalk Analysis of Phase Change Memory Considering Thermoelectric Effect and Thermal Boundary Resistance." Journal of Physics: Conference Series 2624, no. 1 (2023): 012020. http://dx.doi.org/10.1088/1742-6596/2624/1/012020.

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Abstract Phase change memory (PCM) has emerged as a promising memory for next-generation applications due to its high-speed read and write capabilities as well as non-volatility. However, as PCM scales down to smaller feature sizes, it faces the challenge of thermal crosstalk. During the reset operation, a large amount of heat is generated and dissipated in the PCM array, potentially affecting adjacent memory cells, compromising device stability, and limiting high-density integration. To accurately investigate the thermal crosstalk in the PCM array, the conventional finite element model of the PCM array is improved by incorporating the thermoelectric effect and thermal boundary resistance. Under the 65, 45, 32, and 22-nm process nodes, the improved model reveals the occurrence of thermal crosstalk within the PCM array, whereas the conventional model is unable to detect this phenomenon at the 65-nm node. The improved model proposed in this paper incorporates more comprehensive considerations, providing a more precise analysis of the thermal crosstalk phenomenon in the PCM array, and thereby offering theoretical reference for high-density integration of the PCM.

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Stern, Keren, Yair Keller, Christopher M. Neumann, Eric Pop, and Eilam Yalon. "Temperature-dependent thermal resistance of phase change memory." Applied Physics Letters 120, no. 11 (2022): 113501. http://dx.doi.org/10.1063/5.0081016.

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One of the key challenges of phase change memory (PCM) is its high power consumption during the reset operation, when the phase change material (typically Ge2Sb2Te5, i.e., GST) heats up to ∼900 K or more in order to melt. Here, we study the temperature-dependent behavior of PCM devices by probing the reset power at ambient temperatures from 80 to 400 K. We find that different device structures exhibit contrasting temperature-dependent behavior. The reset power in our confined-type PCM is nearly unchanged with ambient temperature, corresponding to a temperature-dependent thermal resistance, whereas results for mushroom-type PCM from the literature show a linear relation between power and temperature, suggesting a more constant thermal resistance. This discrepancy is ascribed to different temperature distributions and thermal properties of the dominant components of the PCM cell thermal resistance, as shown by electro-thermal modeling. In the confined cell, the thermal boundary resistance of the GST and the thermal conductivity of the bottom electrode dominate the thermal resistance, while for the mushroom cell, the GST thermal conductivity plays a greater role. These findings can help to design more power- and energy-efficient PCM devices by better focusing thermal management efforts on the key components of the device.

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Sun, Hao, Lan Chen, Xiaoran Hao, Chenji Liu, and Mao Ni. "An Energy-Efficient and Fast Scheme for Hybrid Storage Class Memory in an AIoT Terminal System." Electronics 9, no. 6 (2020): 1013. http://dx.doi.org/10.3390/electronics9061013.

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Conventional main memory can no longer meet the requirements of low energy consumption and massive data storage in an artificial intelligence Internet of Things (AIoT) system. Moreover, the efficiency is decreased due to the swapping of data between the main memory and storage. This paper presents a hybrid storage class memory system to reduce the energy consumption and optimize IO performance. Phase change memory (PCM) brings the advantages of low static power and a large capacity to a hybrid memory system. In order to avoid the impact of poor write performance in PCM, a migration scheme implemented in the memory controller is proposed. By counting the write times and row buffer miss times in PCM simultaneously, the write-intensive data can be selected and migrated from PCM to dynamic random-access memory (DRAM) efficiently, which improves the performance of hybrid storage class memory. In addition, a fast mode with a tmpfs-based, in-memory file system is applied to hybrid storage class memory to reduce the number of data movements between memory and external storage. Experimental results show that the proposed system can reduce energy consumption by 46.2% on average compared with the traditional DRAM-only system. The fast mode increases the IO performance of the system by more than 30 times compared with the common ext3 file system.

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Shin, Dongsuk, Hakbeom Jang, Kiseok Oh, and Jae W. Lee. "An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory." ACM Transactions on Embedded Computing Systems 21, no. 1 (2022): 1–22. http://dx.doi.org/10.1145/3451995.

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A long battery life is a first-class design objective for mobile devices, and main memory accounts for a major portion of total energy consumption. Moreover, the energy consumption from memory is expected to increase further with ever-growing demands for bandwidth and capacity. A hybrid memory system with both DRAM and PCM can be an attractive solution to provide additional capacity and reduce standby energy. Although providing much greater density than DRAM, PCM has longer access latency and limited write endurance to make it challenging to architect it for main memory. To address this challenge, this article introduces CAMP, a novel DRAM c ache a rchitecture for m obile platforms with P CM-based main memory. A DRAM cache in this environment is required to filter most of the writes to PCM to increase its lifetime, and deliver highest efficiency even for a relatively small-sized DRAM cache that mobile platforms can afford. To address this CAMP divides DRAM space into two regions: a page cache for exploiting spatial locality in a bandwidth-efficient manner and a dirty block buffer for maximally filtering writes. CAMP improves the performance and energy-delay-product by 29.2% and 45.2%, respectively, over the baseline PCM-oblivious DRAM cache, while increasing PCM lifetime by 2.7×. And CAMP also improves the performance and energy-delay-product by 29.3% and 41.5%, respectively, over the state-of-the-art design with dirty block buffer, while increasing PCM lifetime by 2.5×.

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Ho, Chien-Chung, Yu-Ming Chang, Yuan-Hao Chang, Hsiu-Chang Chen, and Tei-Wei Kuo. "Write-aware memory management for hybrid SLC-MLC PCM memory systems." ACM SIGAPP Applied Computing Review 17, no. 2 (2017): 16–26. http://dx.doi.org/10.1145/3131080.3131082.

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Hong, Feng, Jianquan Zhang, Shigui Qi, and Zheng Li. "PCM-2R: Accelerating MLC PCM Writes via Data Reshaping and Remapping." Mobile Information Systems 2022 (July 16, 2022): 1–19. http://dx.doi.org/10.1155/2022/9552517.

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Multilevel cell (MLC) phase change memory (PCM) shows great potential in terms of capacity and cost compared with single-level cell (SLC) PCM by storing multiple bits in one physical PCM cell. However, poor write performance is a huge challenge for MLC PCM. In general, write latency of MLC PCM is 10 to 100X longer compared with DRAM technology. Considerable write latency greatly degrades the overall system performance and restricts the application of MLC PCM. Actually, several chips compose a memory DIMM to match the wide interface of data bus. The data of a write request, i.e., a cache line block, are distributed to multiple PCM chips. As a result, the write service time is determined by the chips with the most data amount. Conventional PCM write schemes do not care for the modified-byte distribution among PCM chips and it just waits for the completion of the chip with the most amount of data. However, it is observed that (1) the conventional PCM write scheme suffers from unbalanced modified-byte distribution that some PCM chips bear too many modified bytes while some chips are kept idle for long times. (2) The modified-byte distribution shows some unique patterns that some bytes are changed more frequently compared with others. (3) MLC PCM shows significant asymmetry considering only MSB or LSB transitions. Based on these observations, in order to solve the poor write problem of PCM, this article presents a novel PCM write scheme called PCM-2R. The key ideas behind our proposed scheme are to reshape the data to evenly distribute the cache line blocks among all chips based on their modified-byte distribution pattern to avoid unbalanced distribution and then remap modified bytes to fast region after decoupling MLC PCM cells considering the state transition asymmetries. The evaluation results show that PCM-2R achieves 51% read latency reduction, 37% write latency reduction, 1.9X IPC improvement, 41% running time reduction, 2.2X throughout improvement, and 52% energy reduction compared with the baseline. Moreover, compared with the state-of-the-art write schemes, PCM-2R achieves 0.2X more IPC improvement and 0.2X throughout improvement.

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Ding, Feilong, Deqi Dong, Yihan Chen, Xinnan Lin, and Lining Zhang. "Robust Simulations of Nanoscale Phase Change Memory: Dynamics and Retention." Nanomaterials 11, no. 11 (2021): 2945. http://dx.doi.org/10.3390/nano11112945.

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A robust simulation framework was developed for nanoscale phase change memory (PCM) cells. Starting from the reaction rate theory, the dynamic nucleation was simulated to capture the evolution of the cluster population. To accommodate the non-uniform critical sizes of nuclei due to the non-isothermal conditions during PCM cell programming, an improved crystallization model was proposed that goes beyond the classical nucleation and growth model. With the above, the incubation period in which the cluster distributions reached their equilibrium was captured beyond the capability of simulations with a steady-state nucleation rate. The implications of the developed simulation method are discussed regarding PCM fast SET programming and retention. This work provides the possibility for further improvement of PCM and integration with CMOS technology.

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Antolini, Alessio, Eleonora Franchi Scarselli, Antonio Gnudi, et al. "Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing." Materials 14, no. 7 (2021): 1624. http://dx.doi.org/10.3390/ma14071624.

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In this paper, a thorough characterization of phase-change memory (PCM) cells was carried out, aimed at evaluating and optimizing their performance as enabling devices for analog in-memory computing (AIMC) applications. Exploiting the features of programming pulses, we discuss strategies to reduce undesired phenomena that afflict PCM cells and are particularly harmful in analog computations, such as low-frequency noise, time drift, and cell-to-cell variability of the conductance. The test vehicle is an embedded PCM (ePCM) provided by STMicroelectronics and designed in 90-nm smart power BCD technology with a Ge-rich Ge-Sb-Te (GST) alloy for automotive applications. On the basis of the results of the characterization of a large number of cells, we propose an iterative algorithm to allow multi-level cell conductance programming, and its performances for AIMC applications are discussed. Results for a group of 512 cells programmed with four different conductance levels are presented, showing an initial conductance spread under 6%, relative current noise less than 9% in most cases, and a relative conductance drift of 15% in the worst case after 14 h from the application of the programming sequence.

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Arjomand, Mohammad, Mahmut T. Kandemir, Anand Sivasubramaniam, and Chita R. Das. "Boosting access parallelism to PCM-based main memory." ACM SIGARCH Computer Architecture News 44, no. 3 (2016): 695–706. http://dx.doi.org/10.1145/3007787.3001211.

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Lee, Jung-Hoon. "PCM Main Memory for Low Power Embedded System." IEMEK Journal of Embedded Systems and Applications 10, no. 6 (2015): 391–97. http://dx.doi.org/10.14372/iemek.2015.10.6.391.

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Jung, Bo-Sung, and Jung-Hoon Lee. "High Performance PCM&DRAM Hybrid Memory System." IEMEK Journal of Embedded Systems and Applications 11, no. 2 (2016): 117–23. http://dx.doi.org/10.14372/iemek.2016.11.2.117.

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HARNSOONGNOEN, SANCHAI, CHIRANUT SA-NGIAMSAK, and APIRAT SIRITARATIWAT. "OPTIMIZATION OF PHASE CHANGE MEMORY WITH THIN METAL INSERTED LAYER ON MATERIAL PROPERTIES." International Journal of Modern Physics B 23, no. 17 (2009): 3625–30. http://dx.doi.org/10.1142/s0217979209063080.

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This works reports, for the first time, the thorough study and optimisation of Phase Change Memory (PCM) structure with thin metal inserted chalcogenide via electrical resistivity (ρ) using finite element modeling. PCM is one of the best candidates for next generation non-volatile memory. It has received much attention recently due to its fast write speed, non-destructive readout, superb scalability, and great compatibility with current silicon-based mass fabrication. The setback of PCM is a high reset current typically higher than 1mA based on 180nm lithography. To reduce the reset current and to solve the over-programming failure, PCM with thin metal inserted chalcogenide (bottom chalcogenide/metal inserted/top chalcogenide) structure has been proposed. Nevertheless, reports on optimisation of the electrical resistivity using the finite element method for this new PCM structure have never been published. This work aims to minimize the reset current of this PCM structure by optimizing the level of the electrical resistivity of the PCM profile using the finite element approach. This work clearly shows that PCM characteristics are strongly affected by the electrical resistivity. The 2-D simulation results reveal clearly that the best thermal transfer of and self-joule-heating at the bottom chalcogenide layer can be achieved under conditions; ρ_bottom chalcogenide > ρ_metal inserted > ρ_top chalcogenide More specifically, the optimized electrical resistivity of PCMTMI is attained with ρ_top chalcogenide: ρ_metal inserted: ρ_bottom chalcogenide ratio of 1:6:16 when ρ_top chalcogenide is 10-3 Ωm. In conclusion, high energy efficiency can be obtained with the reset current as low as 0.3mA and with high speed operation of less than 30ns.

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Priya, Bhukya Krishna, and N. Ramasubramanian. "Enhancing the Lifetime of a Phase Change Memory with Bit-Flip Reversal." Journal of Circuits, Systems and Computers 29, no. 14 (2020): 2050219. http://dx.doi.org/10.1142/s0218126620502199.

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Phase Change Memory (PCM) has evolved as a promising alternative over Dynamic Random Access Memory (DRAM) in terms of cell density and leakage power. While non-volatility is a desirable feature, it gives rise to the possibility of the data being present even after the power is switched off. To secure the data, encryption is normally done by using the standard Advanced Encryption Standard (AES) algorithm. Encrypting the data results in huge number of bit-flips, which reduces the lifetime of a PCM. The proposed method increases the lifetime of PCM by reducing the number of bit-flips occurred due to the encryption of modified words only and leaving the unmodified words as they are. The generated encrypted text, which is written by using the bit-flips reversal method, reduces the number of cells involved in writing by approximately 25%. This method is implemented by using Gem5 simulator and is evaluated with splash2 benchmark suite. It is observed that the proposed method improves the lifetime of a PCM memory by 15% without consuming extra power.

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Akbarzadeh, Negar, Sina Darabi, Atiyeh Gheibi-Fetrat, Amir Mirzaei, Mohammad Sadrosadati, and Hamid Sarbazi-Azad. "H3DM: A High-bandwidth High-capacity Hybrid 3D Memory Design for GPUs." Proceedings of the ACM on Measurement and Analysis of Computing Systems 8, no. 1 (2024): 1–28. http://dx.doi.org/10.1145/3639038.

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Graphics Processing Units (GPUs) are widely used for modern applications with huge data sizes. However, the performance benefit of GPUs is limited by their memory capacity and bandwidth. Although GPU vendors improve memory capacity and bandwidth using 3D memory technology (HBM), many important workloads with terabytes of data still cannot fit in the provided capacity and are bound by the provided bandwidth. With a limited GPU memory capacity, programmers should handle the data movement between GPU and host memories by themselves, causing a significant programming burden. To improve programming ease, GPUs use a unified address space with the host that allows over-subscribing GPU memory, but this approach is not effective in terms of performance once GPUs encounter memory page faults. Many recent works have tried to remedy capacity and bandwidth bottlenecks using dense non-volatile memories (NVMs) and true-3D stacking. However, these works mainly focus on one bottleneck or do not provide a scalable solution that fits future requirements. In this paper, we investigate true-3D stacking of dense, low-power, and refresh-free non-volatile phase change memory (PCM) on top of state-of-the-art GPU configurations to provide higher capacity and bandwidth within the available area and power budget. The higher density and lower power consumption of PCM provide higher capacity through integrating more cells in each 3D layer and enabling stacking more layers. However, we observe that stacking more than six layers of pure-PCM memory violates the thermal constraint and severely harms the performance and power efficiency due to its higher write latency and energy. Further, it degrades the lifetime of GPU to less than one year. Utilizing a hybrid architecture that leverages the benefits of both DRAM and PCM memories has been widely studied by prior proposals; however, true-3D integration of such a hybrid memory architecture especially on top of state-of-the-art powerful GPU architecture has not been investigated yet. We experimentally demonstrate that by covering 80% of write requests in DRAM and eliminating refresh overhead, true-3D stacking of eight 32GB layers of PCM along with two 8GB layers of DRAM is possible resulting in a total of 272GB memory capacity. Based on the explored design requirements, We propose a 3D high-bandwidth high-capacity hybrid memory (H3DM) system utilizing a hybrid-3D (H3D)-aware remapping scheme to reduce expensive PCM writes to under 20% while avoiding DRAM refresh overhead. H3DM improves the performance up to 291% compared to the baseline GPU architecture while remaining within only 3% of an ideal case with DRAM-like access latency, on average. Moreover, by increasing the dataset size above the baseline GPU memory space, H3DM improves performance and power up to 648% and 87% compared to the baseline GPU architecture since it avoids expensive data transfers through off-chip communication links.

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Mohseni, Milad, Ahmed Alkhayyat, P. Balaji Srikaanth, et al. "Analyzing Characteristics for Two-Step SET Operation Scheme for Improving Write Time in Nanoscale Phase-Change Memory (PCM)." Journal of Nanomaterials 2022 (September 9, 2022): 1–20. http://dx.doi.org/10.1155/2022/6822884.

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PCM (phase-change memory) is a memory innovation that has gained prominence as a capacity-class memory for computer systems. It is made up of a tiny functional amount of phase-change material that is located in the middle of two electrodes. In PCM, data is kept by utilizing the difference in electrical resistance between a crystalline phase, which has a high resistance, and its amorphous phase, which has a low resistance. Using electrical pulses, the phase-change material would be shifted from a high to the low conductive region and conversely. However, the device’s material science concerned with PCM has been generally studied, and questions remain regarding their electrical, warm, and fundamental aspects since its publication in the 1960s. One major downside of PCM is its low heat conductivity, which causes delays in the energy charging/discharging procedure and hardware efficiency. As a result of this, one of the primary focuses of PCM studies has been the improvement of PCM’s heat conductivity through the utilization of nanotechnology and nanomaterials. Nanotechnology has been developing ultrasmall nanoparticles to improve traditional PCMs’ thermophysical characteristics. These nanomaterials, such as metal, metal oxide, and carbon, will significantly boost PCM’s thermal properties, including supercooling, viscosity, and heat capacity. An overview of PCM devices is presented in this article, which underlies perusing and composition activities. Consequently, we offered novel PCM devices and materials. Therefore, the total study is qualitative, and no machine learning approach is used. Because of this, we cannot say that the data is quantitative. Our work includes both test representations of the specific features observed in nanoscale PCM devices and material science demonstrations. In the end, we provide a point of view on some remaining open inquiries and possible future exploration directions.

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Lewis, Matthew, and Lucien N. Brush. "Impact of solid–liquid interfacial thermodynamics on phase-change memory RESET scaling." Nanotechnology 33, no. 20 (2022): 205204. http://dx.doi.org/10.1088/1361-6528/ac512c.

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Abstract A model of the RESET melting process in conventional phase-change memory (PCM) devices is constructed in which the Gibbs–Thomson (GT) effect, representing local equilibrium at the solid–liquid interface, is included as an interfacial condition for the electro-thermal model of the PCM device. A comparison is made between the GT model and a commonly used model in which the interfacial temperature is fixed at the bulk melting temperature of the PCM material. The model is applied to conventional PCM designs in which a dome-shaped liquid/amorphous region is formed. Two families of solutions are computed representing steady state liquid regions, distinguished by their thermodynamic aspects. There is a family of solutions representing a hypothetical liquid nucleation process, and a family of larger steady-state liquid solutions representing the limit of the melting process. These ‘melting limits’ enable calculation of minima in voltage and corresponding current required for the RESET process. In this PCM configuration, the GT effect constrains the equilibrium solid–liquid interface temperature to remain above the bulk melting temperature during melting. The magnitude of this temperature difference increases with decreasing device size scale, thus requiring an increase in the required voltage and current needed for RESET compared to the case in which the interface temperature is approximated by the bulk melting temperature. This increase becomes substantial for active device dimensions in the <20 nm range. The impact of this phenomena on PCM device design is discussed.

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Lei, Xin-Qing, Jia-He Zhu, Da-Wei Wang, and Wen-Sheng Zhao. "Design for Ultrahigh-Density Vertical Phase Change Memory: Proposal and Numerical Investigation." Electronics 11, no. 12 (2022): 1822. http://dx.doi.org/10.3390/electronics11121822.

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The integration level is a significant index that can be used to characterize the performance of non-volatile memory devices. This paper proposes innovative design schemes for high-density integrated phase change memory (PCM). In these schemes, diploid and four-fold memory units, which are composed of nano-strip film GST-based memory cells, are employed to replace the memory unit of a conventional vertical PCM array. As the phase transformation process of the phase change material involves the coupling of electrical and thermal processes, an in-house electrothermal coupling simulator is developed to analyze the performance of the proposed memory cells and arrays. In the simulator, a proven mathematical model is used to describe the phase change mechanism, with a finite element approach implemented for numerical calculations. The characteristics of the GST-strip-based memory cell are simulated first and compared with a conventional vertical cell, with a decrease of 32% in the reset current amplitude achieved. Next, the influences of geometric parameters on the characteristics of memory cell are investigated systematically. After this, the electrothermal characteristics of the proposed vertical PCM arrays are simulated and the results indicate that they possess both excellent performance and scalability. At last, the integration densities of the proposed design schemes are compared with the reference array, with a maximum time of 5.94 achieved.

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Gonzalez-Alberquilla, Rodrigo, Fernando Castro, Luis Pinuel, and Francisco Tirado. "CEPRAM: Compression for Endurance in PCM RAM." Journal of Circuits, Systems and Computers 26, no. 11 (2017): 1750167. http://dx.doi.org/10.1142/s0218126617501675.

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We deal with the endurance problem of Phase Change Memories (PCM) by proposing Compression for Endurance in PCM RAM [Formula: see text]CEPRAM[Formula: see text], a technique to elongate the lifespan of PCM-based main memory through compression. We introduce a total of three compression schemes based on already existent schemes, but targeting compression for PCM-based systems. We do a two-level evaluation. First, we quantify the performance of the compression, in terms of compressed size, bit-flips and how they are affected by errors. Next, we simulate these parameters in a statistical simulator to study how they affect the endurance of the system. Our simulation results reveal that our technique, which is built on top of Error Correcting Pointers (ECP) but using a high-performance cache-oriented compression algorithm modified to better suit our purpose, manages to further extend the lifetime of the memory system. In particular, it guarantees that at least half of the physical pages are in usable condition for 25% longer than ECP, which is slightly more than 5% more than a scheme that can correct 16 failures per block.

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Qiao, Yang, Jin Zhao, Haodong Sun, et al. "Pt Modified Sb2Te3 Alloy Ensuring High−Performance Phase Change Memory." Nanomaterials 12, no. 12 (2022): 1996. http://dx.doi.org/10.3390/nano12121996.

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Phase change memory (PCM), due to the advantages in capacity and endurance, has the opportunity to become the next generation of general−purpose memory. However, operation speed and data retention are still bottlenecks for PCM development. The most direct way to solve this problem is to find a material with high speed and good thermal stability. In this paper, platinum doping is proposed to improve performance. The 10-year data retention temperature of the doped material is up to 104 °C; the device achieves an operation speed of 6 ns and more than 3 × 105 operation cycles. An excellent performance was derived from the reduced grain size (10 nm) and the smaller density change rate (4.76%), which are less than those of Ge2Sb2Te5 (GST) and Sb2Te3. Hence, platinum doping is an effective approach to improve the performance of PCM and provide both good thermal stability and high operation speed.

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Zhang, Zhong Hua, San Nian Song, Zhi Tang Song, et al. "Performance Improvement of Phase Change Memory Cell by Using a Tantalum Pentoxide Buffer Layer." Materials Science Forum 848 (March 2016): 425–29. http://dx.doi.org/10.4028/www.scientific.net/msf.848.425.

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The performance of phase change memory (PCM) cell, based on Ti0.5Sb2Te3, was significantly improved by using a tantalum dioxide buffer layer. The presence of a buffer layer reduced the reset voltage of the PCM cell. The theoretical thermal simulation and calculation for the reset process were conducted to analyze the thermal effect of the titanium dioxide heating layer. The improved performance of the PCM cell with dioxide clad layer can be attributed to the fact that the buffer layer not only acted as heating layer but also efficiently reduced the cell dissipated power.

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Song, Zhitang, Daolin Cai, Yan Cheng, et al. "12-state multi-level cell storage implemented in a 128 Mb phase change memory chip." Nanoscale 13, no. 23 (2021): 10455–61. http://dx.doi.org/10.1039/d1nr00100k.

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Yin, You, and Sumio Hosaka. "Crystal Growth Suppression by N-Doping into Chalcogenide for Application to Next-Generation Phase Change Memory." Key Engineering Materials 497 (December 2011): 101–5. http://dx.doi.org/10.4028/www.scientific.net/kem.497.101.

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In this work, we investigate the effect of the N-doping on microstructure and electrical properties of chalcogenide Ge2Sb2Te5(GST) films for application to multilevel-storage phase change memory (PCM). Crystal size can be markedly reduced from 16 nm to 5 nm by N-doping into GST. The crystal growth suppression is believed to be controlled by distributed fine nitride particles. The resistivity of N-GST as a function of annealing temperature exhibits a gradual change due to the crystal growth suppression. The characteristics imply that N-GST is suitable for application to multilevel-storage PCM as the next-generation nonvolatile memory.

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Kim, Jeong-Geun, Shin-Dug Kim, and Su-Kyung Yoon. "Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System." Electronics 9, no. 12 (2020): 2158. http://dx.doi.org/10.3390/electronics9122158.

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This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement.

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Yun, Ji-Tae, Su-Kyung Yoon, Jeong-Geun Kim, Bernd Burgstaller, and Shin-Dug Kim. "Regression Prefetcher with Preprocessing for DRAM-PCM Hybrid Main Memory." IEEE Computer Architecture Letters 17, no. 2 (2018): 163–66. http://dx.doi.org/10.1109/lca.2018.2841835.

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Pourshirazi, Bahareh, Majed Valad Beigi, Zhichun Zhu, and Gokhan Memik. "Writeback-Aware LLC Management for PCM-Based Main Memory Systems." ACM Transactions on Design Automation of Electronic Systems 24, no. 2 (2019): 1–19. http://dx.doi.org/10.1145/3292009.

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Yoon, Su-Kyung, Jitae Yun, Jung-Geun Kim, and Shin-Dug Kim. "Self-Adaptive Filtering Algorithm with PCM-Based Memory Storage System." ACM Transactions on Embedded Computing Systems 17, no. 3 (2018): 1–23. http://dx.doi.org/10.1145/3190856.

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El-Hassan, Nemat H., Nandha Thulasiraman Kumar, and Haider Abbas F. Almurib. "Modelling of wire resistance effect in PCM-based nanocrossbar memory." Journal of Engineering 2016, no. 10 (2016): 357–62. http://dx.doi.org/10.1049/joe.2016.0212.

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Meng, Yingjie, Yimin Chen, Kexin Peng, et al. "GeTe ultrathin film based phase-change memory with extreme thermal stability, fast SET speed, and low RESET power energy." AIP Advances 13, no. 3 (2023): 035205. http://dx.doi.org/10.1063/5.0138286.

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We designed the phase-change memory (PCM) cell based on ultrathin GeTe film (∼10 nm) and homemade nanoscale electrode filling craft to improve data retention ability and reduce programming energy, respectively. It was found that the temperature for ten years’ data retention of this ultrathin GeTe film is 160 ± 32.8 °C, which is much higher than that of conventional Ge2Sb2Te5 (GST, 83 ± 20.6 °C) film. Benefit to the nature of fragile-to-strong crossover behavior in GeTe supercooled liquids that was confined in a two-dimension structure, a fast SET speed of 6 ns is also detected in this ultrathin GeTe PCM. Moreover, the RESET power consumption of this ultrathin GeTe PCM is measured as 1.8 ± 0.5 nJ, and it is much lower than that of GST PCM (16.5 ± 1.5 nJ), which is attributed to the nanoscale electrode of the devices. The above-mentioned improvements enable the application of ultrathin GeTe PCM in neuromorphic computing.

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Xu, Zhehao, Xiao Su, Sicong Hua, Jiwei Zhai, Sannian Song, and Zhitang Song. "Non-volatile multi-level cell storage via sequential phase transition in Sb₇Te₃/GeSb₆Te multilayer thin film." Nanotechnology 33, no. 7 (2021): 075701. http://dx.doi.org/10.1088/1361-6528/ac3613.

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Abstract For high-performance data centers, huge data transfer, reliable data storage and emerging in-memory computing require memory technology with the combination of accelerated access, large capacity and persistence. As for phase-change memory, the Sb-rich compounds Sb7Te3 and GeSb6Te have demonstrated fast switching speed and considerable difference of phase transition temperature. A multilayer structure is built up with the two compounds to reach three non-volatile resistance states. Sequential phase transition in a relationship with the temperature is confirmed to contribute to different resistance states with sufficient thermal stability. With the verification of nanoscale confinement for the integration of Sb7Te3/GeSb6Te multilayer thin film, T-shape PCM cells are fabricated and two SET operations are executed with 40 ns-width pulses, exhibiting good potential for the multi-level PCM candidate.

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Gafner, Yuri Ya, Svetlana L. Gafner, and Daria A. Ryzhkova. "Estimating Ag-Cu Nanoalloy Applicability for PCM Data Recording." Solid State Phenomena 310 (September 2020): 47–52. http://dx.doi.org/10.4028/www.scientific.net/ssp.310.47.

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The paper studies applicability of individual particles of Ag-Cu nanoalloys as data bits in the next generation memory devices constructed on the phase change memory principle. To fulfill this task, the structure formation was simulated with the molecular dynamics method on cooling from the melt of Ag-Cu nanoparticles of the diameter of 2.0 – 8.0 nm of different chemical compositions (with copper content in the alloy from 10 to 50 percent), based on the modified tight-binding potential (TB-SMA). The authors investigated the influence of the size effects and the heat removal rate on the formation of the clusters structure. The investigation showed that different internal structures can be developed upon cooling from the liquid phase, so there were determined some criteria of their stability. Clusters with copper content of not more than 10% and diameters of more than 6.0 nm were isolated from the entire set of the considered particles.

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Yin, You, Rosalena Irma Alip, Yu Long Zhang, Ryota Kobayashi, and Sumio Hosaka. "Multi-Level Storage in Lateral Phase Change Memory: From 3 to 16 Resistance Levels." Key Engineering Materials 534 (January 2013): 131–35. http://dx.doi.org/10.4028/www.scientific.net/kem.534.131.

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Here, we report multi-level storage (MLS) in multi-layer (ML) and single-layer (SL) phase change memories (PCM). For the former ML-PCM device, the active medium with two layers of chalcogenide consists of a top 30 nm TiN/180 nm SbTeN/20 nm TiN/bottom 120 nm SbTeN stacked multi-layer. Three stable and distinct resistance states are demonstrated in both static and dynamic switching characteristics of the multi-layer devices. For the latter SL-PCM device, the active medium with only one layer of chalcogenide consists of a top 50 nm TiN/150 nm SbTeN. We demonstrate that the number of distinguishable resistance levels can readily reach 16 and even higher. These levels in this study result from the initial threshold switching and the subsequent current-controlled crystallization induced by Joule heating. Therefore, the latter memory allows the creation of many distinct levels, thus enabling the low-cost ultra-high-density non-volatile memory.

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Nguyen, Huu Tan, Andrzej Kusiak, Jean Luc Battaglia, et al. "Thermal Properties of In-Sb-Te Thin Films for Phase Change Memory Application." Advances in Science and Technology 95 (October 2014): 113–19. http://dx.doi.org/10.4028/www.scientific.net/ast.95.113.

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Phase change memories (PCM) are typically based on compounds of the Ge-Sb-Te (GST) ternary system. Nevertheless, a major drawback of PCM devices based on GST is the low crystallization temperature, which prevents the fulfillment of automotive-level or military-grade requirements (125°C continuous operation). To overcome this limitation, alloys belonging to the In-Sb-Te (IST) system have been proposed, which have demonstrated high crystallization temperature, and fast switching. Thermal properties of the chalcogenide alloy and of its interfaces within the PCM cell are key parameters versus the programming current, reliability and optimized scaling of PCM devices. The Modulated Photothermal Radiometry (MPTR) technique was implemented to measure the thermal conductivity of IST thin films as well as the thermal boundary resistance at the interface with other surrounding materials (a metal and a dielectric). The experiment was carried outin situfrom room temperature up to 550°C in order to investigate the intrinsic thermal properties at different temperatures and the significant structural rearrangement upon the phase transition. Two different stoichiometries for the IST ternary alloy were deposited by Metal Organic Chemical Vapor Deposition (MOCVD) on a Si substrate covered with thermal SiO2and then capped with a Platinum layer that acts as an optical and thermal transducer. Additional data from Raman and XRD lead to complementary analysis.

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Liu, Guang Yu, Liang Cai Wu, Zhi Tang Song, Feng Rao, San Nian Song, and Yan Cheng. "Stability of Sb₂Te Crystalline Films for Phase Change Memory." Materials Science Forum 898 (June 2017): 1829–33. http://dx.doi.org/10.4028/www.scientific.net/msf.898.1829.

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Stability is one of the most important criterions to judge the quality of products, especially for the phase-change memory (PCM), which is regarded as the most promising candidate for next-generation non-volatile memory. Due to the lack of resistance stability, read errors can occur easily and the reliability of PCM will be influenced. Using Sb2Te as a base material, the resistance stability of Sb2Te was studied, and the results indicated that in the whole cooling process, the resistance of Sb2Te crystalline film was extremely steady under different annealing temperatures and different cooling rates. To unravel the reason why the resistance of Sb2Te crystalline film has good stability, further study was carried out and the results showed that there was no new diffraction peak in the XRD pattern, and the HRTEM images showed the similar hexagonal phase for the films under different annealing temperatures. Moreover, it was observed that the resistance in Sb2Te-based PCM device was still stable for crystalline state and amorphous state. These results revealed that the stability of Sb2Te crystalline films at a micro level and the stability of microscopic structure resulted in the stability of resistance. Therefore, based on the present study, the stability of phase-change material Sb2Te can be applied to exploit more reliable PCM for near-future application.

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Yin, You, and Sumio Hosaka. "Proposed Phase-Change Memory with a Step-Like Channel for High-Performance Multi-State Storage." Key Engineering Materials 459 (December 2010): 145–50. http://dx.doi.org/10.4028/www.scientific.net/kem.459.145.

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Lateral rectangular (R-) and step-like (S-) channel phase-change memory (PCM) cell structures are numerically analyzed for multi-state storage based on their temperature distributions and their programming characteristics. The S-PCM cell is characterized by the sequentially melted sub-channel and step-like programming characteristics. From the viewpoint of the performance for multi-state storage, the step-like characteristics indicate high controllability for its application of multi-state storage.

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Lin, Shu-Yen, and Shao-Cheng Wang. "Thermal-constrained memory management for three-dimensional DRAM-PCM memory with deep neural network applications." Microprocessors and Microsystems 89 (March 2022): 104444. http://dx.doi.org/10.1016/j.micpro.2022.104444.

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Grimonia, E., M. R. C. Andhika, M. F. N. Aulady, R. V. C. Rubi, and N. L. Hamidah. "Thermal Management System Using Phase Change Material for Lithium-ion Battery." Journal of Physics: Conference Series 2117, no. 1 (2021): 012005. http://dx.doi.org/10.1088/1742-6596/2117/1/012005.

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Abstract The lithium-ion battery is promising energy storage that provides proper stability, no memory effect, low self-discharge rate, and high energy density. During its usage, batteries generate heat caused by energy loss due to the transition of chemical energy to electricity and the electron transfer cycle. Consequently, a thermal management system by cooling methods in the battery is needed to control heat. One of the cooling methods is a passive cooling system using a phase change material (PCM). PCM can accommodate a large amount of heat through small dimensions. It is easy to apply and requires no power in the cooling system. This study aims to find the best type of PCM criteria for a Lithium-ion battery cooling system. The research was conducted by simulations using computational fluid dynamics. The variations were using PCM Capric Acid and PCM Hexacosane, with thickness variations of 3 mm, 6 mm, and 9 mm. Hexacosane PCM with 9 mm thickness indicates the best result to reduce heat up to 6.54°K, demonstrating a suitable passive cooling system for Li-ion batteries.

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FAN, Yu-Lei, and Xiao-Feng MENG. "Transaction Recovery Model of Databases Based on PCM and Flash Memory." Chinese Journal of Computers 36, no. 8 (2014): 1582–91. http://dx.doi.org/10.3724/sp.j.1016.2013.01582.

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Ruan, Shenchen, Haixia Wang, and Dongsheng Wang. "MAC : A Novel Systematically Multilevel Cache Replacement Policy for PCM Memory." Computer Applications: An International Journal 3, no. 2 (2016): 11–22. http://dx.doi.org/10.5121/caij.2016.3202.

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Fu, Yinjin, Yutong Lu, Zhiguang Chen wu, Yang Wu, and Nong Xiao. "Design and Simulation of Content-Aware Hybrid DRAM-PCM Memory System." IEEE Transactions on Parallel and Distributed Systems 33, no. 7 (2022): 1666–77. http://dx.doi.org/10.1109/tpds.2021.3123539.

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Junsangsri, Pilin, and Fabrizio Lombardi. "A New Comprehensive Model of a Phase Change Memory (PCM) Cell." IEEE Transactions on Nanotechnology 13, no. 6 (2014): 1213–25. http://dx.doi.org/10.1109/tnano.2014.2353992.

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Ciocchini, Nicola, Marco Cassinerio, Davide Fugazza, and Daniele Ielmini. "Modeling of Threshold-Voltage Drift in Phase-Change Memory (PCM) Devices." IEEE Transactions on Electron Devices 59, no. 11 (2012): 3084–90. http://dx.doi.org/10.1109/ted.2012.2214784.

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Baek, Seungcheol, Hyung Gyu Lee, Chrysostomos Nicopoulos, and Jongman Kim. "Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression." ACM Transactions on Design Automation of Electronic Systems 20, no. 1 (2014): 1–31. http://dx.doi.org/10.1145/2658989.

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Mohseni, Milad, and Ahmad Habibized Novin. "A survey on techniques for improving Phase Change Memory (PCM) lifetime." Journal of Systems Architecture 144 (November 2023): 103008. http://dx.doi.org/10.1016/j.sysarc.2023.103008.

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Yang, Zhe, Dayou Zhang, Jingwei Cai, et al. "Joule heating induced non-melting phase transition and multi-level conductance in MoTe₂ based phase change memory." Applied Physics Letters 121, no. 20 (2022): 203508. http://dx.doi.org/10.1063/5.0127160.

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Phase change memory (PCM) is considered as a leading candidate for next generation data storage as well as emerging computing device, but the advancement has been hampered by high switching energy due to the melting process and amorphous relaxation induced large resistance drift. Polymorphic crystal-crystal transition without amorphization in metal dichalcogenides (TMDs) could be employed to solve these issues. Yet, the mechanism is still controversy. A melting-free PCM made of two dimensional (2D) MoTe2, which exhibits unipolar resistive switching (RS) and multi-level states with substantially reduced resistance drift via joule heating, is reported in this work. The device is first prepared based on the temperature dependence of Raman spectrum and electrical transport investigations on MoTe2 films. Significantly improved device performances on energy efficiency, switching speed, and memory window are further achieved by electrode size scaling down, indicating the key role of localized heating. Then, device scale transmission electron microscopy images reveal that the resistive switching stems from the transition between semiconducting 2H phase and metallic 1T′ phase. An entropy induced Te vacancies model is proposed to explain the reversible phase change mechanism in the MoTe2 based device. This study paves the way for further development of PCM based on atomically thin 2D TMDs, aiming for high density storage-class memory and high-precision neuromorphic computing.

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