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1
Willis, David Joe 1978. "A pFFT accelerated high order panel method." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/78436.
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Kantzon, David. "PFC-design for frequency converter." Thesis, Linköpings universitet, Fysik och elektroteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-124547.
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This thesis deals with power factor correction for three-phase systems. A boost-buck topology was described, modeled and then simulated in MATLAB/Simulink. The simulation results show that the system provides a power factor over 99% over the tested power output range. Moreover, the harmonic injection concept was introduced which reduces the total harmonic distortion to 8.72% at full output power. A prototype system was also built using an FPGA for the control system. The prototype did not provide the performance seen in simulation but showed that the method is valid and does provide a higher power factor when used.
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Bignold, Simon M. "Optimisation of the PFC functional." Thesis, University of Warwick, 2016. http://wrap.warwick.ac.uk/80984/.
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In this thesis we develop and analyse gradient-fl ow type algorithms for minimising the Phase Field Crystal (PFC) functional. The PFC model was introduced by Elder et al [EKHG02] as a simple method for crystal simulation over long time-scales. The PFC model has been used to simulate many physical phenomena including liquid-solid transitions, grain boundaries, dislocations and stacking faults and is an area of active physics and numerical analysis research. We consider three continuous gradient fl ows for the PFC functional, the L2-, H-1- and H2-gradient fl ows. The H-1-gradient flow, known as the PFC equation, is the typical flow used for the PFC model. The L2-gradient flow is known as the Swift-Hohenberg equation. The H2-gradient ow appears to be a novel feature of this thesis and will motivate our development of a line search algorithm. We analyse two methods of time discretisation for our gradient fl ows. Firstly, we develop a steepest descent algorithm based on the H2-gradient fl ow. We further develop a convex-concave splitting of the PFC functional, recently proposed by Elsey and Wirth [EW13], to discretise the L2- and H-1-gradient flows. We are able to prove energy stability of both our steepest descent algorithm and the convex-concave splitting scheme of [EW13]. We then use the Lojasiewicz gradient inequality (first developed in [ Loj62]) to prove that all three schemes converge to equilibrium. For numerical simulations we undertake spatial discretisation of our schemes using Fourier spectral methods. We consider a number of implementation issues for our fully discrete algorithms including a striking issue that occurs when the number of spatial grid points is low. We then perform several numerical tests which indicate that our new steepest descent algorithm performs well compared with the schemes of [EW13] and even compared with a Newton type scheme (the trust region method).
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Pippig, Michael. "PFFT - An Extension of FFTW to Massively Parallel Architectures." Universitätsbibliothek Chemnitz, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-87717.
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We present a MPI based software library for computing the fast Fourier transforms on massively parallel, distributed memory architectures. Similar to established transpose FFT algorithms, we propose a parallel FFT framework that is based on a combination of local FFTs, local data permutations and global data transpositions. This framework can be generalized to arbitrary multi-dimensional data and process meshes. All performance relevant building blocks can be implemented with the help of the FFTW software library. Therefore, our library offers great flexibility and portable performance. Likewise FFTW, we are able to compute FFTs of complex data, real data and even- or odd-symmetric real data. All the transforms can be performed completely in place. Furthermore, we propose an algorithm to calculate pruned FFTs more efficiently on distributed memory architectures.
For example, we provide performance measurements of FFTs of size 512^3 and 1024^3 up to 262144 cores on a BlueGene/P architecture.
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Miller, Daniel [Verfasser]. "Optimierung einer eingangsgleichrichterlosen Leistungsfaktorkorrekturschaltung (PFC) / Daniel Miller." München : Verlag Dr. Hut, 2018. http://d-nb.info/1156510481/34.
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Schiff, Albrecht Johannes. "Optimised PFC circuits for efficient power conversion." Thesis, University of Cambridge, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.611141.
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Matejov, Michal. "Pasivní PFC filtry pro spínané napájecí zdroje." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217598.
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This work deals with theory of switched power sources. There is description of the ways for connection and their practice purposes. In the next parts there are defined requirements on input supply circuit for these sources, especially for the form of output current. There are mentioned the basic connecting methods of PFC circuits and these methods modify the output current to meet the requirements of specification ČSN EN 61000- 3- 2. In the next parts there are shown simulations of PFC circuits made by Pspice application. Further is the basic description of sources construction for the sources which were used for testing and measuring. The final part deals with evaluation of the measuring on the chosen computer’s source. It compares between the manufacturer’s solutions and PFC circuit made by ourselves.
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Livingstone, Phil. "Nicotinic modulation of dopaminergic signalling in the PFC." Thesis, University of Bath, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.528111.
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Sartori, Hamiltom Confortin. "Uma nova metodologia de projeto para otimização do volume do converosr boost PFC." Universidade Federal de Santa Maria, 2009. http://repositorio.ufsm.br/handle/1/8466.
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Conselho Nacional de Desenvolvimento Científico e TecnológicoThis work investigates the influence of operation point (Δi @ fs) in the final volume of PFC boost converter. The boost inductor, EMI filter and thermal heatsink are the elements which main influences in the converter volume. These elements are strongly influenced by the chosen operation point, showing a direct relationship among them. With the increase of switch frequency and of the input current ripple occurs reduction of the boost inductor volume. On the other hand, it increases the switching losses in semiconductors, and influence on the EMI filter volume. It should be highlight that the optimum designs of individual devices or parameters of a system could not take the optimization of the overall system. In this form it is strongly recommended that the engineers and designers take into account the overall system, as well available technologies, standard and recommendation, and finally market commitments. The methodology presented realize the converter design in a integrate form, selecting the operation point that the converter finds the minimal total volume, starting from input variable output power, input and output voltage. The design takes into account different semiconductors technologies, different input filter topologies, different heart sinks profile, different magnetic cores technologies further of international standards that the converter must be adapt. Based on an integrate design of converter parameters is possible optimize the design finding the operation point for the minimal volume.
Esse trabalho investiga o impacto do ponto de operação (Δi @ fs) no volume final do conversor boost operando como pré regulador com correção do fator de potência (PFC). Os elementos de maior influência no volume do conversor são o indutor boost, o filtro de entrada e os dissipadores térmicos. O volume destes elementos é diretamente influenciado pelo ponto de operação, mostrando uma relação direta entre eles. Com o aumento da freqüência de comutação e da ondulação da corrente de entrada ocorre a diminuição do indutor boost, porém, aumentam as perdas nas comutações dos semicondutores e aumenta o volume do filtro de entrada. Com a diminuição da freqüência e da ondulação da corrente ocorre o inverso, sabendo disto, fica claro que projetar individualmente cada um destes três elementos pode resultar em um bom projeto individual, contudo penaliza os outros parâmetros. Assim, a metodologia apresentada realiza o projeto do conversor de forma integrada, escolhendo o ponto de operação em que o conversor encontre o volume final mínimo, partindo de algumas variáveis de entrada, como potência de saída e tensões de entrada e saída. O projeto leva em consideração diferentes tecnologias de semicondutores, topologias de filtros de entrada, perfis de dissipadores térmicos, tecnologias de núcleos magnéticos além das normas internacionais a que o conversor deve se adequar. Baseado no projeto integrado dos parâmetros do conversor é possível otimizar o projeto encontrando o ponto de operação para o volume total mínimo do conversor.
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Zhou, Bo. "CCM Totem Pole Bridgeless PFC with Ultra Fast IGBT." Thesis, Virginia Tech, 2014. http://hdl.handle.net/10919/51120.
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The totem pole PFC suffers from the Mosfet body diode reverse recovery issue which limits this topology adopted in the CCM high power condition. As the ultra-fast IGBT which is capable of providing 100 kHz switching frequency is available in the market, it is possible to apply the totem pole PFC in CCM high power condition. The thesis provides a method by implementing the ultra-fast IGBT and SiC diode to replace the MOSFET in this topology.
To verify the method, a universal CCM totem pole PFC is designed and tested. The design adopts the ADP1048 programmable digital PFC controller by adding external logic gate for totem-pole PFC. ADP1048 greatly simplifies the design process and satisfies the design requirements. The experiment results verify that the totem-pole PFC can be applied into CCM high power condition by using the method. The DC output voltage is well regulated. The power factor is higher than 0.98 when the load is above 400W. The measured efficiency can achieve up to 96.8% at low line and 98.2% at high line condition with switching frequency 80 kHz.Master of Science
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Lange, André De Bastiani. "Retificador PFC monofásico PWM bridgeless três-níveis de alto desempenho." Florianópolis, 2012. http://repositorio.ufsc.br/xmlui/handle/123456789/100858.
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Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia ElétricaMade available in DSpace on 2013-06-25T23:20:04Z (GMT). No. of bitstreams: 1 307896.pdf: 8014354 bytes, checksum: e7f5c5f26cf0e245f5bbdc82d9fe7865 (MD5)
Este trabalho apresenta uma nova topologia de retificador monofásico com fator de potência e rendimento elevados, com o objetivo de adaptar-se aos requisitos de sistemas de conversão modernos. O conversor se caracteriza por integrar as etapas de retificação e conversão CC-CC em um único estágio e por operar com três níveis de tensão para o controle da corrente de entrada. A estrutura possibilita a redução das perdas em condução e de comutação, bem como a redução do volume de dispositivos magnéticos. Uma operação eficiente do retificador é obtida com uma técnica de modulação adequada, também foco deste trabalho. Duas técnicas de controle para o retificador foram analisadas e implementadas em um controlador digital de sinais de baixo custo. Uma análise de estabilidade é apresentada para a técnica de autocontrole de corrente considerando-se os efeitos dos atrasos de transporte da implementação digital. Um novo controlador adaptativo e metodologia de projeto são propostos para permitir a operação do conversor em ampla faixa de variação de carga utilizando esta técnica. A verificação experimental é realizada através de um protótipo de 3 kW desenvolvido em laboratório, para o qual se utilizou uma metodologia de projeto que minimiza o volume de material magnético utilizado no indutor boost.
This work presents a novel single-phase rectifier topology with high power factor and high efficiency, aiming to fulfil modern conversion systems requirements. This converter is characterized by integrating the rectifying and DC-DC conversion stages into a single stage and operates with three voltage levels for controlling the input current. The topology enables low conduction and commutation losses and reduced volume of magnetic devices. Efficient rectifier operation is achieved with a suitable modulation technique, which is also within the focus of this work. Two control techniques for the rectifier have been analysed and implemented in a low-cost digital signal controller. A stability analysis is presented for the current self-control technique considering the effects of the transport delays found in the digital implementation. A new adaptive compensator and design method are proposed to allow the converter to operate with wide load variation range using this technique. Experimental verification is performed with a 3 kW labprototype employing a boost inductor optimized design that minimizes magnetic material volume.
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Koh, Hyunsoo. "Modeling and Control of Single Switch Bridgeless SEPIC PFC Converter." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/34125.
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Due to increasing concerns on the power quality, power factor correction (PFC) has become an important issue in light-emitting diode (LED) lighting applications. A boost converter is one of the most well-known PFC topologies, due to its simple circuitry, simple control scheme and small number of passive components. Even though a boost converter is recognized as a typical PFC converter, its output voltage must be higher than its input voltage. This feature is disadvantageous because the device requires an additional buck-stage for LED lighting systems.
As an alternative to the boost converter, a single-ended primary-inductor converter (SEPIC) allows output voltage to be lower or higher than the input voltage. Thus, the SEPIC converter is gaining popularity as a LED driver because it does not require additional power conversion stage. However, designing a controller to meet stability requirements and international standards is quite challenging for SEPIC converters. Additionally, if the digital controller is adopted for its built-in communication features, creating a digitally controlled SEPIC converter would be even more challenging.
This thesis focuses on the state-space averaging modeling of the SEPIC PFC converter and the design of controllers based on both analog and digital controls with precise modeling. The proposed SEPIC converter incorporates RC damping circuits to avoid the instability, and
thus the entire SEPIC converter becomes a 5th order system. Such a high-order system model was derived mathematically and verified with circuit simulator modeling. After verification of the circuit model, the controller was designed with analog transfer functions and converted to and the discrete domain for digital controller implementation. A 150-W single-switch bridgeless SEPIC PFC converter prototype was built accordingly to verify the design. In addition to the current loop controller design for stability, a feed-forward compensator for is introduced and derived for better waveform quality. Simulation results and experiment results are also presented to verify the complete controller with feed-forward compensation. The Texas Instruments (TI) digital signal processor (DSP) TMS320F28335 was adopted for digital controller implementation. For comparison purpose, the TI UC3854 controller was implemented to verify the analog controller design results.Master of Science
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Miko, Radoslav. "Třífázový síťový napaječ s aktivním usměrňovačem." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242035.
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Diploma thesis deals with problems of power factor correction and total harmonic distortion of line current in three phase industrial power supplies. It focuses mainly on using of single phase active PFC topologies based on the principle of step up converter, which are applicable to three phase systems. Verification of operation and comparison of parameters of several circuits was done by simulation in program Matlab Simulink. Then for selected circuit of active PFC was done complete design. The result is a prototype of single phase active PFC circuit with an output power 2 kW for input voltage range from 180 to 528 V (47 – 63 Hz) and a prototype of three phase active PFC circuit with an output power 6 kW for input voltage range from 3 x 180 to 3 x 528 V (47 – 63 Hz).
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AlShehab, Ali Saeed. "Development and analysis of high-frequency, high-density PFC power conversion." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/106076.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis. "September 2015."
Includes bibliographical references (pages 83-85).
This thesis explores the design of power converters that deliver isolated low-voltage dc output (~24V) and operate from "universal" ac input voltage (85 - 264 Vac RMS). It is important that these converters have good overall efficiency (~90-95%), and good ac line power factor (>0.9, and ideally >0.95) to better utilize the available energy. This thesis looks into achieving high efficiency, high power factor, low voltage stresses, and smaller component sizes by utilizing high frequency operation. The research focuses on component and subsystem evaluation, development and testing as a part of many-person research in this space. The thesis presents a literature based study on current PFC circuit designs and tradeoffs. It also introduces a specific PFC architecture, which provides a low dc output voltage drawing energy from a wide range ac input voltage while maintaining a high power factor. The architecture includes two stages: The first is a "Power Factor Correction" (PFC) which functions as an input stage drawing energy from a wide-range input current. It uses a resonant transition inverted (RTI) buck converter topology to step down the voltage from line voltage (85 - 264 Vac RMS) to around 72V. Furthermore, the inductor for the RTI buck is analyzed. The middle stage is an energy buffer to provide the required energy level for twice line frequency energy buffering and 20ms of energy hold up. The capacitor requirements, analysis, and selection are explored and developed. The second stage is a transformation and regulation stage which also provides electrical isolation between the ac input and dc output. The thesis also explores the use of available conventional high-density telecom "brick" converters as a second stage. In conclusion, the project explores the possibility of using a buck configuration for the PFC, sacrificing the ability to use high energy density 400V capacitors while gaining the advantage of using the high-density telecom brick converters and different output voltage options.
by Ali Saeed AlShehab.
M. Eng.
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Mallet, Géraldine-Mary. "La liaison en français : descriptions et analyses dans le corpus PFC." Paris 10, 2008. http://www.theses.fr/2008PA100172.
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La liaison en français est un phénomène qui s’étend sur différents niveaux d’analyse et qui, pour cette raison, est problématique. La première partie de cette thèse s’attache à décrire ces différentes dimensions impliquées dans le processus (phonologique, morpho-syntaxique, sociolinguistique, lexicale), pour montrer en quoi cette diversité est constitutive du phénomène et qu’on ne peut pas réduire la liaison à une dimension particulière. Dans la seconde partie, nous nous appuyons sur une étude empirique fondée sur une utilisation de la base PFC (Phonologie du Français Contemporain). Cette partie présente la description du protocole, la collecte et l’exploitation des données. La dernière étape de ce travail consiste à proposer une caractérisation de la liaison qui rend compte des contradictions relevées dans la première partie, en s’appuyant sur une véritable base empirique. De cette façon, nous montrons que si la liaison est fréquente, elle concerne néanmoins des classes réduites de mot et nécessite une analyse formes par formes, sans exclure un certain nombre de généralisations locales qui constituent le caractère innovant de ce travailThe French liaison is a complex phenomenon manifested in many different levels of analysis. The first part of the thesis is an overview of the various dimensions involved in the process: phonologic, morpho-syntactic, sociolinguistic, lexicon. The goal of this overview is to show that the multidimensionality is proper to the liaison phenomenon and that the descriptive diversity can not be reduced to a single, specific dimension. The second part is an empirical study based on the Phonology of Contemporary French corpus and database. It contains the description of the protocol, data collection and data processing. The last part carries out a liaison analysis which, standing on a solid empirical fundament, takes into account the contradictions outlined in the first part. The study shows that regardless of its frequency, the liaison affects entire word categories (classes) and requires a form-by-form analysis, yet allowing for certain amount of local generalizations which constitute the scientific contribution of this thesis
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Huang, Weixing. "Design of a Radial Mode Piezoelectric Transformer for a Charge Pump Electronic Ballast with High Power Factor and Zero Voltage Switching." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/31818.
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In a conventional electronic ballast for a fluorescent lamp, inductor-capacitor-transformer
tank circuit is used. A Piezoelectric Transformer (PT) can potentially be used
to replace such a tank circuit to save space and cost. In the past, ballast design using a PT
requires selecting a PT from available samples which are normally not matched to
specific application and therefore resulting in poor performance. In this thesis, a design
procedure was proposed for designing a PT tailored for a 120-V 32-W electronic ballast
with high power factor, high efficiency and Zero-Voltage-Switching (ZVS) of the
inverter transistors that drive the lamp. This involves selection of PT materials,
determination of geometries and the number of physical layers of the PT. A radial mode
piezoelectric transformer prototype based on this design process was fabricated by Face
Electronics Inc. and was tested experimentally, the results showed that the ballast using
this custom-made PT achieved high power factor, Zero-Voltage-Switching and a 83%
overall efficiency.Master of Science
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Sang, Tingting. "Integrated Electro-thermal Design Methodology in Distributed Power Systems (DPS)." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9678.
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Although suitable CAD tools for thermal and electrical analyses in power electronic systems are available, traditional stand-alone simulation method seldom takes into consideration of the inter-dependency of semiconductor device power loss and junction temperature in an iterative process. However these dependencies are important, especially for applications where both cooling and power losses are driven by complex mechanisms.
For a power supply system, a dynamic design process is necessary to address both electrical and thermal issues. It is because the steady state temperatures of the system are obtained from loss-and-temperature iteration. Once a system solid body model is built, iterations between power loss and junction temperature calculations are performed to obtain the steady state temperature distribution. Since reliability and failure rate of components are directly related to temperatures, an accurate model is critical to provide proper thermal management, which achieves maximum power density. All cooling-related data such as placement of components, airflow rate, heat sink size, and device types are subjected to design changes in order to meet ultimately the temperature requirements.
The goal of this thesis is to demonstrate the benefits of integrated analysis and design tools applied in distributed power supply systems designs. First, it will significantly speed up the design process and eliminate the errors resulting from repeated manual data entry and information exchange. Second, the integrated electrical-thermal design tools encompass electrical, thermal, layout, and packaging design to obtain the optimal system design.Master of Science
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Plakke, Anderson Bethany Joy. "Auditory working memory: contributions of lateral prefrontal cortex and acetylcholine in non-human primates." Diss., University of Iowa, 2010. https://ir.uiowa.edu/etd/1060.
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Traditionally, working memory and its neural underpinnings have been studied in the visual domain. A rich and diverse amount of research has investigated the lateral prefrontal cortex (lPFC) as a primary area for visual working memory, while another line of research has found the neurotransmitter acetylcholine (ACh) to be involved. This dissertation used auditory cues and found similar patterns of activity for processing auditory working memory information within a task compared to visual working memory processes. The first two experimental chapters demonstrated that the cholinergic system is involved in auditory working memory in a comparable fashion to its role in visual working memory. In chapter 2, blocking ACh impaired performance on an auditory working memory task in a dose dependent manner. Chapter 3 investigated the specificity of the effect of blocking ACh by administering an ACh agonist (physostigmine) at the same time as an ACh antagonist (scopolamine). When both drugs were administered together performance on the delayed matching-to-sample task (DMTS) task improved compared to performance on scopolamine alone. These results support the hypothesis that ACh is involved in auditory working memory.
Chapter 4 investigated the neural correlates of auditory working memory in area 46 and found that this region of the lPFC contains neurons that are responsive to auditory working memory components in a very similar way to how it this region encodes information during visual working memory tasks. Neurons in the lPFC are responsive to visual or auditory cues, the delay portion of tasks, the wait time (i.e. decision making period), response, and reward times. This type of coding provides support for the theories that position the lPFC as a key player in recognition and working memory regardless of modality.
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Grote, Tobias [Verfasser]. "Digital control for interleaved boost power factor correction (PFC) rectifiers / Tobias Grote." Paderborn : Universitätsbibliothek, 2014. http://d-nb.info/105184813X/34.
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Chen, Rui. "Analysis and Design of a DCM SEPIC PFC with Adjustable Output Voltage." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/51664.
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Power Factor Correction rectifiers are widely adopted as the first stage in most grid-tied power conversion systems. Among all PFC converts for single phase system, Boost PFC is the most popular one due to simplicity of structure and high performance. Although the efficiency of Boost PFC keeps increasing with the evolution of semiconductor technology, the intrinsic feature of high output voltage may result cumbersome system structure with multiple power conversion stages and even diminished system efficiency. This disadvantage is aggravated especially in systems where resonant converters are selected as second stage.
Especially for domestic induction cooker application, step-down PFC with wide range output regulation capability would be a reasonable solution, Conventional induction cooker is composed by input filter, diode-bridge rectifier, and full bridge or half bridge series resonant circuit (SRC). High frequency magnetic field is induced through the switching action to heat the pan. The power level is usually controlled through pulse frequency modulation (PFM). In such configuration, first, a bulky input differential filter is required to filter out the high frequency operating current in SRC. Second, as the output power decreases, the operating point of SRC is moved away from the optimum point, which would result large amount circulating energy. Third, when the pan is made of well conducting and non-ferromagnetic material such as aluminum, due to the heating resistance become much smaller and peak output voltage of the switching bridge equals to the peak voltage of the grid, operating the SRC at the series resonant frequency can result excessive current flowing through the switch and the heating coil. Thus for pan with smaller heating resistance, even at maximum power, the operating frequency is pushed further away from the series resonant point, which also results efficiency loss.
To address these potential issues, a PFC circuit features continuous conducting input current, high power factor, step-down capability and wide range output regulation would be preferred. The Analysis and design work is present in this article for a non-isolated hard switching DCM SEPIC PFC. Due to DCM operation of SPEIC converter, wide adjustable step-down output voltage, continuous conduction of input current and elimination of reverse recovery loss can be achieved at same time.
The thesis begins with circuit operation analysis for both DC-DC and PFC operation. Based on averaged switching model, small signal model and corresponding transfer functions are derived. Especially, the impact from small intermediate capacitor on steady state value are discussed.
With the concept of ripple steering, theoretic analysis is applied to SEPIC converter with two coupled inductors. The results indicate if the coupling coefficient is well designed, the equivalent input inductance can be multiple times larger than the self-inductance. Because of this, while maintaining input current ripple same, the two inductors of SEPIC can be implemented with two smaller coupled inductors. Thus both the total volume of inductors and the total number of windings can be reduced, and the power density and efficiency can be improved. Based on magnetic reluctance model, a corresponding winding scheme to control the coupling coefficient between two coupled inductors is analyzed. Also the impact of coupled inductors on the small signal transfer function is discussed.
For the voltage follower control scheme of DCM PFC, single loop controller and notch filter design are discussed. With properly designed notch filter or the PR controller in another word, the closed loop bandwidth can be increased; simple PI controller is sufficient to achieve high power factor; THD of the input current can be greatly reduced.
Finally, to validate the analysis and design procedure, a 1 kW prototype is built. With 120 Vrms AC input, 60V to 100V output, experimental results demonstrate unity power factor, wide output voltage regulation can be achieved within a single stage, and the 1 kW efficiency is around 93%.Master of Science
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Busà, Veronica. "La production de /R/ chez les locuteurs de Niamey : une première enquête de terrain." Thesis, Paris 10, 2018. http://www.theses.fr/2018PA100008/document.
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Notre étude s’intéresse à un aspect phonologique : le comportement du phonème /R/ du français parlé à Niamey, capitale du Niger, pays de l’Afrique subsaharienne. L’enquête a été mené selon le protocole du projet international, Phonologie du Français Contemporain (abrégé PFC). Il vise à rassembler un vaste corpus oral de français contemporain à travers toutes les zones francophones du monde.Nos enquêtes de terrain ont été effectuées dans une ville où le français demeure la langue officielle, et où l’on retrouve aussi d’autres langues nationales et/ou locales (haousa, songhaï-zarma, touareg, peul, kanuri et arabes). Une présentation des rhotiques du point de vue phonétique et phonologique s’est avéré nécessaire, avant la classification et l’analyse de nos données. D’une part nous avons analysé les allophones de /R/ réalisés par les enquêtés. Ces analyses montrent que la réalisation largement majoritaire est la vibrante alvéolaire [r], suivie de loin par la fricative uvulaire [ʁ], puis par les réalisations [ɰ], [χ], [ɻ] et la non-réalisation de /R/ [ø]. Tous ces résultats ont été comparés ensuite à ceux d’autres points d’enquêtes PFC dans le monde. D’autre part, nous nous sommes intéressés à la chute de /R/ dans les groupes consonantiques et en finales, pour aboutir à la conclusion que ce phénomène dépend du lexique et, plus exactement, concerne généralement la prononciation des chiffres (par exemple quatre [katR]> [kat])This thesis focuses on the phonological aspect of the /R/ in French language spoken in Niamey, the capital of Niger, a Sub-Saharan country of Africa. The survey has been conducted conforms to theprotocol and the mehology of an international project Phonologie du Français Contemporain (PFC), which aims to collect a large corpus of contemporary French spoken from all around the word. In Niamey, French coexists with others national and local languages: haousa, songhaï-zarma, touareg, peul, kanuri et arabic.In the proposed work at first we have illustrated a phonetic and phonology classification of rhotics class, then we have classified and analyzed our data. We have analyzed all allophones of /R/ produced by the interviewed speakers. These data show that the largest part of the speaker pronounce a vibrant alveolar [r], followed by a fricative uvular [ʁ], and then by [ɰ], [χ], [ɻ] and [ø]. Furthermore, we have compared our results with other PFC studies conducted all around the francophone word. Additionally, we have focused on fall of /R/ in cluster group, and we concluded that this fall depends on the lexicon, and concerns especially numbers pronunciation (for example, quatre [katR]> [kat])
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Damasceno, Daniel da Motta Souto. "Metodologia de projeto de conversores boost para correção de fator de potência apliocada a sistemas ininterruptos de energia." Universidade Federal de Santa Maria, 2006. http://repositorio.ufsm.br/handle/1/8539.
Full textAbstract:
This Master Thesis presents a design methodology to a boost PFC converter operating as an Uninterruptible Power Supply rectifier input stage. This methodology defines, making use of a group of current ripples and switching frequencies, the converter minimum volume point analyzing the volumes of the boost inductor, the electromagnetic interference filter and the heat-sinks. Thus, it's developed along this work, each design mentioned above, analyzing the impact of different magnetic materiaIs, input filter topologies and semiconductors technologies. Previously, it is designed the controller and it is developed a simulation structure. ln a second moment, it's designed the boost inductor for a predetermined temperature elevation. After this, it's designed the electromagnetic filter analyzing the impact of different topologies. The heat-sinks are also designed to guarantee the semiconductors operation within the temperature limits. Finally, the methodology based on the previous designs is accomplished, using the procedures and equations already mentioned, becoming possible to define the converter minimum volume point.Esta Dissertação de Mestrado apresenta uma metodologia de projeto para o conversor boost operando como estágio retificador de entrada em uma fonte de alimentação ininterrupta. Essa metodologia se baseia em definir, através de um conjunto de freqüências de comutação e ondulações de corrente, o ponto de minimização do volume do conversor considerando o volume do indutor, do filtro de interferência eletromagnética conduzida e dos dissipadores. Assim, é desenvolvido ao longo desse trabalho o projeto de cada elemento mencionado estudando o impacto do uso de diferentes materiais magnéticos, topologias de filtro de entrada e tecnologias de semicondutores. Inicialmente é projetado o controlador e desenvolvida a estrutura de simulação do conversor. Em um segundo momento é projetado o indutor boost para uma determinada elevação de temperatura. A seguir é projetado o filtro de interferência eletromagnética analisando o impacto de diferentes topologias. Também são projetados os dissipadores que garantem a operação dos semicondutores dentro dos limites de temperatura estabelecidos pelos fabricantes. Por fim, é formalizada a metodologia baseada nos projetos anteriores, pela qual, fazendo uso dos procedimentos e equações fornecidos, torna-se possível definir o ponto de minimização do volume do conversor.
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Smith, Dorinda Ann. "The Development and Application of a Hemolytic Plaque Forming Cell Assay (PFC) and a Cytotoxic T-Lymphocyte Assay (CTL) in Tilapia (Oreochromis niloticus) for Immunotoxicity Risk Assessment of Environmental Contaminants." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/36948.
Full textAbstract:
The prospect of utilizing the cichlid teleost tilapia (Oreochromis niloticus) as an alternative experimental model to mammals for immunotoxicity risk assessment is currently being proposed. As such, the National Toxicology Program's (NTP) standard battery of rodent immunotoxicity assays is being developed for use in this fish species. Included in the testing series are the hemolytic plaque forming cell (PFC) and the cytotoxic T-lymphocyte (CTL) assays, quantitative indicators of antibody production and cell-mediated activity, respectively. The assays were modified in consideration of specific tilapian immune parameters, then tested using fourteen environmental contaminants or drugs, ten of which are classified by the NTP as immunotoxic in rodents. Reduced antibody production via a decrease in plaque number was observed in response to exposure of tilapia to eight of the nine humoral immunotoxicants, and five of the five non-immunotoxicants. Under specific immunization circumstances, immunostimulation (also a response to immunotoxicity) was noted via an increase in plaque number in benzo[a]pyrene (B[a]P) exposed fish using the PFC assay, a result noted in rodents as well. Reduced T-cell recognition and lysis of allogeneic tilapian lymphocytes via a decrease in the percentage of specific 51Chromium (51Cr) release was observed in response to exposure of tilapia to the nine of the ten cell-mediated immunotoxicants, and four of the four non-immunotoxicants. Although the normal teleost immune responsiveness was slightly weaker than seen with mice under comparable conditions (presumably due to differences in antibody structure and decreased cells counts), tilapia were found to exhibit well-defined humoral and cell-mediated immune responses, and responses to immunotoxic and non-immunotoxic chemicals comparable to the rodent model.Master of Science
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Cesar, Eduardo Lenz. "CONTROLE NÃO LINEAR DE UM PRÃ-REGULADOR ISOLADO COM PFC E ACOPLAMENTO AUXILIAR." Universidade Federal do CearÃ, 2011. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=6333.
Full textAbstract:
Este trabalho propÃe o estudo de uma nova topologia, com dois estÃgios, de um conversor
estÃtico, onde existe um fluxo de potÃncia auxiliar com o objetivo de aumentar o
rendimento do sistema. O primeiro estÃgio à um conversor CA-CC com correÃÃo do
fator de potÃncia (PFC) e o segundo estÃgio à um conversor CC-CC isolado em alta
frequÃncia.
Os dois estÃgios do conversor proposto sÃo modelados por equaÃÃes diferenciais e atravÃs
desses modelos sÃo desenvolvidas tÃcnicas de controle nÃo linear para o funcionamento
dos conversores em malha fechada.
A correÃÃo do fator de potÃncia do primeiro estÃgio à realizada pela tÃcnica de controle
PBC (passivity-based control), enquanto que a tensÃo de saÃda do primeiro estÃgio Ã
realizada pelo controle I&I (immersion and invariance).
O segundo estÃgio necessita controlar somente a tensÃo de saÃda atravÃs do controle
backstepping, por se tratar de um conversor CC-CC.This work proposes a study of a new static converter topology with two stages, where the first is an AC-DC converter with PFC and the second is a DC-DC converter isolated in high-frequency. In addition, the static converter has a secondary power flow to achieve a better efficiency from the system. The two converterâs stages are modeled as differential equations, and through those models nonlinear control techniques are developed for close loop operation. The power-factor correction in the first stage is performed by the PBC (passivity-based control) control technique, while the output voltage from the first stage is performed by the I&I (immersion and invariance) control. As the second stage is a DC-DC converter, it only needs to control the output voltage, which is achieved through the backstepping control.
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Cesar, Eduardo Lenz. "Controle não linear de um pré-regulador isolado com PFC e acoplamento auxiliar." reponame:Repositório Institucional da UFC, 2011. http://www.repositorio.ufc.br/handle/riufc/1412.
Full textAbstract:
CESAR, E. L. Controle não linear de um pré-regulador isolado com PFC e acoplamento auxiliar. 2011. 173 f. Dissertação (Mestado em Engenharia Elétrica) - Centro de Tecnologia, Universidade Federal do Ceará, Fortaleza, 2011.Submitted by Marlene Sousa (mmarlene@ufc.br) on 2011-12-13T18:59:15Z No. of bitstreams: 1 2011_dis_elcesar.pdf: 2495209 bytes, checksum: 00444e5d26a6053a7bcedf388e149661 (MD5)
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This work proposes a study of a new static converter topology with two stages, where the first is an AC-DC converter with PFC and the second is a DC-DC converter isolated in high-frequency. In addition, the static converter has a secondary power flow to achieve a better efficiency from the system. The two converter’s stages are modeled as differential equations, and through those models nonlinear control techniques are developed for close loop operation. The power-factor correction in the first stage is performed by the PBC (passivity-based control) control technique, while the output voltage from the first stage is performed by the I&I (immersion and invariance) control. As the second stage is a DC-DC converter, it only needs to control the output voltage, which is achieved through the backstepping control.
Este trabalho propõe o estudo de uma nova topologia, com dois estágios, de um conversor estático, onde existe um fluxo de potência auxiliar com o objetivo de aumentar o rendimento do sistema. O primeiro estágio é um conversor CA-CC com correção do fator de potência (PFC) e o segundo estágio é um conversor CC-CC isolado em alta frequência. Os dois estágios do conversor proposto são modelados por equações diferenciais e através desses modelos são desenvolvidas técnicas de controle não linear para o funcionamento dos conversores em malha fechada. A correção do fator de potência do primeiro estágio é realizada pela técnica de controle PBC (passivity-based control), enquanto que a tensão de saída do primeiro estágio é realizada pelo controle I&I (immersion and invariance). O segundo estágio necessita controlar somente a tensão de saída através do controle backstepping, por se tratar de um conversor CC-CC.
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"Insights into the Fresh Vegetable Sector in Saskatchewan." Thesis, 2015. http://hdl.handle.net/10388/ETD-2015-05-2036.
Full textAbstract:
Saskatchewan has good growing conditions, much land and water resources, minimal pest pressure and the expertise necessary for growing high-quality commercial vegetables. Statistics show, however, that commercial vegetable production occupies a relatively small place in the agricultural economy of Saskatchewan. Saskatchewan production accounts for less than 10 per cent of the total provincial market for fresh vegetables, the other supplies of fresh vegetables marketed in Saskatchewan come from sources outside of the province and imports from the southern United States, Mexico, and other warm regions. The majority of Saskatchewan produced vegetables are sold through market gardens, farmers’ markets and consumer contract sales. In light of the increasing importance of fresh vegetable demand, examining the role of a new marketing organization in the province is important as it might bring about major realignment of the Saskatchewan fresh produce market. Recently, a project supported by the Agriculture Council of Saskatchewan Inc. (ACS) encouraged producers to organize themselves into picking zones and to work together to supply larger retail markets. The Grocery People (TGP) (a retailer) has agreed to purchase vegetables grown in Saskatchewan for their distribution centre in Saskatoon. This new organization, Prairie Fresh Food Corporation (PFFC), despite its numerous benefits, will test the farmer participants’ resolve to cooperate rather than proceed alone. This poses a real opportunity for producers to expand and develop the infrastructure required, as produce can be pooled.
This study uses Transaction Cost, Agency and Monopolistic Competition theories to analyze the factors that hamper farmers from participating in contracts and taking advantage of these potential opportunities. It considers the advantages and barriers or potential challenges to wholesalers and retailers cooperating with this plan. In particular, an economic model of economies of scale through collective action is developed. The model assumes that small growers can access higher market share through collective action and achieving economies of scale.
The results of personal interviews with eleven members of PFFC are presented and analyzed in a case study format. The case study analysis of PFFC reveals that the organization could provide positive benefits to its members in the early period of its establishment. The results show that the market share of the PFFC is still relatively small throughout the province, but its members expect it to expand in the future. The results suggest that high relative prices in the market and trust in the buyer have a positive effect on the probability of farmer participation in the project.
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Lin, Cheng-Pin, and 林正斌. "Comparison Between Dual Phase Interleaved PFC Converter and ZCS PFC Converter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/rnp27c.
Full textAbstract:
碩士崑山科技大學
電子工程研究所
96
In This thesis, we study and implement a 300W BCM (Boundary Current Mode) dual-phase interleave PFC (Power Factor correction) circuit and a 300W active PFC circuit with ZCS (Zero Current Switching)。 At first, we describe the operation and topology difference between these circuits, then design and implement both of these practical PFC circuits for performance comparison. Finally, the results of comparisons are presented. According to comparisons of switching waveforms, power factors and other relative experiment results, the BCM interleaved PFC and ZCS PFC are suitable for apply on cases under 300W and above 300W, respectively.
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Shen, Chuan-Hsing, and 沈俊興. "PFC: Packet Filter Cache." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/92813635078526655899.
Full textAbstract:
碩士元智大學
資訊工程學系
92
As communication technology advances, network capacity grows exponentially in recent years. The performance of network monitoring tools is getting more critical as they must process much lager number of packets in a unit of time than ever before. A common core component in any network monitoring tools is a packet filter which processes every packet header and passes those packets matching some filter rules to user spaces for further processing. Previous work on packet filters make an effort to investigate flexible and extensible filter abstractions but sacrifice performance, or focus on low-level, optimized filtering representations but sacrifice flexibility. In this paper, a packet filter architecture called Packet Filter Cache (PFC) is proposed to improve the performance of existing packet filters. The PFC architecture adds a filter rule cache before an existing packet filter. Instead of caching instruction set as in Warm cache, the filter rule cache stores the hash value of a filter rule as a hash table entry that can be searched in one memory access. By taking advantage of the hash lookup speed, PFC can boost filtering performance by using only small cache size. Moreover, PFC also caches unmatched packet flows to achieve high hit rate. Since PFC is only a cache mechanism added before a traditional packet filter, it does not need to re-engineer existing filter module and hence can be applied on most packet filters. Simulation shows PFC can improve the processing time about four times at cache hit rate of 70%.
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Westerman, George, and Robert Walpole. "PFPC: Building an IT Risk Management Competency." 2005. http://hdl.handle.net/1721.1/18232.
Full textAbstract:
IT Risk management is becoming increasingly important for CIOs and their executive counterparts. Educators and managers have materials they can use to discuss specific IT risks in project management, security and other risk-related topics, but they have few resources they can use to have a holistic discussion of enterprise-level IT risk management. This case is intended to address the gap. It describes the IT risks facing a large financial services firm, PFPC, as a result of rapid growth, a large merger and distributed management of the IT function. The firm’s first enterprise-wide CIO, Martin Deere used risk management as a key pillar in a major revamp of the firm's applications and IT capabilities. The case is rich in detail on the firm's IT risks, the new risk management process, including examples of the firm's risk management tools. It also describes early lessons and outcomes in the implementation of risk management capabilities. The case has enough richness and potential controversy to engage students from the undergraduate through executive levels in an informative and interesting discussion of IT risk management.
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Yang, Chin-chi, and 楊清吉. "Realization and Comparison for a Single-stage Flyback PFC and a Single-stage SEPIC PFC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/45293180514036399879.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
97
The rapid advancements in new materials and manufacturing technologies have facilitated the use of high-luminance LEDs for lighting applications, and they have efficacies (lm/W) above those of incandescent lamp, which are growing to fluorescent efficacy levels. Compared with fluorescent lamps, LED lamps have numerous advantages, such as up to 100,000 hours of operation life, a wide range of temperature operation for -20�aC to 120�aC, and their ability to work with low and safe voltages. In general lighting applications, a single-stage discontinuous current conduction mode (DCM) Flyback power factor correction (PFC) converter is commonly used to drive LED lamps for achieving a high power factor and regulating lamp current with a simple circuit configuration. However, DCM operation causes high peak current stresses and serious electromagnetic interference (EMI) problem. The thesis aims to study a coupled inductor SEPIC PFC converter topology for lighting LED driver. Continuous current conduction mode (CCM) operation on input current can be realized by using a commercial low-cost BCM PFC control IC. High efficiency and high power factor can be simultaneously achieved by the studied single-stage LED driver. The operation principles and design considerations of the studied LED driver are analyzed and discussed. A laboratory prototype is also implemented and tested to verify the feasibility. Finally, performance comparisons between the studied LED driver and the conventional single-stage DCM Flyback converter topology are also presented.
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Lin, Jia-Yi, and 林佳儀. "PFC Rectifiers Based Bridgeless Boost Converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/69808943006936706932.
Full textAbstract:
碩士國立交通大學
機械工程系所
101
This paper presents the AC to DC Power Factor Correction converter with boost topology, using average current mode in fixed 200kHz switching frequency, and using microcontroller TMS320F28035 to control the PWM duty ratio in continuous conduction mode to re-shape the input current waveform and in phase with the input voltage. Typically, the PFC stage is a bridge rectifier followed by a boost circuit. However, the current distortion and power losses in the diode bridge cannot be ignored, so the conventional PFC topology is replaced by bridgeless PFC topology. This paper using the full-load 300W with two boost circuits in parallel whitch operates alternately in positive and negative half cycle of AC input voltage, so the conduction loss and current shape distortion can be improved due to the reduction of the number of diodes compare to the conventional PFC topology. The experiment results show in full-load the power efficiency is 93.39% and the power factor reaches to 0.9994.
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Tsai, Chien-Li, and 蔡建利. "A Passive PFC Converter with ZCS." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/229sfd.
Full textAbstract:
碩士國立臺北科技大學
電機工程系研究所
96
The PFC (Power Factor Correction) circuit is widely used in various power supplies so as to reduce the corresponding harmonic distortion and to increase power factor. Up to now, the environment protection and the energy saving are getting more and more attractive in the world. Consequently, improvement in the overall efficiency of the power supply is indispensable, and hence enhancement of the efficiency of the PFC circuit is an important research topic. Consequently, a passive ZCS (Zero Current Switching) PFC circuit topology is presented herein, which is used on the characteristics of the saturable coupling inductor. As the PFC circuit works in the steady state, such an inductor is short-circuited, so as to make the loss in this inductor as minimum as possible. On the other hand, as the power switch of the PFC circuit is switched on, the saturable coupling inductor gets far away from the saturated condition and is represented as an inductor, so as to reduce the reverse recovery current of the boost diode and to absorb the portion of the energy created from this current. By doing so, the boost diode can be switched off under ZCS, and at the same time the switching loss of the main power switch can be reduced. Besides, before the main power switch is turned off and the boost diode is turned on, the ZCS circuit releases this stored energy to the output, so as to further upgrade the efficiency of the PFC circuit.
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Wang, Chien-Hung, and 王健鴻. "Digital Control for Cuk PFC Converter." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/85361477657003231723.
Full textAbstract:
碩士國立交通大學
電機學院電機與控制學程
104
This thesis presents Cuk converter and its digital control method to achieve the power factor correction (PFC) function. Compared to the common dual- loop-control method, this thesis focuses on the new control mode to meet IEC61000-3-2 harmonic standard. This context is adopted from Texas Instruments C2000 series TMS320F28335 , of which DSP chip is to be controlled by the entire circuit. This DSP is categorized into TMS320F28X series, which has floating-point capabilities. Compared to the fixed-point DSP, it has not only more accuracy arithmetic function, but also has the advantages of low cost and low power consumption. Furthermore, it can hold greater data storage capacity and handle more accurate and faster AD converter, and so on. Digital Power Control is equipped easy and convenient applicability, providing better power management system, sophisticated power control solution, common design platform power control, cost decrease factor, and, most importantly, value-added intelligent integration. As the above-mentioned advantages are derived from programmable feature, so this is also a main factor to use DSP Chip to replace analog PWM IC.
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HIEU, PHAM PHU, and PHAM PHU HIEU. "Digital Control Strategy for Boost PFC Converter." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/27729671064086308862.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
103
Power factor correction (PFC) shapes the input current to minimize the reactive power drawing from the mains. The use of PFC circuits is widely discussed and considered for most off-line power supplies. For high power applications, boost PFC converter operated in continuous conduction mode is usually employed and controlled by analog ICs such as UC3854. However, when the converter operates at lower power range, discontinuous conduction mode will appear during parts of line period, causing input current distortion. Moreover, the input EMI filter causes the significant displacement between input voltage and input current when the converter operates at high-line light-load condition. With functions integrated inside analog ICs, they cannot be adapted to various mode of operation of circuit, resulting in poor power factor (PF) and high total harmonic distortion (THD). In order to implement more complex control scheme to improve PF and THD, the advantages of digital control are exploited. With flexibility, decreased number of components, less sensitivity with change of noise, low cost and increased performance, the digital controller is an interesting topic to research and employ for boost PFC converter. In this thesis, the digital controller what employs the Sample Correction, Duty Ratio Feed Forward and EMI filter capacitance current injection algorithms is proposed to solve above problems. A 400W Boost PFC prototype is implemented to verify the feasibility of the proposed control algorithms. The experimental results show the PF and THD improvements in both CCM and DCM operations.
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Liu, Jyun-Lin, and 劉俊麟. "A PFC Buck Rectifier with THD Improved." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/smhh9b.
Full textAbstract:
碩士國立臺北科技大學
電機工程系
106
A buck PFC rectifier with THD improved is developed herein. This converter operates in the discontinuous conduction mode (DCM) ,which makes the control easy. In addition, the diode has zero current turn-off such that there is no problem in reverse recovery current. Via output voltage sampling and voltage-follower control, a desired control force is created to drive the main power switch. By doing so, not only the output voltage is kept constant at a given value, but also the zero current region before and after the zero crossing point of the input current can be reduced. In this thesis, a voltage supperposition method is used such that the zero current region is reduced, thereby making the total harmonic decreased. Finally, the feasibility and effectiveness of the proposed method are verified by simulation and experiment, respectively.
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Knoblich, Ulf, David J. Freedman, and Maximilian Riesenhuber. "Categorization in IT and PFC: Model and Experiments." 2002. http://hdl.handle.net/1721.1/7270.
Full textAbstract:
In a recent experiment, Freedman et al. recorded from inferotemporal (IT) and prefrontal cortices (PFC) of monkeys performing a "cat/dog" categorization task (Freedman 2001 and Freedman, Riesenhuber, Poggio, Miller 2001). In this paper we analyze the tuning properties of view-tuned units in our HMAX model of object recognition in cortex (Riesenhuber 1999) using the same paradigm and stimuli as in the experiment. We then compare the simulation results to the monkey inferotemporal neuron population data. We find that view-tuned model IT units that were trained without any explicit category information can show category-related tuning as observed in the experiment. This suggests that the tuning properties of experimental IT neurons might primarily be shaped by bottom-up stimulus-space statistics, with little influence of top-down task-specific information. The population of experimental PFC neurons, on the other hand, shows tuning properties that cannot be explained just by stimulus tuning. These analyses are compatible with a model of object recognition in cortex (Riesenhuber 2000) in which a population of shape-tuned neurons provides a general basis for neurons tuned to different recognition tasks.
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Chung, Chao-Chiang, and 鍾肇強. "Current Sensorless Control for Bridgeless PFC Boost Rectifier." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/94691112933957658344.
Full textAbstract:
碩士國立交通大學
電機學院電機與控制學程
100
The conventional multi-loop control senses the input voltage, the output voltage and the inductor current, in order to yield in-phase sinusoidal current and regulate the output voltage. In this paper, the current sensorless control for bridgeless PFC boost rectifier is proposed where only the input voltage and the output voltage are sensed. The current sensorless control has one voltage loop, which simplies the control structure, and reduce the number of sensors. In this thesis, the input current waveform are analyzed and the circuit behavior is modeled with consideration of both the inductor resistance and the switch conduction voltage. From the simulation and experiment results, the measured sinusoidal current is in-phase with the input voltage evenwhen the line frequency is high to 400 Hz.
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LIN, LI-PEI, and 林立培. "Realization of an IB-HEPCS Bridgeless PFC Converter." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/9s7ygu.
Full textAbstract:
碩士國立虎尾科技大學
電機工程系碩士班
106
Amidst the rapid development of electric vehicles today, battery charging system have been one of the main focuses of research and development. Wide application of most battery charging posts in the current market are limited due to size and installation difficulty. Almost all electric vehicles batteries are charged by converting alternating current to direct current, though the charging process is slow as the power efficiency of the vehicle’s on-board charger is restricted to the size, weight and heat dissipation limits of the converter’s power circuit. Therefore, this study proposes a component that shares the electric vehicle’s power system to increase power efficiency, thereby eliminating the vehicle’s on-board charger, efficiently reducing the size of the battery charging post and increasing power efficiency at the same time. This study proposes a hybrid electric power conversion system for converting electrical energy by using both the active and passive components of the electric vehicle’s power system within the AC to DC totem-pole bridgeless power factor corrector boost converter. The core purpose of this study is to establish an Nth-coupling switching matrix for the motor driver’s active switching component. This method will allow for four voltage levels in circuit analysis to be set up, establish the control rate for switching between systems, and create a coupling switching matrix through theoretical analysis. The coupling switch is then simplified to allow for a simplifier circuit architecture through the difference in the matrix architecture, thereby achieving bridgeless power factor correction and boosting pressure. Finally, the theory is validated through circuit analysis simulation and realizing the actual circuit architecture.
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Wu, Yi-Jie, and 吳怡潔. "Study and Implementation of Active Clamp Flyback PFC." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/3p4j4u.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
107
At present, most AC-DC converters adopt a two-stage serial connection architecture, which consists of a power factor corrector and a DC-DC voltage converter to achieve a high power factor AC-DC power converter. However, because of the two-stage circuit, there is a high demand for circuit planning and component usage, and efficiency improvement is limited. In order to reduce the input current distortion, the traditional average current control method should not be too large in the output voltage loop bandwidth, so the chopping suppression effect of the output voltage is not ideal, especially the chopping of the second harmonic frequency component. Based on the traditional average current control, this paper develops a set of single-stage active clamp flyback power factor correction converters to improve the above shortcomings by the dual-loop control method. Current loop control allows the input current to follow the input voltage waveform for high power factor. The output voltage loop circuit regulates the output voltage by frequency conversion. This method can make the voltage loop loop not limited by the bandwidth, thus increasing the voltage loop bandwidth, thereby reducing the output voltage ripple. In this thesis, the single-stage active clamp flyback power factor correction converter is used as the architecture to introduce the power factor correction control method and the active clamp flyback type operation principle, and complete an input voltage of 110Vac, output voltage of 48Vdc, and output power 80W power converter verifies the theoretical results through actual circuit measurement.
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"Accurate Estimation of Core Losses for PFC Inductors." Master's thesis, 2019. http://hdl.handle.net/2286/R.I.55521.
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abstract: As the world becomes more electronic, power electronics designers have continuously designed more efficient converters. However, with the rising number of nonlinear loads (i.e. electronics) attached to the grid, power quality concerns, and emerging legislation, converters that intake alternating current (AC) and output direct current (DC) known as rectifiers are increasingly implementing power factor correction (PFC) by controlling the input current. For a properly designed PFC-stage inductor, the major design goals include exceeding minimum inductance, remaining below the saturation flux density, high power density, and high efficiency. In meeting these goals, loss calculation is critical in evaluating designs. This input current from PFC circuitry leads to a DC bias through the filter inductor that makes accurate core loss estimation exceedingly difficult as most modern loss estimation techniques neglect the effects of a DC bias. This thesis explores prior loss estimation and design methods, investigates finite element analysis (FEA) design tools, and builds a magnetics test bed setup to empirically determine a magnetic core’s loss under any electrical excitation. In the end, the magnetics test bed hardware results are compared and future work needed to improve the test bed is outlined.Dissertation/Thesis
Masters Thesis Electrical Engineering 2019
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Wu, Jung-Piao, and 吳榮標. "Noise Suppression Techniques for PFC/PWM Combo IC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/55865008013481924101.
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碩士國立臺灣科技大學
電子工程系
104
This thesis is proposed to investigate the noise suppression techniques for a PFC/PWM combo IC. When powers on, input current transient noise interferes a 400-W power supply unit’s current sampling and causes the power MOSFET malfunction or damage. Thus, the PFC circuit is modified to suppress the noise according to the measured abnormal signals. After modified, the new design circuit validated at different temperature environments, power sources, and voltage conditions is implemented. As a result of validation, the noise in input current is improved, and the most important of all, the MOSFET of power factor corrector boost circuit would not switch disorder even if the noise exists. The PFC/PWM combo IC can work normally.
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Fang, Yen-Ting, and 房彥廷. "Improving the Efficiency of Active PFC on SMPS." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/12403205282820805683.
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碩士國立高雄應用科技大學
電機工程系
97
This thesis is about the discussion and analysis of the operational principle for active power factor corrector (PFC) with discontinuous conduction mode (DCM). Meanwhile, a prototype of PFC with universal voltage input, high efficiency, and power factor close to 1 is designed, which comply with the United States Environmental Protection Agency's Energy Star 2.0 for the requirement of power factor on high power SMPS. Taguchi method is used for regulation the designing parameters to make further improvement, which can achieve the optimum design of PFC and then enhance the conversion efficiency of switching power supplies. The main contribution of this thesis is a high efficiency of active PFC has been realized and that concretely helps the energy-saving and carbon-reduction SMPS design.
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Lin, Rong-Wei, and 林熔偉. "Study and Implementation of Digital Controlled PFC Converters." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/83163556743361951027.
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碩士崑山科技大學
電機工程研究所
102
This thesis presents the design and implementation of a fully digital-controlled single-phase power factor converter (PFC). The proposed PFC controller consists of an inner current-loop controller and an outer voltage-loop controller. By using the average-current-mode control technique as inter loop controller, the problems of low power factor and high input current distortion occurred in the conventional AC/DC converter as the nonlinear load characteristic can be improved. For outer loop voltage control, PI controller is adapted to achieve the output regulation performance. Finally, an experimental test with input voltage ranging from 90VAC to 130VAC, 300V output voltage and 150W maximum output power was implemented with high performance digital signal controller dsPIC30F4011. The experimental results show that the implemented circuit achieves the expected specifications of high power factor, fast dynamic response and low total harmonic distortion.
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Shaffer, Andrew P. Raghavan Padma. "Pfftc an improved fast fourier transform for the ibm cell broadband engine /." 2009. http://etda.libraries.psu.edu/theses/approved/WorldWideIndex/ETD-4024/index.html.
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Kuo-Fan, Lin. "Design of the Improved Zero Current Switching PFC Converter." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0002-1706200511393600.
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Chen, Wei-Cheng, and 陳威成. "Current sensorless control for modified half-bridge PFC converter." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/60099960610576659240.
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碩士國立交通大學
電機學院電機與控制學程
102
This thesis presents the improvement of half-bridge power factor corrector (PFC) converter. For the main power circuit, use modified half-bridge PFC converter to replace the traditional topology. The modified structure can improve the short through problem which caused by series switching components to enhance the circuit reliability. And also, it can reduce the switching power loss which caused by the body diodes’ reverse current recovery time. Especially, the double voltage output characteristic of half bridge structure will be useful for higher voltage application. In order to simply the modified half bridge PFC control structure, the current sensorless control model would be estimated on the feasibility. First, check and compare the electrical characteristic difference of simulated result between multi-feedback control model and current sensorless control model. To estimate the electrical characteristic of current sensorless control model is good enough to be used. Finally, implement and evaluate the sample with modified half bridge PFC structure and sensorless control model.
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Lin, Kuo-Fan, and 林國藩. "Design of the Improved Zero Current Switching PFC Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/75176769361446257782.
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碩士淡江大學
電機工程學系碩士班
93
In the PFC converter design must carefully deal with the hard switching losses due to the recovery current of boost diode. There are two approaches had proposed to solve the hard switching losses issue. One is passive soft switching method and the other is active soft switching method. Practically, the passive soft switching method has been used more widely in industry, because of it has simple, low cost, and reliable. Although, the passive soft switching method has more merits but it still exists some drawbacks that need to be improved. This thesis proposes the improved zero current switching method not only to solve the hard switching issue but also to improve drawbacks of the passive soft switching method. Especially, the saturable core (Amorphous core) and a branch circuit are proposed to substitute the fixed inductor in ZCS circuit. This proposal optimizes the passive soft switching circuit and improves many drawbacks. In this thesis, besides the principle of operation is introduced in detail, the experimental results of the real implementation is compared with the hard switching PFC converter as well as others passive soft switching. According to experimental results, this proposed improved zero current switching method is proved feasible, and also improves the most of drawbacks of passive soft switching methods.
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LIANG, CHI HO, and 梁期合. "Flyback PFC Converter with Low-Frequency Voltage Ripple Reduction." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/xgh9vy.
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碩士國立臺灣科技大學
電子工程系
102
This thesis studied two circuit topologies to reduce low-frequency output ripple voltage based on flyback power factor corrector (PFC). In the first topology, a reverse ripple voltage is produced by an Inverse-Buck convertor cascode at the output side to cancel the ripple. In the other topology, a bidirectional buck-boost converter is parallel-connected at the output to absorb/ supply power and thus reduce the ripple. Due to ripple reduction, small output capacitance can be used. Therefore, electrolytic capacitor is replaced by solid-state capacitor in the prototype converter to prolong the lifetime. In this thesis, the operating principles and design considerations for the two circuit topologies are analyzed and discussed. 36 V/ 60 W laboratory prototypes are built and tested to verify the theoretical analysis.
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HSIEH, CHIH-CHANG, and 謝志昌. "Design and Implementation of 1kW PFC system power supply." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/mbbkkd.
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碩士國立高雄應用科技大學
電子工程系
105
Power factor correction(PFC) has been widely used to increase the efficiency of power transmission, especially, in the modern Green Power era. Most electromechanical machines are inductive load. This causes a non-zero difference between the phases of current and voltage and leads to power factor smaller than one, which means that the effective power would be smaller than the apparent power. In other words, the efficiency of the power transmission is smaller than 100 percent. In order to improve this problem, a power factor correction circuit has to be used, especially, in high power machines. This thesis aims to design a high power DC supply with the PFC operating in continuous current mode. According to the considerations of low cost and low harmonic distortion, the average current mode control is used, In addition, a zero-crossing AC switch using TRIAC is applied to avoid the inrush current. Aver implementation, the measured power efficiency and power factor are respectively greater than 0.95 and 0.90, for the output power among 300W and 1000W.
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Chen, Yu-Zhi, and 沈育志. "Development of interleaved control for the PFC flyback converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/wk9e39.
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碩士國立臺北科技大學
電力電子產業研發碩士專班
95
This paper presents two-phase flyback converter based on interleaved control, so as to upgrade the output power and to improve the power factor. Such interleaved control is realized via the proposed control rule. In this paper, the proposed control scheme for a 144W two-phase flyback converter, which has the rated input voltage of 110Vrms and the output voltage of 48V, is implemented by logic circuits. And, some simulation and experimental results are provided to demonstrate the effectiveness of the proposed control strategy.