Relevant bibliographies by topics / Phase locked loop (PLL) controller

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Phase locked loop (PLL) controller'

Author: Grafiati
Published: 4 June 2025
Last updated: 23 June 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Phase locked loop (PLL) controller.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Phase locked loop (PLL) controller"

1

Imran, Rajib, Monirul Islam, and Abdullah Al Kafi. "Synthesizable Digital Phase Locked Loop Implementation." Advanced Materials Research 684 (April 2013): 317–21. http://dx.doi.org/10.4028/www.scientific.net/amr.684.317.

Full text
Abstract:
Phase locked loop (PLL) is a very common circuit in the most of the electrical devices. The systems where needed clock or data recovery or frequency synthesis, PLL is the most cost effective and efficient choice that from cellular phone in our hands to the computers, televisions, radios and a different controller, PLL is everywhere. Due to ever increasing growth of the digital systems especially in the wireless communication, the Digital PLL (DPLL) has been developed to overcome the disadvantages of analog techniques such as large noise, power hungry, parameter sensitivity etc. Besides DPLL provides faster lock-in time, better testability, stability and portability over different process. The most of the resources available discussed about the theoretical model of the DPLL which is not synthesizable, that’s why a model is presented here keeping in mind that must be fully digital and synthesizable. The proposed PLL structure is fully digital, has the design flexibility with reduced hardware, low power consumption and higher power efficiency.
APA, Harvard, Vancouver, ISO, and other styles
2

Niezrecki, C., and H. H. Cudney. "Structural Control Using Analog Phase-Locked Loops." Journal of Vibration and Acoustics 119, no. 1 (1997): 104–9. http://dx.doi.org/10.1115/1.2889677.

Full text
Abstract:
A study of the application of the phase-locked loop (PLL) to modal control of mechanical structures is performed. An analog PLL circuit is used to control the vibration of a cantilevered beam with piezoelectric sensors and actuators. By using the PLL controller, strain rate feedback is provided within a narrow and distinct frequency range about the fourth mode of the beam. The controller ignores all other modes and does not affect the phase outside of the frequency range. The PLL controller provides a simple, inexpensive, and effective method to control an individual structural mode or set of modes without causing spillover.
APA, Harvard, Vancouver, ISO, and other styles
3

Vukadinović, Dinko, Tien Duy Nguyen, Cat Ho Nguyen, Nhu Lan Vu, Mateo Bašić, and Ivan Grgić. "Hedge-Algebra-Based Phase-Locked Loop for Distorted Utility Conditions." Journal of Control Science and Engineering 2019 (March 3, 2019): 1–17. http://dx.doi.org/10.1155/2019/3590527.

Full text
Abstract:
This paper presents the first application of the hedge-algebra theory in the field of grid synchronization. For this purpose, an optimized hedge-algebra controller (HAC) is developed and incorporated within the three-phase phase-locked loop (PLL) with moving average filters (MAFs) inside its feedback loop. Optimized fuzziness parameters and linguistic rule base of the HAC are obtained by a genetic algorithm using the integral of absolute error as the performance index during optimization. Calculated optimal parameter values of the HAC depend on the most frequently occurring disturbance in the electric grid. Two different PLL structures are proposed, depending on the types of disturbances occurring in the electric grid. The first structure is the conventional synchronous reference frame PLL with the nonadaptive MAF (i.e., MAF without order adjustment), but with the PI/PID controller in the phase loop replaced by the developed HAC. Such PLL structure is suitable for all analyzed disturbance types, expect for step-changes in the grid frequency. The second PLL structure introduces the adaptive MAF (i.e., MAF with order adjustment) and a new feedback signal in the output stage of the controller to achieve zero steady-state error in the case of step-changes in the grid frequency. The disturbance rejection capability of the two developed PLLs with the HAC (HAC-PLLs) is tested separately and compared experimentally with the PID- and fuzzy-controller-based PLLs.
APA, Harvard, Vancouver, ISO, and other styles
4

R, Prithiviraj, and Selvakumar J. "Non-Linear Mathematical Modelling for Phase Locked Loop." International Journal of Engineering & Technology 7, no. 4.10 (2018): 81. http://dx.doi.org/10.14419/ijet.v7i4.10.20710.

Full text
Abstract:
Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.
APA, Harvard, Vancouver, ISO, and other styles
5

B R, Mr Chethan, Punith H D, Abhishek Gowda H A, Manoj B S, and Rahul H R. "Design of Phase Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39446.

Full text
Abstract:
A Phase-Locked Loop (PLL) is a crucial feedback control system used to synchronize the phase of an output signal with a reference signal. This paper explores the design, analysis, and applications of PLLs in modern communication systems, digital circuits, and power electronics. The study covers the fundamental components of a PLL—phase detector, low-pass filter, and voltage-controlled oscillator (VCO)—and their interactions in achieving phase synchronization. Key performance parameters such as lock time, jitter, stability, and noise sensitivity are examined in detail. Furthermore, the paper discusses advanced PLL architectures, including digital PLLs (DPLLs) and all-digital PLLs (ADPLLs), highlighting their advantages in high-speed and low-power applications. Simulation and experimental results validate the theoretical analysis, demonstrating the PLL's effectiveness in frequency synthesis, clock recovery, and modulation/demodulation tasks. The findings underscore the PLL's versatility and its continued relevance in evolving technologies such as 5G networks, IoT devices, and mixed- signal integrated circuits. Key Words: Phase detector, loop filter, VCO, frequency divider.
APA, Harvard, Vancouver, ISO, and other styles
6

Telnov, A. A. "Designing a Phase-Locked Frequency Control System." LETI Transactions on Electrical Engineering & Computer Science 15, no. 7 (2022): 37–46. http://dx.doi.org/10.32603/2071-8985-2022-15-7-37-46.

Full text
Abstract:
The article is devoted to the development of a phase locked loop (PLL) system using the CD4046 integrated circuit. To achieve this goal, the principles of operation of two types of phase detectors were investigated. In the second half of the article, the main transfer functions of the PLL system are derived, an example of calculating the feedback controller is considered. The reliability of the calculation results is confirmed by modeling a computer model of a resonant voltage inverter.
APA, Harvard, Vancouver, ISO, and other styles
7

S C, Mrs Shyamala, Latish Patil, Srinivas Gowda K R, Yashwanth T, and Dhruva Kumar T R. "Realization of an All-Digital Phase-Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–7. https://doi.org/10.55041/ijsrem39448.

Full text
Abstract:
An all-digital phase locked loop (PLL) is presented in the paper. The goal of a PLL, a closed-loop control system, is to synchronize the phase and frequency of an incoming signal. Clock generation and recovery communication systems are the most flexible uses of PLL. Digital PLLs are chosen because of the greater integration of digital designs. The implementation of ADPLL utilizing a Xilinx Vivado tool and code is written in Verilog. Key Words: All Digital PLL, digitally controlled oscillator(DCO),Low Pass Filter(LPF),Increment-Decrement (ID)
APA, Harvard, Vancouver, ISO, and other styles
8

Din, Zakiud, Jianzhong Zhang, Hussain Bassi, Muhyaddin Rawa, and Yipeng Song. "Impact of Phase Locked Loop with Different Types and Control Dynamics on Resonance of DFIG System." Energies 13, no. 5 (2020): 1039. http://dx.doi.org/10.3390/en13051039.

Full text
Abstract:
In recent years, the doubly fed induction generator (DFIG) operates in a weak grid, rather than a strong grid due to the high proportion of wind energy into the power grid. The impedance interaction between the DFIG system and series and parallel compensated weak grid might cause the subsynchronous resonance (SSR) and high frequency resonance (HFR) in the DFIG system, respectively. Phase locked loop (PLL) is a popular grid synchronization technique, and the high bandwidth PLL can cause resonance at middle frequencies in the DFIG system. However, the impact of PLL types and their controller dynamics on the resonance in the DFIG system are not adequately researched. The impact of the PLL controller with different types, such as synchronous reference frame (SRF) and Lead/Lag PLL, is studied in this paper to fill this gap. Additionally, an improved PLL is proposed, which can guarantee the high phase margin and decrease the likelihood of the resonance at middle frequencies in the DFIG system under a weak grid. Moreover, the phase margin of the DFIG system impedance with an improved PLL is less sensitive to its controller parameters. Simulation and experimental results verify the effectiveness of the proposed method.
APA, Harvard, Vancouver, ISO, and other styles
9

Melikyan, V. Sh, A. A. Durgaryan, H. P. Petrosyan, and A. G. Stepanyan. "Power Efficient, Low Noise 2-5 GHz Phase Locked Loop." Electronics and Communications 16, no. 4 (2011): 66–72. http://dx.doi.org/10.20535/2312-1807.2011.16.4.244797.

Full text
Abstract:
A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead
APA, Harvard, Vancouver, ISO, and other styles
10

Adesina, Naheem Olakunle, and Ashok Srivastava. "Memristor-Based Loop Filter Design for Phase Locked Loop." Journal of Low Power Electronics and Applications 9, no. 3 (2019): 24. http://dx.doi.org/10.3390/jlpea9030024.

Full text
Abstract:
The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Phase locked loop (PLL) controller"

1

Scheibe, Niko. "Entwicklung einer monolithisch integrierten 2,44 GHz Phasenregelschleife in der LFoundry 150nm-CMOS Technologie." Master's thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-61765.

Full text
Abstract:
Die Spezifikationen und Toleranzbereiche heutiger Hochgeschwindigkeitsdatenübertragungstechnologien nehmen immer weiter an Komplexität, aufgrund der steigenden Informationsmenge, zu. Zur Verarbeitung von Daten in Frequenzbereichen oberhalb von einem Gigahertz sind Referenzsignale notwendig, welche ein äußerst geringes Phasenrauschen aufweisen um benachbarte Kanäle nicht zu beeinflussen. Diese Referenzsignale werden in Mischerschaltungen zur Modulation oder Demodulation zwischen radio frequency (RF)- und intermediate frequency (IF)-Signalen verwendet. Die benötigte Signalform ist eine Sinusschwingung, die nicht durch digitale Schaltungsblöcke erzeugt werden kann. Daher ist die Notwendigkeit von analogen LC-Oszillatoren gegeben. Die Erzeugung von höchst stabilen und hochfrequenten Signalen war lange Zeit teuren Silizium-Germanium-Technologien vorbehalten. Jedoch erfordert der steigende Integrationsgrad und der hart umkämpfte Markt, die Entwicklung von RF-Schaltungen in günstigen CMOS-Technologien. In Zusammenarbeit mit der Landshut Silicon Foundry soll dazu eine monolithisch integrierte Phase-Locked Loop (PLL) mit einer mittleren Ausgangsfrequenz von 2,44 GHz und einem Phasenrauschen kleiner -115 dBc/Hz bei einem Abstand von 1 MHz vom Träger entwickelt werden. Dabei wird das Hauptaugenmerk auf den Kern der PLL gelegt, welcher einen spannungsgesteuerten Oszillator, einen Phasen-/Frequenzdetektor, eine Ladungspumpe, einen Schleifenfilter und einen Frequenzteiler beinhaltet. Außerdem sollen Testszenarien vorgestellt werden, um die Eigenschaften der gefertigten PLL zu bestimmen und zu vergleichen.
APA, Harvard, Vancouver, ISO, and other styles
2

Eklund, Robert. "Linearization of Voltage-Controlled Oscillators in Phase-Locked Loops." Thesis, Linköping University, Department of Science and Technology, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5366.

Full text
Abstract:
<p>This is a thesis report done as part of the Master of Science in Electronics Design Engineering given at Linköping University, Campus Norrköping. The thesis work is done at Ericsson AB in the spring of 2005. The thesis describes a method of removing variations in the tuning sensitivity of voltage-controlled crystal oscillators due to different manufacturing processes. These variations results in unwanted variations in the modulation bandwidth of the phase-locked loop the oscillator is used in. Through examination of the theory of phase-locked loops it is found that the bandwidth of the loop is dependent on the tuning sensitivity of the oscillator.</p><p>A method of correcting the oscillator-sensitivity by amplifying or attenuating the control-voltage of the oscillator is developed. The size of the correction depends on the difference in oscillator-sensitivity compared to that of an ideal oscillator. This error is measured and the correct correction constant calculated.</p><p>To facilitate the measurements and correction extra circuits are developed and inserted in the loop. The circuits are both analog and digital. The analog circuits are mounted on an extra circuit board and the digital circuits are implemented in VHDL in an external FPGA.</p><p>Tests and theoretical calculations show that the method is valid and able to correct both positive and negative variations in oscillator-sensitivity of up to a factor ±2.5 times. The bandwidth of the loop can be adjusted between 2 to 15 Hz (up to ±8 dB, relative an unmodified loop).</p>
APA, Harvard, Vancouver, ISO, and other styles
3

Thomas, Renji George. "A Full Digital Phase Locked Loop." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Kim, Sinnyoung. "Analysis and Design of Radiation-Hardened Phase-Locked Loop." 京都大学 (Kyoto University), 2014. http://hdl.handle.net/2433/188872.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Parash, Par Nima. "Automotive Radar Demonstrator : Phase-locked loop and filterdesign." Thesis, Linköping University, Department of Science and Technology, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18937.

Full text
Abstract:
<p> </p><p>As technique and requirement of today’s products keeps expending, Acreo AB has been researching for automotive radar that fulfills these requirements, e.g. higher resolution, faster system and lower cost.</p><p>The purpose of this master thesis work has been to evaluate a previous design and implement changes. The work has resulted in a PCB card that will be used to compare the performance between two radar modules. The demonstrator has been developed in two versions – first based on the existing GaAs-chipset (Gallium Arsenide) and a second with the inclusion of a low cost SiGe-chipset (Silicon Germanium).</p><p>The outcome of this work proves that some requirements cannot be fulfilled and therefore a next-generation radar demonstrator has been proposed. The new radar demonstrator includes changes that can fulfill the requirements.</p><p> </p>
APA, Harvard, Vancouver, ISO, and other styles
6

Lapčík, Josef. "Kmitočtové syntezátory." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219149.

Full text
Abstract:
This diploma thesis concerns with analysis and dividing of frequency synthesizers and design of DDS, PLL synthesizers. Base types of frequency synthesizers are described including differences between methods of their operation. Base circuits of both – DDS and PLL synthesizers and other important circuits are described in details at design part of this thesis. Design of DDS and PLL synthesizer is described in particular sections. Both synthesizers are directly realized and stand-alone control applications are created. PLL synthesizer is also ready to control thru Agilent VEE program environment. Particular example application is designed in Agilent VEE. This application is used as basis of attached lab project.
APA, Harvard, Vancouver, ISO, and other styles
7

Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.

Full text
Abstract:
Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.
APA, Harvard, Vancouver, ISO, and other styles
8

Keregudadhahalli, Rajesh Kumar. "Costas PLL Loop System for BPSK Detection." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Švábeník, Petr. "Synchronizace času pomocí GPS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218601.

Full text
Abstract:
This thesis discusses about using the worldwide satellite system GPS for time and frequency synchronization. This thesis presents study about basic principles of the GPS system, its segments and ways of using this system. Some GPS receivers suitable for receiving the time marks (pulses) used for time synchronization are described. Thesis contents designing of the circuit that will receive time marks and it will digitalize and record external signal and send it with precision time information to PC for displaying and post processing. Thesis also discusses about both hardware and software development of the synchronization module and software used in PC.
APA, Harvard, Vancouver, ISO, and other styles
10

Pardo, Gonzalez Mauricio. "MEMS-based phase-locked-loop clock conditioner." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/43643.

Full text
Abstract:
Ultra narrow-band filters and the use of two loops in a cascade configuration dominate current clock conditioners based on phase-locked-loop (PLL) schemes. Since a PLL exhibits a low-pass transfer function with respect to the reference clock, the noise performance at very close-to-carrier offset frequencies is still determined by the input signal. Although better cleaning can be achieved with extremely narrow loops, an ultra low cut-off frequency could not be selected since the stability of the configuration deteriorates as the filter bandwidth is reduced. This fact suggests that a full-spectrum clock conditioning is not possible using traditional PLL architectures, and an alternative scheme is necessary to attenuate the very-close-to-carrier phase noise (PN). In addition, ultra-narrow loop filters can compromise on-chip integration because of the large size capacitors needed when chosen as passive. Input signal attenuation with relaxed bandwidth requirements becomes the main aspect that a comprehensive clock cleaner must address to effectively regenerate a reference signal. This dissertation describes the Band-Reject Nested-PLL (BRN-PLL) scheme, a modified PLL-based architecture that provides an effective signal cleaning procedure by introducing a notch in the input transfer function through inner and outer loops and a high-pass filter (HPF). This modified response attenuates the reference-signal PN and reduces the size of the loop-filter capacitors substantially. Ultra narrow loops are no longer required because the notch size is related to the system bandwidth. The associated transfer function for the constitutive blocks (phase detectors and local oscillators) show that the output close-to-carrier and far-from-carrier PN sections are mainly dominated by the noise from the inner-PLL phase detector (PD) and local oscillator (LO) located in the outer loop, respectively. The inner-PLL PD transfer function maintains a low-pass characteristic with a passband gain inversely proportional to the PD gain becoming the main contribution around the carrier signal. On the other hand, the PN around the transition frequency is determined mainly by the reference and the inner-PLL LO. Their noise contributions to the output will depend on the associated passband local maxima, which is located at the BRN-PLL transition frequency. Hence, in this region, the inner-PLL LO is selected so that its effect can be held below that of the outer-PLL PD. The BRN-PLL can use a high-Q MEMS-based VCO to further improve the transition region of the output PN profile and an LC-VCO as outer-PLL LO to reduce the noise floor of the output signal. In particular, two tuning mechanisms are explored for the MEMS-VCO: series tuning using varactors and phase shifting of a resonator operating in nonlinear regime. Both schemes are implemented to generate a tunable oscillator with no PN-performance degradation.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "Phase locked loop (PLL) controller"

1

Aktas, Adem. CMOS PLLs and VCOs for 4G wireless. Kluwer Academic Publishers, 2004.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

Unruh, Eric L. PLL: Linear Phase-Locked Loop Control System Analysis Software and User's Manual. Artech House Publishers, 1991.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Saniei, Namdar. A 20 GHz silicon germanium-HBT phase locked loop (PLL) for serial link applications. 2005.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Aktas, Adem. Cmos Plls and Vcos for 4G Wireless. Springer, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Aktas, Adem, and Mohammed Ismail. CMOS PLLs and VCOs for 4G Wireless. Springer London, Limited, 2007.

Find full text
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Phase locked loop (PLL) controller"

1

Tran, Thanh T. "Phase-Locked Loop (PLL)." In High-Speed DSP and Analog System Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6309-3_6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Ehrhardt, Dietmar. "PLL (Phase Locked Loop)." In Verstärkertechnik. Vieweg+Teubner Verlag, 1992. http://dx.doi.org/10.1007/978-3-322-83026-5_24.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Tran, Thanh T. "Phase-Locked Loop (PLL)." In High-Speed System and Analog Input/Output Design. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-04954-5_11.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Alvarado, Unai, Guillermo Bistué, and Iñigo Adín. "Phase Locked Loop (PLL) Design." In Lecture Notes in Electrical Engineering. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-22987-9_8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Margaris, Nikolaos I. "2. PLL components." In Theory of the Non-linear Analog Phase Locked Loop. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-39990-2_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Yawale, Shrikrishna, and Sangita Yawale. "Active Filter Circuits and Phase-Locked Loop (PLL)." In Operational Amplifier. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-4185-5_7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Margaris, Nikolaos I. "3. Introduction to first order PLL." In Theory of the Non-linear Analog Phase Locked Loop. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-39990-2_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Margaris, Nikolaos I. "12. Introduction to third order type – II PLL." In Theory of the Non-linear Analog Phase Locked Loop. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-39990-2_12.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Margaris, Nikolaos I. "6. Introduction to second order type – I PLL." In Theory of the Non-linear Analog Phase Locked Loop. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-39990-2_6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Margaris, Nikolaos I. "9. Introduction to second order type – II PLL." In Theory of the Non-linear Analog Phase Locked Loop. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-39990-2_9.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Phase locked loop (PLL) controller"

1

Sallah, Siti Sarah Md, Adib Irfan Hakeem Azulyzal, Emilia Noorsal, Anith Nuraini Abd Rashid, and Ahmed Saad Abdou Ahmed. "Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology." In 2024 IEEE International Conference on Applied Electronics and Engineering (ICAEE). IEEE, 2024. http://dx.doi.org/10.1109/icaee62924.2024.10667618.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Abdo, Mostafa, Mohammed Amer, and Sherif Helmy. "Comparative Analysis of Enhanced Phase-Locked Loop (PLL) Approaches for Renewable Energy Resources Integration." In 2025 15th International Conference on Electrical Engineering (ICEENG). IEEE, 2025. https://doi.org/10.1109/iceeng64546.2025.11031267.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Lan, Shi-Yue, Chih-Hsiang Chang, Tung-Sheng Chan, Po-Kai Huang, and Yue-Fang Kuo. "A 6GHz Sub-Sampling Phase-Locked Loop Using a Lock Detector Controller." In 2024 IEEE 13th Global Conference on Consumer Electronics (GCCE). IEEE, 2024. https://doi.org/10.1109/gcce62371.2024.10760284.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Han, Keyi, Ruiyang Xu, Yuyao Guo, et al. "Highly linear and stable III-V/Si3N4 FMCW laser equipped with a customized electro-optical phase-locked loop." In Optical Fiber Communication Conference. Optica Publishing Group, 2025. https://doi.org/10.1364/ofc.2025.m3j.1.

Full text
Abstract:
We demonstrate a high-performance FMCW laser source comprising a III-V/Si3N4 hybrid laser and an EO-PLL. The ranging precision is significantly improved from 4.44 m to 10.28 cm at a 300-m fiber length.
APA, Harvard, Vancouver, ISO, and other styles
5

Cheng, Jiahui, Hao Gao, Yaojun Qiao, Zhuoze Zhao, Bin Luo, and Song Yu. "Stable Unidirectional Two-way Radio Frequency Transfer over 185 km Outdoor Optical Cable Based on Dual-PLL." In CLEO: Science and Innovations. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/cleo_si.2024.sth4q.4.

Full text
Abstract:
We design a novel phase-locked loop and demonstrate stable unidirectional two-way radio frequency transfer over 185 km outdoor optical cable based on dual-PLL. The fractional frequency stability of the received signal approaches 1.18 × 10 − 14@1 s and 1.63 × 10 − 15@10000 s.
APA, Harvard, Vancouver, ISO, and other styles
6

Gilbert, A. J., M. P. Foster, D. A. Stone, and C. M. Bingham. "Phase Locked Loop (PLL) based self-oscillating controller for LCC resonant converters." In 4th IET International Conference on Power Electronics, Machines and Drives (PEMD 2008). IEE, 2008. http://dx.doi.org/10.1049/cp:20080561.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Akhtar, Mohd Afroz, Srishti Choudhury, and Suman Saha. "LQR based PI Controller Tuning for Transport Delay-Phase Locked Loop (TD-PLL)." In 2018 3rd International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH). IEEE, 2018. http://dx.doi.org/10.1109/cipech.2018.8724257.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Jamaludin, N. F., and A. F. Abidin. "Phase-Locked Loop (PLL) controller for Distribution Synchronous static compensator (D-STATCOM) to mitigate voltage flicker." In 2013 IEEE 7th International Power Engineering and Optimization Conference (PEOCO). IEEE, 2013. http://dx.doi.org/10.1109/peoco.2013.6564568.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

VanZwieten, Tannen S., James H. VanZwieten, Mark J. Balas, and Frederick R. Driscoll. "Direct Adaptive Rejection of Vortex-Induced Disturbances for a Powered Spar Platform." In ASME 2009 28th International Conference on Ocean, Offshore and Arctic Engineering. ASMEDC, 2009. http://dx.doi.org/10.1115/omae2009-79492.

Full text
Abstract:
The Rapidly Deployable Stable Platform (RDSP) is a novel vessel designed to be a reconfigurable, stable at-sea platform. It consists of a detachable catamaran and spar, performing missions with the spar extending vertically below the catamaran and hoisting it completely out of the water. Multiple thrusters located along the spar allow it to be actively controlled in this configuration. A controller is presented in this work that uses an adaptive feedback algorithm in conjunction with Direct Adaptive Disturbance Rejection (DADR) to mitigate persistent, vortex-induced disturbances. Given the frequency of a disturbance, the nominal DADR scheme adaptively compensates for its unknown amplitude and phase. This algorithm is extended to adapt to a disturbance frequency that is only coarsely known by including a Phase Locked Loop (PLL). The PLL improves the frequency estimate on-line, allowing the modified controller to reduce vortex-induced motions by more than 95% using achievable thrust inputs.
APA, Harvard, Vancouver, ISO, and other styles
10

Yadav, Uma, Anju Gupta, and Rajesh Ahuja. "Robust Control Design Procedure and Simulation of PRES Controller having Phase-Locked Loop(PLL) control technique in Grid-Tied Converter." In 2020 3rd International Seminar on Research of Information Technology and Intelligent Systems (ISRITI). IEEE, 2020. http://dx.doi.org/10.1109/isriti51436.2020.9315358.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Phase locked loop (PLL) controller' for particular source types:
Journal articles Dissertations / Theses
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography