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Journal articles on the topic 'Phase locked loop (PLL) controller'
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1
Imran, Rajib, Monirul Islam, and Abdullah Al Kafi. "Synthesizable Digital Phase Locked Loop Implementation." Advanced Materials Research 684 (April 2013): 317–21. http://dx.doi.org/10.4028/www.scientific.net/amr.684.317.
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Phase locked loop (PLL) is a very common circuit in the most of the electrical devices. The systems where needed clock or data recovery or frequency synthesis, PLL is the most cost effective and efficient choice that from cellular phone in our hands to the computers, televisions, radios and a different controller, PLL is everywhere. Due to ever increasing growth of the digital systems especially in the wireless communication, the Digital PLL (DPLL) has been developed to overcome the disadvantages of analog techniques such as large noise, power hungry, parameter sensitivity etc. Besides DPLL provides faster lock-in time, better testability, stability and portability over different process. The most of the resources available discussed about the theoretical model of the DPLL which is not synthesizable, that’s why a model is presented here keeping in mind that must be fully digital and synthesizable. The proposed PLL structure is fully digital, has the design flexibility with reduced hardware, low power consumption and higher power efficiency.
2
Niezrecki, C., and H. H. Cudney. "Structural Control Using Analog Phase-Locked Loops." Journal of Vibration and Acoustics 119, no. 1 (1997): 104–9. http://dx.doi.org/10.1115/1.2889677.
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A study of the application of the phase-locked loop (PLL) to modal control of mechanical structures is performed. An analog PLL circuit is used to control the vibration of a cantilevered beam with piezoelectric sensors and actuators. By using the PLL controller, strain rate feedback is provided within a narrow and distinct frequency range about the fourth mode of the beam. The controller ignores all other modes and does not affect the phase outside of the frequency range. The PLL controller provides a simple, inexpensive, and effective method to control an individual structural mode or set of modes without causing spillover.
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Vukadinović, Dinko, Tien Duy Nguyen, Cat Ho Nguyen, Nhu Lan Vu, Mateo Bašić, and Ivan Grgić. "Hedge-Algebra-Based Phase-Locked Loop for Distorted Utility Conditions." Journal of Control Science and Engineering 2019 (March 3, 2019): 1–17. http://dx.doi.org/10.1155/2019/3590527.
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This paper presents the first application of the hedge-algebra theory in the field of grid synchronization. For this purpose, an optimized hedge-algebra controller (HAC) is developed and incorporated within the three-phase phase-locked loop (PLL) with moving average filters (MAFs) inside its feedback loop. Optimized fuzziness parameters and linguistic rule base of the HAC are obtained by a genetic algorithm using the integral of absolute error as the performance index during optimization. Calculated optimal parameter values of the HAC depend on the most frequently occurring disturbance in the electric grid. Two different PLL structures are proposed, depending on the types of disturbances occurring in the electric grid. The first structure is the conventional synchronous reference frame PLL with the nonadaptive MAF (i.e., MAF without order adjustment), but with the PI/PID controller in the phase loop replaced by the developed HAC. Such PLL structure is suitable for all analyzed disturbance types, expect for step-changes in the grid frequency. The second PLL structure introduces the adaptive MAF (i.e., MAF with order adjustment) and a new feedback signal in the output stage of the controller to achieve zero steady-state error in the case of step-changes in the grid frequency. The disturbance rejection capability of the two developed PLLs with the HAC (HAC-PLLs) is tested separately and compared experimentally with the PID- and fuzzy-controller-based PLLs.
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R, Prithiviraj, and Selvakumar J. "Non-Linear Mathematical Modelling for Phase Locked Loop." International Journal of Engineering & Technology 7, no. 4.10 (2018): 81. http://dx.doi.org/10.14419/ijet.v7i4.10.20710.
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Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.
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B R, Mr Chethan, Punith H D, Abhishek Gowda H A, Manoj B S, and Rahul H R. "Design of Phase Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39446.
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A Phase-Locked Loop (PLL) is a crucial feedback control system used to synchronize the phase of an output signal with a reference signal. This paper explores the design, analysis, and applications of PLLs in modern communication systems, digital circuits, and power electronics. The study covers the fundamental components of a PLL—phase detector, low-pass filter, and voltage-controlled oscillator (VCO)—and their interactions in achieving phase synchronization. Key performance parameters such as lock time, jitter, stability, and noise sensitivity are examined in detail. Furthermore, the paper discusses advanced PLL architectures, including digital PLLs (DPLLs) and all-digital PLLs (ADPLLs), highlighting their advantages in high-speed and low-power applications. Simulation and experimental results validate the theoretical analysis, demonstrating the PLL's effectiveness in frequency synthesis, clock recovery, and modulation/demodulation tasks. The findings underscore the PLL's versatility and its continued relevance in evolving technologies such as 5G networks, IoT devices, and mixed- signal integrated circuits. Key Words: Phase detector, loop filter, VCO, frequency divider.
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Telnov, A. A. "Designing a Phase-Locked Frequency Control System." LETI Transactions on Electrical Engineering & Computer Science 15, no. 7 (2022): 37–46. http://dx.doi.org/10.32603/2071-8985-2022-15-7-37-46.
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The article is devoted to the development of a phase locked loop (PLL) system using the CD4046 integrated circuit. To achieve this goal, the principles of operation of two types of phase detectors were investigated. In the second half of the article, the main transfer functions of the PLL system are derived, an example of calculating the feedback controller is considered. The reliability of the calculation results is confirmed by modeling a computer model of a resonant voltage inverter.
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S C, Mrs Shyamala, Latish Patil, Srinivas Gowda K R, Yashwanth T, and Dhruva Kumar T R. "Realization of an All-Digital Phase-Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–7. https://doi.org/10.55041/ijsrem39448.
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An all-digital phase locked loop (PLL) is presented in the paper. The goal of a PLL, a closed-loop control system, is to synchronize the phase and frequency of an incoming signal. Clock generation and recovery communication systems are the most flexible uses of PLL. Digital PLLs are chosen because of the greater integration of digital designs. The implementation of ADPLL utilizing a Xilinx Vivado tool and code is written in Verilog. Key Words: All Digital PLL, digitally controlled oscillator(DCO),Low Pass Filter(LPF),Increment-Decrement (ID)
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Din, Zakiud, Jianzhong Zhang, Hussain Bassi, Muhyaddin Rawa, and Yipeng Song. "Impact of Phase Locked Loop with Different Types and Control Dynamics on Resonance of DFIG System." Energies 13, no. 5 (2020): 1039. http://dx.doi.org/10.3390/en13051039.
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In recent years, the doubly fed induction generator (DFIG) operates in a weak grid, rather than a strong grid due to the high proportion of wind energy into the power grid. The impedance interaction between the DFIG system and series and parallel compensated weak grid might cause the subsynchronous resonance (SSR) and high frequency resonance (HFR) in the DFIG system, respectively. Phase locked loop (PLL) is a popular grid synchronization technique, and the high bandwidth PLL can cause resonance at middle frequencies in the DFIG system. However, the impact of PLL types and their controller dynamics on the resonance in the DFIG system are not adequately researched. The impact of the PLL controller with different types, such as synchronous reference frame (SRF) and Lead/Lag PLL, is studied in this paper to fill this gap. Additionally, an improved PLL is proposed, which can guarantee the high phase margin and decrease the likelihood of the resonance at middle frequencies in the DFIG system under a weak grid. Moreover, the phase margin of the DFIG system impedance with an improved PLL is less sensitive to its controller parameters. Simulation and experimental results verify the effectiveness of the proposed method.
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Melikyan, V. Sh, A. A. Durgaryan, H. P. Petrosyan, and A. G. Stepanyan. "Power Efficient, Low Noise 2-5 GHz Phase Locked Loop." Electronics and Communications 16, no. 4 (2011): 66–72. http://dx.doi.org/10.20535/2312-1807.2011.16.4.244797.
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A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead
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Adesina, Naheem Olakunle, and Ashok Srivastava. "Memristor-Based Loop Filter Design for Phase Locked Loop." Journal of Low Power Electronics and Applications 9, no. 3 (2019): 24. http://dx.doi.org/10.3390/jlpea9030024.
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The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.
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Rekha, S. Sasi, and K. Arokia James Immanuvel. "Power Quality Improvement in Wind Energy Generation Using Fuzzy Logic Controller." Advanced Materials Research 984-985 (July 2014): 730–39. http://dx.doi.org/10.4028/www.scientific.net/amr.984-985.730.
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Nowadays, renewable energies have been widely applied to achieve eco friendly objectives. This paper presents the development of a single-phase grid-connected wind energy generation with the improvement in power quality and efficiency. This mainly focuses on showing the improvement in power quality by overcoming the drawbacks with the existing wind energy generation based on the PLL with the discrete PI controller. It is found that Total Harmonic Distortions (THD) present in PLL Single-phase grid-connected wind energy generation can be reduced by using modified PLL method. The modified wind energy generation is based on PLL with Fuzzy logic controller instead of PLL with discrete PI controller. The PLL gets input from the load side, and compare with any one parameters current or voltage (closed loop system). The aim of this survey is to propose a new topology in (HCM) HILL CLIMB METHOD. The tasks related to the SVPWM algorithm, the PLL, the MPPT algorithm, and the monitoring of the DC voltage were successfully implemented in the DSC. Keywords – Total Harmonic Distortions, Phase Locked Loop, Discrete PI Controller, Fuzzy logic controller, Space Vector Pulse Width Modulation, Maximum Power Point Tracking, Digital Signal Controller.
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Li, Jincheng. "Working principle and application analysis of phase-locked loop." Applied and Computational Engineering 11, no. 1 (2023): 174–80. http://dx.doi.org/10.54254/2755-2721/11/20230228.
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This article analyzes the current research status of phase-locked loops (PLLs) from multiple aspects. The working principle and components of PLL are discussed in detail, including the feedback controlling mechanism, clock skew generation and elimination, and frequency multiplication. The main components of PLL, including phase detector, low-pass filter, and voltage-controlled oscillator, are also explained in the following parts. The article further explores the applications of PLL, such as frequency synthesizers and clock and data recovery, and the challenges faced in designing PLLs. These challenges include the need for new architectures and advanced loop filters and improved phase detectors. Finally, the prospects and potential developments in PLL technology will be given. The paper will first present a comprehensive review of recent advances in PLL research, focusing on both the theoretical and practical aspects of PLL design and application. Then highlight the innovative approaches proposed by researchers to address the challenges associated with PLLs, including new architectures, advanced loop filters, and improved phase detectors.
13
Almathnani, Ali, Ali Lesewed, Jamal Alakshi, and Saleh Abuazoum. "Control of Dynamic Voltage Restorer Using Novel Fast Two Vector Phase-Locked Loops Regulator." Journal of Pure & Applied Sciences 20, no. 2 (2021): 129–36. http://dx.doi.org/10.51984/jopas.v20i2.1284.
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A fast two-vector Phase-locked loops (PLL) control has been proposed to control the phase and frequency of the grid voltage using 48-pulse switching. The novel controller senses the phase shift of the grid voltage as a frequency deviation by the load and locked to the positive sequence. The controller was designed to track the grid voltage angle and kept the grid frequency within the satisfying rang at all the time. The PI- controller was proposed to obtain the desired performance of the PLL. The fast PLL phase shift of the grid voltage. The test results shows that the new design of controller can control the response of the positive sequence between -1.75p.u to 1.75p.u. With in-phase compensation. The proposed PLL controller has been simulated by using PSCAD/EMTD software package.
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Ezzidin, Hassan Aboadla, and Hassan Ali. "180 nm NMOS voltage-controlled oscillator for phase-locked loop applications." International Journal of Informatics and Communication Technology (IJ-ICT) 12, no. 3 (2023): 236–41. https://doi.org/10.11591/ijict.v12i3.pp236-241.
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The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset and a total harmonic distortion (THD) of 3.9%. The proposed design is verified by PSpice simulations. A new criterion is proposed for optimizing NMOS LC oscillators.
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Purwanto, Aji, Iwan Setiawan, and Bambang Winardi. "DESAIN DAN IMPLEMENTASI SECOND ORDER GENERALIZED INTEGRATOR-PHASE LOCKED LOOP (SOGI-PLL) UNTUK TEGANGAN SATU FASA MENGGUNAKAN DSPIC30F4011 DENGAN KONTROL PROPORTIONAL INTEGRAL." TRANSIENT 7, no. 3 (2019): 729. http://dx.doi.org/10.14710/transient.7.3.729-736.
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Grid Side Converter (GSC) is a power converter device that have important role in electrical energy conversion systems especially in the utilization of renewable energy sources in order to be connected to the grid. Based on the grid connection requirements, the GSC should be able to operate even if the grid is experiencing interference. Based on the problem, the GSC control system technically should have ability to detect grid disturbances quickly by using Phase Locked Loop (PLL) method that can provide grid voltage information. Compared with other PLL algorithms, the Second Order Generalized Integrator-Phase Locked Loop (SOGI-PLL) has adaptive-filtering characteristics in adjusting phase information. The SOGI-PLL method in this final project will be implemented for single phase system using dsPIC30F4011 microcontroller with PI controller. PI controller is expected to make the system has a fast response to the changes that occur, because the purpose of the PLL’s own needs is to get the results of grid voltage information such as magnitude, frequency, and phase in realtime. As the results, the SOGI-PLL algorithm through the use of ZMPT101B sensor shows the magnitude, frequency, and phase information is suitable with the grid voltage. The result of phase estimation have also been implemented in the inverter product development project, so that the output voltage inverter is in phase with the grid voltage.
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Guo, Baoling, Seddik Bacha, Mazen Alamir, and Julien Pouget. "A phase-locked loop using ESO-based loop filter for grid-connected converter: performance analysis." Control Theory and Technology 19, no. 1 (2021): 49–63. http://dx.doi.org/10.1007/s11768-021-00036-0.
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AbstractAn extended state observer (ESO)-based loop filter is designed for the phase-locked loop (PLL) involved in a disturbed grid-connected converter (GcC). This ESO-based design enhances the performances and robustness of the PLL, and, therefore, improves control performances of the disturbed GcCs. Besides, the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions. The unbalanced grid is particularly taken into account for the performance analysis. A tuning approach based on the well-designed PI controller is discussed, which results in a fair comparison with conventional PI-type PLLs. The frequency domain properties are quantitatively analysed with respect to the control stability and the noises rejection. The frequency domain analysis and simulation results suggest that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency, while have better ability to attenuate high-frequency measurement noises. The phase margin decreases slightly, but remains acceptable. Finally, experimental tests are conducted with a hybrid power hardware-in-the-loop benchmark, in which balanced/unbalanced cases are both explored. The obtained results prove the effectiveness of ESO-based PLLs when applied to the disturbed GcC.
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Musengimana, Antoine, Haoyu Li, Xuemei Zheng, and Yanxue Yu. "Small-Signal Model and Stability Control for Grid-Connected PV Inverter to a Weak Grid." Energies 14, no. 13 (2021): 3907. http://dx.doi.org/10.3390/en14133907.
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This paper presents a small signal stability analysis to assess the stability issues facing PV (photovoltaic) inverters connected to a weak grid. It is revealed that the cause of the transient instabilities, either high-frequency or low-frequency oscillations, is dominated by the outer control loops and the grid strength. However, most challenging oscillations are low-frequency oscillations induced by coupling interaction between the outer loop controller and PLL (Phase-Locked Loop) when the inverter is connected to a weak grid. Therefore, the paper proposes a low-frequency damping methodology in order to enhance the high system integration, while maintaining the stability of the system. The control method uses a DC link voltage error to modulate the reference reactive current. The proposed control reduces the low-frequency coupling between the DVC (DC link voltage controller), AVC (AC voltage controller) and PLL (Phase-locked loop). According to this study’s results, the performance capability of the grid-connected PV inverter is improved and flexibility in the outer loop controller design is enhanced. The control strategy proposed in this paper is tested using the PLECS simulation software (Plexim GmbH, Zurich Switzerland) and the results are compared with the conventional method.
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Charlamov, Jevgenij. "PLL DESIGN AND INVESTIGATION IN CMOS." Mokslas - Lietuvos ateitis 2, no. 1 (2010): 54–58. http://dx.doi.org/10.3846/mla.2010.012.
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In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm2, power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.
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Charlamov, J., and R. Navickas. "Phase Locked Loop Integrated System." Solid State Phenomena 164 (June 2010): 221–26. http://dx.doi.org/10.4028/www.scientific.net/ssp.164.221.
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CMOS-MEMS integration is an indispensable technique for self-calibration of electromechanical performance to make MEMS devices independent on environmental drift or fabrication errors. The goal of single-chip integration (the “holy grail” for the semiconductor timing industry) would be to include the resonator, the oscillator, the PLL and a temperature compensation circuit (TCC) on a single silicon substrate. The current structure of silicon MEMS-based devices utilizes a stacked-die arrangement, housed in a multi-chip package [1]. MEMS-based timing circuits often use PLLs, which can succumb to phase jitter and noise at higher timing frequencies. The architecture of a charge pump phase locked loop (CPPLL) is proposed in this work. It is discussed how its functional blocks influence the overall system performance. We have performed voltage-controlled oscillator (VCO) phase noise analysis and have determined the relationship between CPPLL and VCO phase noises and have discussed the requirements and results of the accomplished design.
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Ahmed, Hafiz, Samet Biricik, Hasan Komurcugil, and Mohamed Benbouzid. "Enhanced Quasi Type-1 PLL-Based Multi-Functional Control of Single-Phase Dynamic Voltage Restorer." Applied Sciences 12, no. 1 (2021): 146. http://dx.doi.org/10.3390/app12010146.
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This paper considers the reference signal generation problem for the multi-functional operation of single-phase dynamic voltage restorers. For this purpose, a single-phase quasi type-1 phase-locked loop (QT1-PLL) is proposed. The pre-loop filter part of this PLL is composed of a frequency-fixed delayed signal cancellation method and a two-stage all-pass filter. Thanks to the frequency-fixed nature, the pre-loop filter is easy to implement and can provide rejection of any measurement offset. Moreover, this PLL benefits from the excellent harmonic robustness property of the conventional QT1-PLL. Small-signal modeling and gain tuning procedures are detailed in this paper. In order to track the reference voltage signals generated by the proposed PLL, a super-twisting sliding mode controller is also presented, which helps to achieve fast dynamic responses. Laboratory-scale prototype-based experimental studies were conducted to validate the developed reference generator and the controller. Experimental results show that the proposed method is fast in detecting and compensating any grid voltage anomalies to maintain constant load voltage despite voltage sag, swell, and harmonic distortions.
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Hassan Aboadla, Ezzidin, and Ali Hassan. "180 nm NMOS voltage-controlled oscillator for phase-locked loop applications." International Journal of Informatics and Communication Technology (IJ-ICT) 12, no. 3 (2023): 236. http://dx.doi.org/10.11591/ijict.v12i3.pp236-241.
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<p>The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset and a total harmonic distortion (THD) of 3.9%. The proposed design is verified by PSpice simulations. A new criterion is proposed for optimizing NMOS LC oscillators.</p>
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Abbas, Waseem, Zubair Mehmood, and Munkyo Seo. "A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS." Electronics 9, no. 9 (2020): 1502. http://dx.doi.org/10.3390/electronics9091502.
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A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.
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Bany Issa, Mohammad A., Zaid A. Al Muala, and Pastora M. Bello Bugallo. "Grid-Connected Renewable Energy Sources: A New Approach for Phase-Locked Loop with DC-Offset Removal." Sustainability 15, no. 12 (2023): 9550. http://dx.doi.org/10.3390/su15129550.
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Renewable Energy Sources (RES) are widely used worldwide due to their positive effect on the environment, being sustainable, low cost, and controllable. The power generated from RESs must be configured to interface and perfectly synchronize with the grid by using Power Electronics Converters (PEC). A Phase-Locked Loop (PLL) is one of the most popular synchronization techniques used due to its speed and robustness. A growing issue that results in oscillations in the estimated fundamental grid phase, frequency, and voltage amplitude is the DC-offset in the input of the PLL. This study was developed to eliminate the DC-offset in the single-phase grid synchronization using Delay Signal Cancellation (DSC) and a fixed-length Transfer Delay (TD)-based PLL. Then, the small-signal model, stability analysis, and selection of controller gains were discussed. The proposed PLL was simulated using MATLAB/Simulink. Moreover, to evaluate the proposed method, several scenarios were developed in order to compare it with other powerful PLLs in terms of performance indicators such as settling time, frequency, and phase error. As a result, the proposed PLL has the fastest dynamic response, completely rejects the DC-offset effect, and fully synchronizes with the electrical grid.
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B. S., Premananda, Dhanush T. N., Vaishnavi S. Parashar, and D. Aneesh Bharadwaj. "Design and Implementation of High Frequency and Low-Power Phase-locked Loop." U.Porto Journal of Engineering 7, no. 4 (2021): 70–86. http://dx.doi.org/10.24840/2183-6493_007.004_0006.
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Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.
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Kampitsis, Georgios E., Anastasis P. Tsoumanis, Konstantinos C. Gallos, Stavros A. Papathanassiou, and Stefanos N. Manias. "Experimental Investigation of the Response of Different PLL Algorithms to Grid Disturbances." Materials Science Forum 856 (May 2016): 291–96. http://dx.doi.org/10.4028/www.scientific.net/msf.856.291.
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In this paper, the performance of three different phase locked loop (PLL) algorithms is experimentally evaluated in a grid connected photovoltaic inverter. Robust PLL is a key requirement for ensuring system compatibility with existing grid codes. The double second order generalized integrator (DSOGI) and the decoupled double synchronous reference frame (DDSRF) PLL are compared against the conventional synchronous reference frame (SRF) PLL under grid disturbances. All synchronization algorithms are initially simulated in Matlab and subsequently transformed in discrete time for implementation in the digital controller. Grid distortions, such as phase voltage sags, frequency fluctuations and voltage harmonic distortion are emulated via a controllable three phase generator.
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Nikitin, Y., and G. Tsygankov. "Modeling PLL Loop with Nonlinearity." Telecom IT 7, no. 4 (2019): 9–14. http://dx.doi.org/10.31854/2307-1303-2019-7-4-9-14.
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A model of a pulse phase-locked loop multiplying ring in a MicroCap11 medium is considered. The analysis uses a nonlinear model of a voltage-controlled oscillator with a user-defined control characteristic. An RS-trigger is used as a pulse-phase detector, a pulse counter in the negative feedback circuit is implemented on JK-triggers. Transient processes in the ring, as well as the spectrum of the output oscillations in the steady (stationary) mode are considered.
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Lee, Tzung-Je, and Chua-Chin Wang. "A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators." VLSI Design 2008 (September 24, 2008): 1–8. http://dx.doi.org/10.1155/2008/512946.
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A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper. Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively. By using separate regulators, the area and the power consumption of the regulator can be reduced. Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise. The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process. The peak-to-peak jitter (P2P jitter) of the proposed PLL is measured to be 81.8 ps at 80 MHz when a 250 mVrms supply noise is added. By contrast, the P2P jitter is measured to be 118.2 ps without the two regulators when the same supply noise is coupled.
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Zhao, Xinghua, Zhanchao Liu, Xinda Song, Jianli Li, and Yibo Shao. "LADRC-Based Magnetic Field Measurement Method for a Nuclear Magnetic Resonance Rotation Sensor." Applied Sciences 11, no. 21 (2021): 10458. http://dx.doi.org/10.3390/app112110458.
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Magnetic field measurement is fundamental to nuclear magnetic resonance rotation sensors (NMRRS). A phase-locked loop (PLL)-based measurement with two nuclear isotopes is commonly applied to observe the magnetic field. However, the phase-loop and frequency-loop of the nuclear isotopes cannot be optimized simultaneously by a PLL-based method. In this paper, an approach based on a linear active disturbance rejection controller (LADRC) is proposed for synchronous phase-loop control of the two nuclear isotopes. Meanwhile, the frequencies of the nuclear isotopes are observed by linear extended state observers (LESOs). The phase and frequency loops can be decoupled and optimized with the proposed method. An experimental NMRRS prototype used for verification is built. The effectiveness and the feasibility of the proposed method are validated with the experimental results.
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Jeraputra, Chuttchaval, Jetnarong Pongpaiboon, Thamvarit Singhavilai, and Supun Tiptipakorn. "Phase Lead-Lag Synchronous Reference Frame Phase-locked loop for Grid Synchronization of a Single-Phase Inverter." ECTI Transactions on Electrical Engineering, Electronics, and Communications 20, no. 1 (2022): 123–32. http://dx.doi.org/10.37936/ecti-eec.2022201.246117.
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In this study, a phase lead-lag synchronous reference frame phase-locked loop (SRF-PLL) is proposed for the grid connection of a single-phase inverter. A tuned filter is employed to enable the phase of the input voltage to be advanced or delayed by ±45 degrees with respect to the grid voltage. The generated orthogonal signals are fed into Park's transformation. Only the quadrature-phase signal is regulated to zero using a PI controller. Its output determines the estimated frequency. The phase angle is obtained by integrating the estimated frequency. The linearized model of the proposed SRF-PLL is developed and stability analysis is discussed. The viability of the proposed method is tested under computer simulation using MATLAB/Simulink. The method is then implemented on a 32-bit microcontroller and tested with a programmable AC source. The results positively confirm the effectiveness of the method.
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Abhuday, Parasar* Megha Kimothi. "DESIGN IMPLEMENTATION OF DIGITAL FM MODULATOR & DEMODULATOR FOR SDR USING FPGA." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 7, no. 3 (2018): 178–86. https://doi.org/10.5281/zenodo.1194275.
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This paper represents the recent advancement in the chip technology is integrating several sequential elements in System on Chip (SoC). But most of the circuits are using traditional clock distribution networks and facing the problem of skew and jitter problems. The clock signal generated by the oscillators and the flip-flops and registers are not receiving the clock pulse at the accurate time. The problem can be solved using Network of Phase-Locked Loop (PLL) oscillators coupled in phase. A phase locked loop ensures that the clock frequencies seen at the clock inputs of various registers and flip-flops match the frequency generated by the oscillator. The popular technique to demodulate FM signal is Phase Locked Loop (PLL). The existing technologies are based on software defined radio (SDR) [7, 8] and the demand needs programmable SDR instead of analog SDR. In SDR, Programmable digital devices are used and they transmit and receive the baseband signal at radio frequency. The recent cellular devices follow the communication protocol and provide connectivity to end user anywhere in the particular region.The design approach is based on digital components rather than analog components such as phase detector, loop filter and Voltage Controlled Oscillator (VCO). The signal is presented using digital words instead of analog voltages. In digital FM receiver, PLL is the main part to capture and lock the signals at different frequency and phase. The main purpose of PLL is to maintain the coherence between the modulated signal frequency (f<sub>i</sub>) and the respective frequency (f<sub>o</sub>), with the concept of phase comparison. PLL permits to track the frequency changes of applied input signals, as it is locked once. The paper focuses on the design, FPGA implementation of FM receiver integrated with digital PLL. There is a use of 8 bit analog to digital conversion (ADC) circuit, which is accepting frequency modulated signal as a series of digital numerical values. The same signals are demodulated by the receiver on every clock cycle. The paper proposed the design and FPGA implementation of digital PLL and programmable all FM receiver. The design is developed in Xilinx 14.2 ISE software and simulated in Modelsim 10.1b software with the help of VHDL programming language and the targeted onVirtex-5 FPGA.
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Xu, Tao. "Application and Research of Voltage-Controlled Oscillator in Phase-Locked Loop." Highlights in Science, Engineering and Technology 106 (July 16, 2024): 13–21. http://dx.doi.org/10.54097/70mg4863.
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The first PLL chip in history was created by some researchers in the middle of the 1960s. PLL has significant uses in numerous industries, including communication and aerospace, because to its clear benefits. It can accomplish a wide range of tasks at a reasonable cost. This paper delves into the application and study of Voltage-Controlled Oscillators (VCOs) within Phase-Locked Loops (PLLs), crucial components in modern communication technology. Various VCO design techniques, including Colpitts, Clapp, ring oscillator, and CMOS VCOs, are analyzed with a focus on performance metrics such as phase noise and tuning range. The research also presents innovative high-performance VCO designs, showcasing advancements in frequency switching and phase noise reduction. Practical applications of VCOs within PLLs are explored through case studies, highlighting their role in aerospace sensorless control schemes and communication system distributed beamforming. The paper underscores the significance of VCOs in achieving stable frequency outputs and enhancing system performance, offering insights into future advancements in communication technology. Through detailed analysis and case studies, The goal of this research is to support the continuous improvement and enhancement of VCOs in PLL systems.
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Osmany, S. A., F. Herzel, K. Schmalz, and W. Winkler. "Phase noise and jitter modeling for fractional-N PLLs." Advances in Radio Science 5 (June 13, 2007): 313–20. http://dx.doi.org/10.5194/ars-5-313-2007.
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Abstract. We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filtered by the PLL operation. We express the rms phase error (jitter) in terms of phase noise of the reference, the VCO phase noise and the third-order loop filter parameters. In addition, we consider OFDM systems, where the PLL phase noise is reduced by digital signal processing after down-conversion of the RF signal to baseband. The rms phase error is discussed as a function of the loop parameters. Our model drastically simplifies the noise optimization of the PLL loop dynamics.
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Chatterjee, Basab, Surjadeep Sarkar, and Falguni Sinhababu. "Modification over Dithered DPLL to reduce the effect of narrowband channel interference." YMER Digital 21, no. 06 (2022): 383–91. http://dx.doi.org/10.37896/ymer21.06/37.
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Digital signal processing based digital phase locked loop (DSP DPLL) are most commonly used for carrier phase tracking in the recent times. Phase locked loop (PLL) behaves in nonlinear fashion at the time of signal acquisition. The linearity is restored in the PLL behavior once acquisition is over and signal tracking is taking place. But the same PLL or DSP-DPLL shows non-linearity both during acquisition and tracking when narrowband channel interference is present in the received signal. In this paper, a single tone signal is introduced as channel interference to study the effect on DPLL and its modified versions. To overcome the effect of channel interference, a single tone dither signal is included in the loop of DPLL. Although an improvement in acquisition and tracking performance is observed, but addition of dither signal contributes to the phase error variance and consequently output noise to increase. Therefore, a further modification is proposed by incorporating an additional phase control in the digital control oscillator (DCO) of the loop to improve the output SNR. The proposed loop is implemented on reconfigurable logic platform using System Generator, a tool from Xilinx used to design real time DSP application. The hardware simulation results demonstrate a comparison among traditional DPLL, dithered DPLL and phase controlled dithered DPLL where the proposed version of the loop outperforms others in terms of acquisition and noise rejection. Keywords DSP Digital Phase Locked Loop, Phase Controlled DPLL, Channel Interference, Dither DPLL, VHDL System Design, Modified DCO
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Chemidi, A., M. C. Benhabib, and M. A. Bourouis. "Performance improvement of shunt active power filter based on indirect control with a new robust phase-locked loop." Electrical Engineering & Electromechanics, no. 4 (July 8, 2022): 51–56. http://dx.doi.org/10.20998/2074-272x.2022.4.07.
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Introduction. Since the development of the first active power filter (APF) in 1976, many efforts have been focused on improving the performances of the APF control as the number of different nonlinear loads has continued to increase. These nonlinear loads have led to the generation of different types of current harmonics, which requires more advanced controls, including robustness, to get an admissible total harmonic distortion (THD) in the power system. Purpose. The purpose of this paper is to develop a robust phase-locked loop (PLL) based on particle swarm optimization-reference signal tracking (PSO-RST) controller for a three phase three wires shunt active power filter control. Methodology. A robust PLL based on PSO-RST controller insert into the indirect d-q control of a shunt active power filter was developed. Results. Simulation results performed under the MATLAB/SimPowerSystem environment show a higher filtering quality and a better robustness compared to the classical d-q controls. Originality. Conventional PLLs have difficulty determining the phase angle of the utility voltage sources when grid voltage is distorted. If this phase angle is incorrectly determined, this leads to a malfunction of the complete control of the active power filters. This implies a bad compensation of the current harmonics generated by the nonlinear loads. To solve this problem we propose a robust and simple PLL based on PSO-RST controller to eliminate the influence of the voltage harmonics. Practical value. The proposed solution can be used to improve the functioning of the shunt active power filter and to reduce the amount of memory implementation.
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CHALLAL, Mouloud, Abderrahmane OUADI, Hamid BENTARZI, Abderazak CHERFI, and Omar SAIDI. "Design and Implementation of a Digital Phase Locked Loop for GPS Synchronization." Algerian Journal of Signals and Systems 10, no. 1 (2025): 18–23. https://doi.org/10.51485/ajss.v10i1.233.
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In this paper, a Digital Phase-Locked Loop (DPLL) for GPS synchronization is designed, implemented and tested. It consists of a Phase Frequency Detector (PFD), an RC Low-Pass Filter (LPF), and a Relaxation Voltage Controlled Oscillator (VCO). The analysis, design, and examination of each block are carried out, resulting in a successful assembly of the entire DPLL circuit. The designed PLL is simulated, measured, and then compared with the experimental observations using LM565 IC. The findings demonstrate the PLL capability to achieve frequency synchronization with minimal phase error at the desired frequency of 1 KHz, along with a wide lock-in range.
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Zsigmond, Andor-Attila, and András Kelemen. "Implementation of Grid Synchronization Methods on a Real Time Development System." Acta Universitatis Sapientiae, Electrical and Mechanical Engineering 13, no. 1 (2021): 52–67. http://dx.doi.org/10.2478/auseme-2021-0005.
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Abstract The paper presents a study regarding the implementation of two representative grid synchronization methods, intended to be used in the control structure of a three phase switch mode voltage rectifier. The methods considered are the Synchronous Reference Frame Phase Locked Loop (SRF PLL) and the Double Synchronous Frame Phase Locked Loop (DSRF PLL), respectively. These synchronization methods have been compared on a real time development system type dSpace 1104 from the point of view of their performance in case of an unbalanced mains voltage system. Finally, the influence of the chosen grid synchronization method on the performance of a synchronous reference frame controlled three-phase switch mode voltage rectifier is studied by simulation, and better results are demonstrated to be provided by the use of the DSRF PLL.
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Tsai, Ming-Fa, Chung-Shi Tseng, and Bor-Yuh Lin. "Phase Voltage-Oriented Control of a PMSG Wind Generator for Unity Power Factor Correction." Energies 13, no. 21 (2020): 5693. http://dx.doi.org/10.3390/en13215693.
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This paper presents the power factor control of a permanent magnet synchronous wind generator (PMSG) wind turbine using a phase voltage-oriented control (PVOC) scheme, which is different from the conventional rotor flux-oriented control (RFOC) method and without using a rotor position sensor or sensorless estimator. The proposed control system is operated in two separately synchronously rotating d-q frames. One is for a phase-locked loop (PLL) and the other is for the PVOC current control loop. A PI controller functioned as a low-pass filter in the PLL loop is designed for extracting the phase voltage angle for the coordinate transformation between the stationary α-β frame and the synchronously rotating d-q frame in the PVOC control loop. The d-q modeling of the PMSG with the three-phase voltage vector aligned on the d-axis is then derived and based on which an another PI controller followed by decoupling control is designed, so that the three-phase currents are in phase with the three-phase output voltages of the wind generator for unity power factor correction. The simulation results in PSIM show the performance of the proposed control system which is also experimentally verified by using a TI TMS320F28335 digital control chip.
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A., Chemidi, C. Benhabib M., and A. Bourouis M. "Performance improvement of shunt active power filter based on indirect control with a new robust phase-locked loop." Electrical Engineering & Electromechanics, no. 4 (July 8, 2022): 51–56. https://doi.org/10.20998/2074-272X.2022.4.07.
Full textAbstract:
<strong><em>Introduction.</em></strong> <em>Since the development of the first active power filter (APF) in 1976, many efforts have been focused on improving the performances of the APF control as the number of different nonlinear loads has continued to increase. These nonlinear loads have led to the generation of different types of current harmonics, which requires more advanced controls, including robustness, to get an admissible total harmonic distortion (THD) in the power system</em>. <strong><em>Purpose.</em></strong> <em>The purpose of this paper is to develop a robust phase-locked loop (PLL) based on particle swarm optimization-reference signal tracking (PSO-RST) controller for a three phase three wires shunt active power filter control.</em> <strong><em>Methodology.</em></strong> <em>A robust PLL based on PSO-RST controller insert into the indirect d-q control of a shunt active power filter <strong>was</strong> developed. <strong>Results.</strong> Simulation results performed under the MATLAB/SimPowerSystem environment show a higher filtering quality and a better robustness compared to the classical d-q controls.</em> <strong><em>Originality.</em></strong> <em>Conventional PLLs have difficulty determining the phase angle of the utility voltage sources when grid voltage is distorted. If this phase angle is incorrectly determined, this leads to a malfunction of the complete control of the active power filters. This implies a bad compensation of the current harmonics generated by the nonlinear loads. To solve this problem we propose a robust and simple PLL based on PSO-RST controller to eliminate the influence of the voltage harmonics.</em> <strong><em>Practical value.</em></strong> <em>The proposed solution can be used to improve the functioning of the shunt active power filter and to reduce the amount of memory implementation.</em>
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Wang, Yan Wen, and Yan Hua Jiang. "Research on Detection and Control Strategy for UPQC without PLL in Coal Mine." Applied Mechanics and Materials 448-453 (October 2013): 3942–46. http://dx.doi.org/10.4028/www.scientific.net/amm.448-453.3942.
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To improve the power quality of power grid in coal mine, a kind of detection and control method for unified power quality controller (UPQC) without phase locked loop (PLL) is put forward. It can get the positive-sequence component of unity fundamental voltage through Park transformation,and then obtains the positive-sequence active component of fundamental current after proper operation . The PLL or filtering of three-phase voltage and the synchronous coordinates transformation for current are cancelled. The control strategy of the system is studied and the effectiveness and validity of UPQC are verified by simulation results.
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M., El malah, Ba-razzouk A., Guisser M., Abdelmounim E., and Madark M. "Backstepping based power control of a three-phase single-stage grid-connected PV system." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 6 (2019): 4738–48. https://doi.org/10.11591/ijece.v9i6.pp4738-4748.
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In order to reduce costs while maintaining superior performance, this paper presents a new control methodology of a three-phase grid connected photovoltaic system without using the intermediary DC/DC converter. Based on the synchronized nonlinear model of the whole photovoltaic system, two controllers have been proposed for the three-phase inverter in order to ensure the operation of the PV system at the maximum power point with unity power factor and minimum grid disturbance. Grid synchronization has been ensured by a three-phase 2nd order PLL (Phase-Locked Loop). The stability of each controller is demonstrated by means of Lyapunov analysis and evaluated under changing atmospheric conditions using the Matlab/Simulink environment, the simulation results clearly demonstrate the performance provided by each controller.
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Shepherd, Paul, Ashfaqur Rahman, Shamim Ahmed, A. Matt Francis, Jim Holmes, and H. Alan Mantooth. "500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (2014): 000076–83. http://dx.doi.org/10.4071/hitec-tp15.
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Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.
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Chutpipat, Chaichomnan, and Khumsat Phanumas. "A 1.8 V 25 Mbps CMOS single-phase, phase-locked loop-based BPSK, QPSK demodulator." A 1.8 V 25 Mbps CMOS single-phase, phase-locked loop-based BPSK, QPSK demodulator 13, no. 6 (2023): 6102–17. https://doi.org/10.11591/ijece.v13i6.pp6102-6117.
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A single-phase binary/quadrature phase-shift keying (BPSK/QPSK) demodulator basing on a phase-locked loop (PLL) is described. The demodulator relies on a linear characteristic a rising-edge RESET/SET flipflop (RSFF) employed as a phase detector. The phase controller takes the average output from the RSFF and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for a multiple-PSK (m-PSK) signal. Symbol-error rate analysis has also been extensively carried out. The proposed BPSK and QPSK demodulators have been fabricated in a 0.18 m digital complementary metal–oxide–semiconductor (CMOS) process where they operate from a single supply of 1.8 V. At a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum symbol rates of 25 and 12.5 Msymb/s while consuming 0.68 and 0.79 mW, respectively. At these maximum symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 7.9×10-10 and 9.8×10-10, respectively where their corresponding energy per bit figures were at 27.2 and 31.7 pJ.
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Faragalla, Asmaa, Omar Abdel-Rahim, Mohamed Orabi, and Esam H. Abdelhameed. "Enhanced Virtual Inertia Control for Microgrids with High-Penetration Renewables Based on Whale Optimization." Energies 15, no. 23 (2022): 9254. http://dx.doi.org/10.3390/en15239254.
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High penetration of renewable energy sources into isolated microgrids (µGs) is considered a critical challenge, as µGs’ operation at low inertia results in frequency stability problems. To solve this challenge, virtual inertia control based on an energy storage system is applied to enhance the inertia and damping properties of the µG. On the other hand, utilization of a phase-locked loop (PLL) is indispensable for measuring system frequency; however, its dynamics, such as measurement delay and noise generation, cause extra deterioration of frequency stability. In this paper, to improve µG frequency stability and minimize the impact of PLL dynamics, a new optimal frequency control technique is proposed. A whale optimization algorithm is used to enhance the virtual inertia control loop by optimizing the parameters of the virtual inertia controller with consideration of PLL dynamics and the uncertainties of system inertia. The proposed controller has been validated through comparisons with an optimized virtual inertia PI controller which is tuned utilizing MATLAB internal model control methodology and with H∞-based virtual inertia control. The results show the effectiveness of the proposed controller against different operating conditions and system disturbances and uncertainties.
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Kebe, Mamady, and Mihai Sanduleanu. "A Low-Phase-Noise 8 GHz Linear-Band Sub-Millimeter-Wave Phase-Locked Loop in 22 nm FD-SOI CMOS." Micromachines 14, no. 5 (2023): 1010. http://dx.doi.org/10.3390/mi14051010.
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Low-phase noise and wideband phased-locked loops (PLLs) are crucial for high-data rate communication and imaging systems. Sub-millimeter-wave (sub-mm-wave) PLLs typically exhibit poor performance in terms of noise and bandwidth due to higher device parasitic capacitances, among other reasons. In this regard, a low-phase-noise, wideband, integer-N, type-II phase-locked loop was implemented in the 22 nm FD-SOI CMOS process. The proposed wideband linear differential tuning I/Q voltage-controlled oscillator (VCO) achieves an overall frequency range of 157.5–167.5 GHz with 8 GHz linear tuning and a phase noise of −113 dBc/Hz @ 100 KHz. Moreover, the fabricated PLL produces a phase noise less than −103 dBc/Hz @ 1 KHz and −128 dBc/Hz @ 100 KHz, corresponding to the lowest phase noise generated by a sub-millimeter-wave PLL to date. The measured RF output saturated power and DC power consumption of the PLL are 2 dBm and 120.75 mW, respectively, whereas the fabricated chip comprising a power amplifier and an integrated antenna occupies an area of 1.25 × 0.9 mm2.
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Hafid, Abdul. "Pengaruh Penalaan Pengontrol PID Phase-Locked Loop (PLL) Grid Tie Inverter Terhadap Transfer Daya Ke Grid." CYCLOTRON 7, no. 01 (2024): 1–7. http://dx.doi.org/10.30651/cl.v7i01.20195.
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Makalah ini menjelaskan pengaruh tuning pengontrol Grid Tie Inverter PID Phase-Locked Loop (PLL) terhadap transfer daya ke jaringan. Penyetelan pengontrol menggunakan metode sensitivitas ultimate  Ziegler-Nichols. Grid Tie Inverter umumnya digunakan untuk menyinkronkan PV array dengan jaringan listrik PLN/Grid. Simulasi menggunakan Simulink Matlab model 250 kW PV array yang terhubung ke jaringan listrik. Simulasi dijalankan pada Matlab R2019a menggunakan PC dengan prosesor i7 4790- Ram 4 GB. Berdasarkan hasil simulasi, jika gain pengontrol diatur dengan konstanta KP =100, konstanta integral KI =400 dan konstanta turunan KD = 250 maka daya keluaran PV array yang masuk ke Grid melalui inverter sangat berfluktuasi walaupun kondisi iradiasi matahari yang jatuh ke permukaan panel surya tetap konstan. Hal yang sama terjadi jika penguatan pengontrol PID diatur dengan nilai KP =100, KI =300 dan KD =150. Jika gain pengontrol PID diatur pada nilai KP = 0.5, KI =2 dan KD =2, maka terlihat bahwa daya keluaran inverter stabil. Berdasarkan hasil pengujian kelima gain tuning inverter PID Phase-Locked Loop inverter PV dengan menggunakan metode sensitivitas ultimate Ziegler-Nichols, hasilnya semuanya berhasil yaitu transfer daya dari PV array ke jaringan listrik berjalan dengan baikKata kunci: PID controller, Phase-Locked Loop, Ziegler-Nichols, Grid Tie Inverter  Â
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Kang, Jin-Wook, Ki-Woong Shin, Hoon Lee, Kyung-Min Kang, Jintae Kim, and Chung-Yuen Won. "A Study on Stability Control of Grid Connected DC Distribution System Based on Second Order Generalized Integrator-Frequency Locked Loop (SOGI-FLL)." Applied Sciences 8, no. 8 (2018): 1387. http://dx.doi.org/10.3390/app8081387.
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This paper studies a second order generalized integrator-frequency locked loop (SOGI-FLL) control scheme applicable for 3-phase alternating current/direct current (AC/DC) pulse width modulation (PWM) converters used in DC distribution systems. The 3-phase AC/DC PWM converter is the most important power conversion system of DC distribution, since it can boost 380 Vrms 3-phase line-to-line AC voltage to 700 Vdc DC output with various DC load devices and grid voltages. The direct-quadrature (d-q) transformation, positive sequence voltage extraction, proportional integral (PI) voltage/current control, and phase locked loop (PLL) are necessary to control the 3-phase AC/DC PWM converter. Besides, a digital filter, such as low pass filter and all pass filter, are essential in the conventional synchronous reference frame-phase locked loop (SRF-PLL) method to eliminate the low order harmonics of input. However, they limit the bandwidth of the controller, which directly affects the output voltage and load of 3-phase AC/DC PWM converter when sever voltage fluctuation, such as sag, swell, etc. occurred in the grid. On the other hand, the proposed control method using SOGI-FLL is able to do phase angle detection, positive sequence voltage extraction, and harmonic filtering without additional digital filters, so that more stable and fast transient control is achieved in the DC distribution system. To verify the improvement of the characteristics in the unbalanced voltage and frequency fluctuation of the grid, a simulation and experiment are implemented with 50 kW 3-phase AC/DC PWM converter used in DC distribution.
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Malah, M. El, A. Ba-razzouk, M. Guisser, E. Abdelmounim, and M. Madark. "Backstepping Control for MPPT and UPF of a Three Phase Single Stage Grid Connected PV System." IAES International Journal of Robotics and Automation (IJRA) 7, no. 4 (2018): 262. http://dx.doi.org/10.11591/ijra.v7i4.pp262-272.
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<span>This paper presents a new control methodology of a three phase grid connected photovoltaic system without using the intermediary DC/DC converter. Based on the synchronized nonlinear model of the whole photovoltaic system, two controllers have been proposed for the three-phase inverter in order to ensure the operation of the PV system at the maximum power point with unity power factor and minimum grid disturbance. Grid synchronization has been ensured by a three-phase 2<sup>nd</sup> order PLL (Phase-Locked Loop). The stability of each controller is demonstrated by means of Lyapunov analysis and evaluated under changing atmospheric conditions using the Matlab/Simulink environment, the simulation results clearly demonstrate the performance provided by each controller.</span>
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Malah, Mohammed El, Abdellfattah Ba-razzouk, M’hammed Guisser, Elhassane Abdelmounim, and Mhamed Madark. "Backstepping based power control of a three-phase Single-stage Grid-connected PV system." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 6 (2019): 4738. http://dx.doi.org/10.11591/ijece.v9i6.pp4738-4748.
Full textAbstract:
In order to reduce costs while maintaining superior performance, this paper presents a new control methodology of a three-phase grid connected photovoltaic system without using the intermediary DC/DC converter. Based on the synchronized nonlinear model of the whole photovoltaic system, two controllers have been proposed for the three-phase inverter in order to ensure the operation of the PV system at the maximum power point with unity power factor and minimum grid disturbance. Grid synchronization has been ensured by a three-phase 2<sup>nd</sup> order PLL (Phase-Locked Loop). The stability of each controller is demonstrated by means of Lyapunov analysis and evaluated under changing atmospheric conditions using the Matlab/Simulink environment, the simulation results clearly demonstrate the performance provided by each controller.
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Arun, K., and K. Selvajyothi. "Single Phase Variable Sampling Phase Locked Loop using Composite Observer." Indonesian Journal of Electrical Engineering and Computer Science 2, no. 1 (2016): 49. http://dx.doi.org/10.11591/ijeecs.v2.i1.pp49-60.
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<p>An observer based variable sampling period phase locked loop is introduced for grid connected systems. The composite observer acts as an efficient estimator of the fundamental components from a periodic input signal rich in DC and harmonics. The observer gains are designed using pole placement technique, which inherently ensures the stability of this estimator. Even under drift frequency, a constant number of samples (512) per cycle are maintained with the help of the numerically controlled oscillator. This makes the oscillator gain elements in the observer a constant and eliminates the trigonometric computation. This phase locked loop is found to be working in a wide range of frequency 40 – 70Hz. The performance of the proposed scheme is studied with a synthetic harmonic rich signal as well as validated by implementing the PLL in Cyclone IV FPGA with a real time grid voltage.</p>
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H, Thejusraj, Prithivi Raj, J. Selvakumar, and S. Praveen Kumar. "Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop." International Journal of Engineering & Technology 7, no. 3.12 (2018): 871. http://dx.doi.org/10.14419/ijet.v7i3.12.16553.
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This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.