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Dissertations / Theses on the topic 'Phase Locked Loop (PLL)'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Thomas, Renji George. "A Full Digital Phase Locked Loop." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406.

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2

Kim, Sinnyoung. "Analysis and Design of Radiation-Hardened Phase-Locked Loop." 京都大学 (Kyoto University), 2014. http://hdl.handle.net/2433/188872.

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3

Parash, Par Nima. "Automotive Radar Demonstrator : Phase-locked loop and filterdesign." Thesis, Linköping University, Department of Science and Technology, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18937.

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<p> </p><p>As technique and requirement of today’s products keeps expending, Acreo AB has been researching for automotive radar that fulfills these requirements, e.g. higher resolution, faster system and lower cost.</p><p>The purpose of this master thesis work has been to evaluate a previous design and implement changes. The work has resulted in a PCB card that will be used to compare the performance between two radar modules. The demonstrator has been developed in two versions – first based on the existing GaAs-chipset (Gallium Arsenide) and a second with the inclusion of a low cost SiGe-chip

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4

Keregudadhahalli, Rajesh Kumar. "Costas PLL Loop System for BPSK Detection." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515.

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5

SINGH, GUNEET. "HIGH-FREQUENCY CHARGE-PUMP BASED PHASE-LOCKED LOOP DESIGN AND IT'S CHARACTERIZATION USING VERILOG-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155077793.

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6

Pardo, Gonzalez Mauricio. "MEMS-based phase-locked-loop clock conditioner." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/43643.

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Ultra narrow-band filters and the use of two loops in a cascade configuration dominate current clock conditioners based on phase-locked-loop (PLL) schemes. Since a PLL exhibits a low-pass transfer function with respect to the reference clock, the noise performance at very close-to-carrier offset frequencies is still determined by the input signal. Although better cleaning can be achieved with extremely narrow loops, an ultra low cut-off frequency could not be selected since the stability of the configuration deteriorates as the filter bandwidth is reduced. This fact suggests that a full-spectr

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7

Lei, Feiran. "Injection Locked Synchronous Oscillators (SOs) and Reference Injected Phase-Locke Loops (PLL-RIs)." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492789278258943.

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8

Bolucek, Muhsin Alperen. "Design And Implementation Of Low Phase Noise Phase Locked Loop Based Local Oscillator." Master's thesis, METU, 2009. http://etd.lib.metu.edu.tr/upload/12611353/index.pdf.

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In this thesis, a low phase noise local oscillator operating at 2210 MHz is designed and implemented to be used in X-Band transmitter of a LEO satellite. Designed local oscillator is a PLL (Phase Locked Loop) based frequency synthesizer which is implemented using discrete commercial components including ultra low noise voltage controlled oscillator and high resolution, low noise fractional-N synthesizer. Operational settings of the synthesizer are done using three wire serial interface of a microcontroller. Although there are some imperfections in the implementation, phase noise of the prototy

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9

Kippenberger, Roger Miles. "On Real Time Digital Phase Locked Loop Implementation with Application to Timing Recovery." Thesis, University of Canterbury. Electrical and Computer Engineering, 2006. http://hdl.handle.net/10092/1146.

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In digital communication systems symbol timing recovery is of fundamental importance. The accuracy in estimation of symbol timing has a direct effect on received data error rates. The primary objective of this thesis is to implement a practical Digital Phase Locked Loop capable of accurate synchronisation of symbols suffering channel corruption typical of modern mobile communications. This thesis describes an all-software implementation of a Digital Phase Locked in a real-time system. A timing error detection (TED) algorithms optimally implemented into a Digital Signal Processor. A real-time

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10

Wali, Naveen, and Balamurali Radhakrishnan. "Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744.

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An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were stud

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11

Shen, Jue. "Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37212.

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With the advancement of CMOS process and fabrication, it has been a trend to maximize digital design while minimize analog correspondents in mixed-signal system designs. So is the case for PLL. PLL has always been a traditional mixed-signal system limited by analog part performance. Around 2000, there emerged ADPLL of which all the blocks besides oscillator are implemented in digital circuits. There have been successful examples in application of Bluetooth, and it is moving to improve results for application of WiMax and ad-hoc frequency hopping communication link. Based on the theoretic and m

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12

AraÃjo, Renato Guerreiro. "PLL (Phase-Locked Loop) structures for single phase and three phase systems with a high rejection capacity to sub and interharmonic." Universidade Federal do CearÃ, 2015. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=15882.

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CoordenaÃÃo de AperfeÃoamento de Pessoal de NÃvel Superior<br>In applications related to power converters, such as inverters, rectifiers and the use of active filters, the synchronization method represent a very important element in the performance of the control strategy of this equipment. The estimated values of the synchronism angle, frequency and amplitude determined by the synchronization algorithms present, facing strongly distorted signals with the presence of sub and interharmonics, high errors. This study presents two algorithms: one applied on single-phase electrical systems and one

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13

Asghar, Malik Summair. "A “Divide-by-Odd Number” Injection-Locked Frequency Divider." Thesis, Linköpings universitet, Institutionen för systemteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-88014.

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The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to mod

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14

Araújo, Renato Guerreiro. "Estruturas de PLL (Phase-Locked Loop) monofásica e trifásica com alta rejeição a sub e inter-harmônicas." reponame:Repositório Institucional da UFC, 2015. http://www.repositorio.ufc.br/handle/riufc/15474.

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ARAÚJO, R. G. Estruturas de PLL (Phase-Locked Loop) monofásica e trifásica com alta rejeição a sub e inter-harmônicas. 137 f. 2015. Dissertação (Mestrado em Engenharia Elétrica) - Centro de Tecnologia, Universidade Federal do Ceará, Fortaleza, 2015.<br>Submitted by Marlene Sousa (mmarlene@ufc.br) on 2016-02-15T13:33:43Z No. of bitstreams: 1 2015_dis_rgaraujo.pdf: 4472806 bytes, checksum: e5fc0c7e779855fe380073eb2f4579f6 (MD5)<br>Approved for entry into archive by Marlene Sousa(mmarlene@ufc.br) on 2016-03-15T19:12:54Z (GMT) No. of bitstreams: 1 2015_dis_rgaraujo.pdf: 4472806 bytes, checksum: e5

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Eklund, Robert. "Linearization of Voltage-Controlled Oscillators in Phase-Locked Loops." Thesis, Linköping University, Department of Science and Technology, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5366.

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<p>This is a thesis report done as part of the Master of Science in Electronics Design Engineering given at Linköping University, Campus Norrköping. The thesis work is done at Ericsson AB in the spring of 2005. The thesis describes a method of removing variations in the tuning sensitivity of voltage-controlled crystal oscillators due to different manufacturing processes. These variations results in unwanted variations in the modulation bandwidth of the phase-locked loop the oscillator is used in. Through examination of the theory of phase-locked loops it is found that the bandwidth of the loop

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16

Jiang, Bo. "A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration." ScholarWorks @ UVM, 2016. http://scholarworks.uvm.edu/graddis/562.

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The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the pha

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17

Ögren, Jim. "PLL design for inverter grid connection : Simulations for ideal and non-ideal grid conditions." Thesis, Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-156145.

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In this report a phase locked loop (PLL) system for grid voltage phase tracking has been investigated. The grid voltage phase angle contains critical information for connecting a power plant, such as a wave energy converter, to the grid. A synchronous reference frame PLL system with PI-regulator gains calculated with the symmetrical optimum method has been designed and simulations in SIMULINK have been made. For ideal grid conditions the phase angle was tracked fast and accurate. For non-ideal conditions the phase angle was tracked but with less accuracy, due to slow dynamics of the system, bu

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18

Barale, Francesco. "Frequency dividers design for multi-GHz PLL systems." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24610.

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19

Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.

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Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analo

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20

Sun, Lizhong Carleton University Dissertation Engineering Electronics. "High speed submicron CMOS oscillators and PLL clock generators." Ottawa, 1999.

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21

Lin, Ming-Lang. "Analogue to information system based on PLL-based frequency synthesizers with fast locking schemes." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/4627.

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Data conversion is the crucial interface between the real world and digital processing systems. Analogue-to-digital converters and digital-to-analogue converters are two key conversion devices and used as the interface. Up to now, the conventional ADCs based on Nyquist sampling theorem are facing a critical challenge: the resolution and the sampling rate must be radically increased when some applications such as radar detection and ultra-wideband communication emerge. The offset of comparators and the setup time of sample-and-hold circuits, however, limit the resulution and clock rate of ADCs.

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22

Moes, Henderikus Jan. "A low noise PLL-based frequency synthesiser for X-band radar." Thesis, Link to the online version, 2008. http://hdl.handle.net/10019/1337.

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23

Tonucci, Elena. "Implementazione di un sistema ottimizzato per la stima della frequenza di segnali mediante Phase-Locked Loops." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/23522/.

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I Phase-Locked Loops sono sistemi che forniscono una stima coerente in fase del segnale in ingresso. In ambito di tracking radiometrico di sonde deep space, essi vengono utilizzati per la stima della frequenza residua, indispensabile per attuare le funzioni di navigazione, determinazione d’orbita e guida. Sebbene le loro prestazioni siano deteriorate da disturbi di diversa natura, essi sono a tutt’oggi lo strumento più impiegato per elaborare dati provenienti da esperimenti di radio scienza, tant’è che diversi studi hanno tentato negli anni di migliorare le loro prestazioni, mediante l’utilizz

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24

Konečný, Tomáš. "Návrh fázového závěsu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217873.

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25

Moberg, Caroline. "Development of measurement algorithm in an industrial PLC : An evaluation of DSOGI-PLL for real time measurements." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-388490.

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The aim of this project was to devise an algorithm for three phase AC power grid measurements that could be utilized in an excitation system for controlling generators. This application requires fast and accurate measurements even when the voltages in the power grid are characterized by unbalanced three-phase, frequency variations and harmonic distortions. Phase locked loop algorithms are used in grid synchronization techniques and are developed to withstand disturbances in the power grid. A DSOGI-PLL was implemented on a PLC and then evaluated. The DSOGI-PLL was tested with input voltages gen

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26

Lee, Kun Seok. "Wideband phase-locked loops with high spectral purity for wireless communications." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44882.

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The objective of this research is to demonstrate the feasibility of the implementation of wideband RF CMOS PLLs with high spectral purity using deep sub-micron technologies. To achieve wide frequency coverage, this dissertation proposed a 45-nm SOI-CMOS RF PLL with a wide frequency range to support multiple standards. The PLL has small parasitic capacitance with the help of a SOI technology, increasing the frequency tuning range of a capacitor bank. A designed and fabricated chip demonstrates the PLL supporting almost all cellular standards with a single PLL. This dissertation also proposed a

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Shariat, Yazdi Ramin. "Mixed signal design flow, a mixed signal PLL case study." Thesis, University of Waterloo, 2001. http://hdl.handle.net/10012/916.

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Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is

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28

Gomes, Pedro Henrique de Castro. "Análise e síntese de um algoritmo “Phase-Locked Loop” robusto para estimação de amplitude, fase e freqüência de sinais elétricos." Universidade Federal de Juiz de Fora (UFJF), 2007. https://repositorio.ufjf.br/jspui/handle/ufjf/3807.

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Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-03-21T18:37:34Z No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5)<br>Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-03-22T12:40:06Z (GMT) No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5)<br>Made available in DSpace on 2017-03-22T12:40:06Z (GMT). No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5)

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Berenguer, Sau Jordi. "Síntesis de frecuencias en microondas mediante sistemas PLL: aplicación a la recepción de señales emitidas por satélite hasta 30 GHz." Doctoral thesis, Universitat Politècnica de Catalunya, 1988. http://hdl.handle.net/10803/6898.

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La tesi estudia el problema de la síntesi de freqüències en les bandes de freqüències de microones i ones mil·limètriques, i la seva aplicació al disseny dels oscil·ladors locals d'un receptor coherent per a la recepció de les *radiobalises que a 12, 20 i 30 GHz emetia el satèl·lit Olympus de l'Agència Espacial Europea (ESA), amb la finalitat de caracteritzar el comportament radioelèctric de l'atmosfera a aquestes freqüències, a partir de mesures d'atenuació i transpolarització sobre aquests senyals de test, tot això dintre del marc d'un experiment de propagació (OPEX) propiciat per l'agència.

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30

Tiagaraj, Sathya Narasimman. "Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262041.

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31

Gao, Siyu. "Grid synchronisation of VSC-HVDC system." Thesis, University of Manchester, 2015. https://www.research.manchester.ac.uk/portal/en/theses/grid-synchronisation-of-vschvdc-system(6de14261-b0cd-4a82-bfb9-2ccaae012c4e).html.

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This thesis investigates issues affecting grid synchronisation of VSC-HVDC systems with particular regard to, but not limited to, offshore wind power generation during the complex but potentially serious behaviours following solar storms. An averaged value model (AVM) for the contemporary modular multilevel converter (MMC) based VSC-HVDC system is developed and is used in combination with different phase-locked loop (PLL) models and the unified magnetic equivalent circuit (UMEC) transformer model to assess the impacts of geomagnetically induced current (GIC) on grid synchronisation of an offsh

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32

Cheng, Shanfeng. "Design of CMOS integrated phase-locked loops for multi-gigabits serial data links." Texas A&M University, 2006. http://hdl.handle.net/1969.1/4954.

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High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyze

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33

Finelli, Stefano. "Realizzazione di un sistema di stabilizzazione per laser a stato solido, per la generazione di luce squeezed in esperimenti di interferometria." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2015. http://amslaurea.unibo.it/8296/.

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Con questo lavoro di tesi si affrontano i primi accorgimenti sperimentali necessari alla realizzazione di un esperimento di ottica quantistica. L'attività svolta consiste nell'ottimizzazione dei parametri di un PLL (Phase-Locked Loop) che mantiene due laser agganciati in frequenza, e nella misura del rumore di fase presente nell'aggancio. Questa stabilizzazione costituisce il primo passo per la generazione di luce squeezed, associata a particolari stati del campo elettromagnetico. Grazie a quest'ultima, è possibile migliorare la sensibilità raggiungibile in esperimenti di interferometria di pr

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Choi, Jaehyouk. "Fully-integrated DLL/PLL-based CMOS frequency synthesizers for wireless systems." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/42698.

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A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important. As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to

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Siqueira, Paulo de Tarso Dalledone. "Memória: preservação de características individuais e de grupo em sistemas coerentes formados pelo acoplamento de osciladores." Universidade de São Paulo, 2003. http://www.teses.usp.br/teses/disponiveis/43/43134/tde-20022014-142003/.

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O presente trabalho propõe-se a oferecer respostas à questão de como a informação é preservada num sistema, focalizando-se na distinção entre os papéis desempenhados pelos constituintes elementares e pelos estruturais na preservação da memória desse sistema. Os sistema simulados circunscreveram-se a malhas, com diferentes graus de regularidade, compostas pelo acoplamento de osciladores não-lineares que apresentam comportamento coerente no estado de equilíbrio. Malhas de Sincronismo de Fase, também conhecidas por PLLs (Phase Locked Loops), foram adotadas como elementos constituintes básicos dos

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Antunes, Richard Henrique Ribeiro. "Detecção e classificação de VTCDs em sistemas de distribuição de energia elétrica usando redes neurais artificiais." Universidade do Estado do Rio de Janeiro, 2012. http://www.bdtd.uerj.br/tde_busca/arquivo.php?codArquivo=3879.

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Fundação de Amparo à Pesquisa do Estado do Rio de Janeiro<br>O objetivo deste trabalho é conhecer e compreender melhor os imprevistos no fornecimento de energia elétrica, quando ocorrem as variações de tensão de curta duração (VTCD). O banco de dados necessário para os diagnósticos das faltas foi obtido através de simulações de um modelo de alimentador radial através do software PSCAD/EMTDC. Este trabalho utiliza um Phase-Locked Loop (PLL) com o intuito de detectar VTCDs e realizar a estimativa automática da frequência, do ângulo de fase e da amplitude das tensões e correntes da rede elétrica.

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Lisboa, Alexandre Coutinho. "Controle de caos em PLL de terceira ordem." Universidade de São Paulo, 2009. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-02092009-100746/.

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Inicialmente, apresentam-se características de dispositivos eletrônicos conhecidos como PLLs (phase-locked loops). PLLs são amplamente empregados para se extrair sinais de tempo em canais de comunicação e em aplicações nas quais se deseja controle automático de freqüência. O objeto principal é estudar PLLs analógicos descritos por uma equação diferencial ordinária de terceira ordem. Assim, deduzem-se condições de estabilidade assintótica e identifica-se um regime de caos conservativo, que ocorre sob certas combinações de valores de parâmetros. Três métodos de controle não-linear/caótico são en

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Scheibe, Niko. "Entwicklung einer monolithisch integrierten 2,44 GHz Phasenregelschleife in der LFoundry 150nm-CMOS Technologie." Master's thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-61765.

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Die Spezifikationen und Toleranzbereiche heutiger Hochgeschwindigkeitsdatenübertragungstechnologien nehmen immer weiter an Komplexität, aufgrund der steigenden Informationsmenge, zu. Zur Verarbeitung von Daten in Frequenzbereichen oberhalb von einem Gigahertz sind Referenzsignale notwendig, welche ein äußerst geringes Phasenrauschen aufweisen um benachbarte Kanäle nicht zu beeinflussen. Diese Referenzsignale werden in Mischerschaltungen zur Modulation oder Demodulation zwischen radio frequency (RF)- und intermediate frequency (IF)-Signalen verwendet. Die benötigte Signalform ist eine Sinusschw

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Imran, Saeed Sohail. "Investigation of Mechanisms for Spur Generation in Fractional-N Frequency Synthesizers." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80886.

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With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated

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Sousa, Fernando Rangel de. "Application du corrélateur " Five-Port " aux PLLs, à la récupération de porteuse et à un MODEM de télécommunications dans la bande 1,8 - 5,5 Ghz." Paris, ENST, 2004. https://pastel.archives-ouvertes.fr/pastel-00000987.

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Le corrélateur "Five-Port" est un dispositif qui calcule précisément le rapport complexe entre deux signaux hyperfréquences à partir de la mesure des valeurs de puissance aux sorties d'un circuit interférométrique à cinq accès. Son application est connue dans les systèmes radars, les systèmes de détermination de la direction d'arrivée de signaux RF, les démodulateurs homodynes et, comme nous proposons dans ce travail, dans les boucles à verrouillage de phase et de récupération de porteuse. Tandis que les corrélateurs cartésiens classiques projettent le vecteur représentant le signal à démodule

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Bouloc, Jeremy. "Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4307/document.

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Un microscope à force atomique (AFM) est utilisé pour caractériser des matériaux isolant ou semi-conducteur avec une résolution pouvant atteindre l'échelle atomique. Ce microscope est constitué d'un capteur de force couplé à une électronique de contrôle pour pouvoir correctement caractériser ces matériaux. Parmi les différents modes (statique et dynamique), nous nous focalisons essentiellement sur le mode dynamique et plus particulièrement sur le fonctionnement sans contact à modulation de fréquence (FM-AFM). Dans ce mode, le capteur de force est maintenu comme un oscillateur harmonique par le

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42

Souza, José Renato Cozzolino Rodrigues de. "Um estudo sobre o desempenho de algoritmos de estimação de frequência visando unidades de medição fasorial." Niterói, 2017. https://app.uff.br/riuff/handle/1/3936.

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Submitted by Patrícia Cerveira (pcerveira1@gmail.com) on 2017-06-12T18:19:03Z No. of bitstreams: 1 José Renato Cozzolino.pdf: 2923143 bytes, checksum: 2941736082bf50938fdb3dcfea03c36e (MD5)<br>Approved for entry into archive by Biblioteca da Escola de Engenharia (bee@ndc.uff.br) on 2017-07-03T13:30:54Z (GMT) No. of bitstreams: 1 José Renato Cozzolino.pdf: 2923143 bytes, checksum: 2941736082bf50938fdb3dcfea03c36e (MD5)<br>Made available in DSpace on 2017-07-03T13:30:54Z (GMT). No. of bitstreams: 1 José Renato Cozzolino.pdf: 2923143 bytes, checksum: 2941736082bf50938fdb3dcfea03c36e (MD5)<br>A es

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Olivarez, Nathan. "Mitigating the Effects of Ionospheric Scintillation on GPS Carrier Recovery." Digital WPI, 2013. https://digitalcommons.wpi.edu/etd-theses/245.

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Ionospheric scintillation is a phenomenon caused by varying concentrations of charged particles in the upper atmosphere that induces deep fades and rapid phase rotations in satellite signals, including GPS. During periods of scintillation, carrier tracking loops often lose lock on the signal because the rapid phase rotations generate cycle slips in the PLL. One solution to mitigating this problem is by employing decision-directed carrier recovery algorithms that achieve data wipe-off using differential bit detection techniques. Other techniques involve PLLs with variable bandwidth and variable

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44

Hallal, Ayman. "Génération d'ondes millimétriques et submillimétriques sur des systèmes fibrés à porteuses optiques stabilisées." Thesis, Rennes 1, 2017. http://www.theses.fr/2017REN1S005/document.

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Je rapporte dans ce manuscrit une étude théorique et expérimentale d’une source compacte, fiable et bas coût d’ondes électromagnétiques continues et cohérentes de 30 Hz de largeur de raie, accordables de 1 GHz à 500 GHz par pas de 1 GHz. Ces ondes sont générées par un photo-mélange de deux diodes lasers DFB (Distributed Feedback) très accordables autour de 1550 nm, stabilisées avec des polarisations orthogonales sur une même cavité Fabry-Perot optique fibrée. J’ai conçue des électroniques de correction très rapides pour chaque laser permettant d’avoir une bande passante d’asservissement de 7 M

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Sagha, Hossein. "Development of innovative robust stability enhancement algorithms for distribution systems containing distributed generators." Thesis, Queensland University of Technology, 2015. https://eprints.qut.edu.au/91052/1/Hossein_Sagha_Thesis.pdf.

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This project was a step forward in improving the voltage profile of traditional low voltage distribution networks with high photovoltaic generation or high peak demand. As a practical and economical solution, the developed methods use a Dynamic Voltage Restorer or DVR, which is a series voltage compensator, for continuous and communication-less power quality enhancement. The placement of DVR in the network is optimised in order to minimise its power rating and cost. In addition, new approaches were developed for grid synchronisation and control of DVR which are integrated with the voltage qual

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Klapil, Filip. "Frekvenční syntezátor pro mikrovlnné komunikační systémy." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413162.

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The main aim of the thesis is to develop a solution of a frequency synthesizer for a microwave communication systems. Specifically, it suggests a design for frequency synthesizer with phase-locked loop. At beginning of the thesis the principle and basic properties of this method of signal generation are explained. Then it is followed by a brief discussion of the parameters of synthesizers and their influence on design. Another part of the work is the analysis of circuit the frequency synthesizer with the phase-locked loop MAX2871, which is followed by a proposal for the design of the frequency

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Marmo, Carlos Nehemy. "Sincronismo em redes mestre-escravo de via-única: estrela simples, cadeia simples e mista." Universidade de São Paulo, 2003. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-18022004-233234/.

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Neste trabalho, são estudados os problemas de sincronismo de fase nas redes mestre-escravo de via única (OWMS), nas topologias Estrela Simples, Cadeia Simples e mista, através da Teoria Qualitativa de Equações Diferenciais, com ênfase no Teorema da Variedade Central. Através da Teoria das Bifurcações, analisa-se o comportamento dinâmico das malhas de sincronismo de fase (PLL) de segunda ordem que compõem cada rede, frente às variações nos seus parâmetros constitutivos. São utilizadas duas funções de excitação muito comuns na prática: o degrau e a rampa de fase, aplicadas pelo nó mestre. Em cad

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Švábeník, Petr. "Synchronizace času pomocí GPS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218601.

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This thesis discusses about using the worldwide satellite system GPS for time and frequency synchronization. This thesis presents study about basic principles of the GPS system, its segments and ways of using this system. Some GPS receivers suitable for receiving the time marks (pulses) used for time synchronization are described. Thesis contents designing of the circuit that will receive time marks and it will digitalize and record external signal and send it with precision time information to PC for displaying and post processing. Thesis also discusses about both hardware and software develo

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Narashimhamurthy, Chetan. "Phase Locked Loop using LABVIEW." Thesis, Linnéuniversitetet, Institutionen för fysik och elektroteknik (IFE), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-82408.

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The phase-locked loop is an important concept in the ﬁeld of wireless communication. PLL:s have wide-ranging applications in many electronic circuits. The history and the basic principle of the phase-locked loop are discussed. The different building blocks and their roles are also described along with some of the major applications ofphase-locked loops. The thesis mainly describes how to build a phase-locked loop circuit using LabVIEW, as a laboratory experiment intended for a course in Radio Engineering. It was previously implemented in PSpice and this is described for comparison. The basic f

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Hardwicke, K. R. "A SELF TUNING PHASE-LOCKED LOOP." International Foundation for Telemetering, 1992. http://hdl.handle.net/10150/608941.

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International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California<br>The uncertainty in the gain of voltage controlled crystal oscillators (VCXOs) used in the implementation of certain analog phase-locked loops (PLLs) suggests some form of automatic tuning algorithm, both for pretuning and during operation. This paper proposes an adaptive PLL (APLL) algorithm to fill this need for PLLs used in the recovery of tones in noise. This algorithm makes use of a resonant error algorithm to remove the effects of VCXO noise

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