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Journal articles on the topic 'Phase Locked Loop (PLL)'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Subhash, Patel *. Abhishek Vaghela Bhavin Gajjar. "DESIGN OF PHASE LOCKED LOOP." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 5 (2017): 312–20. https://doi.org/10.5281/zenodo.573512.

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In this work, we have designed CDR-PLL for 1GHz frequency. The design is carried out in the 180nm CMOS technology. We have use Hogge phase detector with the Kim-Lee delay cell based VCO. The designed CDR-PLL is tested by applying the 8B-10B encoded data and the simulation results are represented. The obtained results show that the clock is recovered successfully.

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2

Imran, Rajib, Monirul Islam, and Abdullah Al Kafi. "Synthesizable Digital Phase Locked Loop Implementation." Advanced Materials Research 684 (April 2013): 317–21. http://dx.doi.org/10.4028/www.scientific.net/amr.684.317.

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Phase locked loop (PLL) is a very common circuit in the most of the electrical devices. The systems where needed clock or data recovery or frequency synthesis, PLL is the most cost effective and efficient choice that from cellular phone in our hands to the computers, televisions, radios and a different controller, PLL is everywhere. Due to ever increasing growth of the digital systems especially in the wireless communication, the Digital PLL (DPLL) has been developed to overcome the disadvantages of analog techniques such as large noise, power hungry, parameter sensitivity etc. Besides DPLL pr

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3

B R, Mr Chethan, Punith H D, Abhishek Gowda H A, Manoj B S, and Rahul H R. "Design of Phase Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39446.

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A Phase-Locked Loop (PLL) is a crucial feedback control system used to synchronize the phase of an output signal with a reference signal. This paper explores the design, analysis, and applications of PLLs in modern communication systems, digital circuits, and power electronics. The study covers the fundamental components of a PLL—phase detector, low-pass filter, and voltage-controlled oscillator (VCO)—and their interactions in achieving phase synchronization. Key performance parameters such as lock time, jitter, stability, and noise sensitivity are examined in detail. Furthermore, the paper di

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4

R, Prithiviraj, and Selvakumar J. "Non-Linear Mathematical Modelling for Phase Locked Loop." International Journal of Engineering & Technology 7, no. 4.10 (2018): 81. http://dx.doi.org/10.14419/ijet.v7i4.10.20710.

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Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.

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5

D Patel, Nilesh, and Amisha P Naik. "PHASE LOCKED LOOP USING SUB HARMONIC INJECTION TECHNIQUE WITH AUTO ADJUSTED DELAY LOCKED LOOP." ICTACT Journal on Microelectronics 6, no. 3 (2020): 959–63. https://doi.org/10.21917/ijme.2020.0166.

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For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents design for low jitter, phase noise, power dissipation for 7.5 GHz Phase locked loop using sub harmonic injection technique with auto adjusted Delay locked loop in 180-nm CMOS technology. The measured phase noise at 1 MHz reference offset frequency is 122.31 dB

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6

S C, Mrs Shyamala, Latish Patil, Srinivas Gowda K R, Yashwanth T, and Dhruva Kumar T R. "Realization of an All-Digital Phase-Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–7. https://doi.org/10.55041/ijsrem39448.

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An all-digital phase locked loop (PLL) is presented in the paper. The goal of a PLL, a closed-loop control system, is to synchronize the phase and frequency of an incoming signal. Clock generation and recovery communication systems are the most flexible uses of PLL. Digital PLLs are chosen because of the greater integration of digital designs. The implementation of ADPLL utilizing a Xilinx Vivado tool and code is written in Verilog. Key Words: All Digital PLL, digitally controlled oscillator(DCO),Low Pass Filter(LPF),Increment-Decrement (ID)

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7

Melikyan, V. Sh, A. A. Durgaryan, H. P. Petrosyan, and A. G. Stepanyan. "Power Efficient, Low Noise 2-5 GHz Phase Locked Loop." Electronics and Communications 16, no. 4 (2011): 66–72. http://dx.doi.org/10.20535/2312-1807.2011.16.4.244797.

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A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead

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8

Bondariev, Andriy, Ivan Maksymiv, and Serhii Altunin. "Simulation and investigations of a software implemented phase-locked loop with improved noise immunity." Computational Problems of Electrical Engineering 8, no. 2 (2018): 41–48. http://dx.doi.org/10.23939/jcpee2018.02.041.

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The improvement of noise immunity of a communication system is an effective way to increase the capacity of communication systems, which would provide more qualitative service for a larger number of users. This task can be solved by lowering the noise threshold of a phase-locked loop (PLL) in these systems if the dynamic properties of the device are preserved. The literature review indicates that such a device with improved noise immunity has already been implemented, but the effects of noise and modulation on its dynamic behavior were analyzed separately. This article is devoted to the analys

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9

Anupama, Patil* Dr P.H.Tandel. "DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP." DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP 5, no. 5 (2016): 134–38. https://doi.org/10.5281/zenodo.51007.

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The Phase Locked Loop (PLL) is an almost always used electronics circuit for communication systems like modulator, demodulator, frequency generator and frequency synthesizer etc. All-digital phase locked loop (ADPLL) is digital version of the PLL. In this paper, a novel Hilbert transform based phase detection system for all-digital phase locked loop (ADPLL) is presented. The digital discrete time components are used to realize the phase detector system reducing the complexity of the design. The Hilbert transform based phase detection system provides a definite advantage over conventional analo

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10

Li, Jincheng. "Working principle and application analysis of phase-locked loop." Applied and Computational Engineering 11, no. 1 (2023): 174–80. http://dx.doi.org/10.54254/2755-2721/11/20230228.

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This article analyzes the current research status of phase-locked loops (PLLs) from multiple aspects. The working principle and components of PLL are discussed in detail, including the feedback controlling mechanism, clock skew generation and elimination, and frequency multiplication. The main components of PLL, including phase detector, low-pass filter, and voltage-controlled oscillator, are also explained in the following parts. The article further explores the applications of PLL, such as frequency synthesizers and clock and data recovery, and the challenges faced in designing PLLs. These c

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11

Zhai, Bingcong. "Understanding of the Coherent Demodulation with Phase-Locked Loop." MATEC Web of Conferences 176 (2018): 01028. http://dx.doi.org/10.1051/matecconf/201817601028.

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The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way. Therefore, more and more attentions have been paid to the research and application of all digital phase-locked loops. This paper serves as an introduction about the basic background of PLL, the basic characteristics and structure of PLL, and the basic principles of modulation and demodulation. It provides a concise application about the basic principle and

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12

Zhao, Lei, Lei Shi, and Congying Zhu. "New Nonlinear Second-Order Phase-Locked Loop with Adaptive Bandwidth Regulation." Electronics 7, no. 12 (2018): 346. http://dx.doi.org/10.3390/electronics7120346.

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Synchronization of large acquisition bandwidth brings great challenges to the traditional second-order phase-locked loop (PLL). To address the contradiction between acquisition bandwidth and noise suppression capability of the traditional PLL, a new second-order PLL coupled with a nonlinear element is proposed. The proposed nonlinear second-order PLL regulates the loop noise bandwidth adaptively by the nonlinear module. When a large input–output phase error occurs, this PLL reduces the frequency offset quickly by taking advantage of the large bandwidth. When the phase error is reduced by the l

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13

Issam, A. Smadi, A. Albatran Saher, and Q. Ababneh Taher. "A synchronization technique for single-phase grid applications." International Journal of Power Electronics and Drive Systems 13, no. 4 (2022): 2181~2189. https://doi.org/10.5281/zenodo.7328831.

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The utility grid disturbances like DC offset and harmonic components can severely affect the estimated variables from the phase-locked loop (PLL), resulting in poor performance of the system relying on it. Therefore, there is an emerging need for well-designed PLL algorithms ensuring robust response against different operating conditions. This paper proposes a simple singlephase PLL algorithm with inherent DC offset and specific harmonic orders rejection capability. Utilizing adaptive time-delay fictitious signal generation. A full mathematical model of the proposed PLL has been provided. The

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14

Radwan, Eyad, Khalil Salih, Emad Awada, and Mutasim Nour. "Modified phase locked loop for grid connected single phase inverter." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (2019): 3934. http://dx.doi.org/10.11591/ijece.v9i5.pp3934-3943.

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Connecting a single-phase or three-phase inverter to the grid in distributed generation applications requires synchronization with the grid. Synchronization of an inverter-connected distributed generation units in its basic form necessitates accurate information about the frequency and phase angle of the utility grid. Phase Locked Loop (PLL) circuit is usually used for the purpose of synchronization. However, deviation in the grid frequency from nominal value will cause errors in the PLL estimated outputs, and that’s a major drawback. Moreover, if the grid is heavily distorted with low order h

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15

Shewale, Saurabh J. "Design and Analysis of CMOS Phase Lock Loop (PLL) Using VLSI Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. 11 (2021): 1334–37. http://dx.doi.org/10.22214/ijraset.2021.38363.

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Abstract: This paper proffers comparative research of Complementary MOSFET (CMOS) of the Phase Lock Loop (PPL) circuit. Our approach is based on hybrid design Phase Lock Loop (PLL) circuits combined in a single unit. A phase-locked loop (PLL) is used in space communication for synchronization purposes also very useful in time to digital converters and in instrumentation engineering. A phased lock loop (PLL) is a control system that makes an output signal whose frequency depends on the input phase difference. The phase detector takes the phase of an input signal and compares it with the phase p

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16

Adesina, Naheem Olakunle, and Ashok Srivastava. "Memristor-Based Loop Filter Design for Phase Locked Loop." Journal of Low Power Electronics and Applications 9, no. 3 (2019): 24. http://dx.doi.org/10.3390/jlpea9030024.

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The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the

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17

Eyad, Radwan, Salih Khalil, Awada Emad, and Nour Mutasim. "Modified phase locked loop for grid connected single phase inverter." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (2019): 3934–43. https://doi.org/10.11591/ijece.v9i5.pp3934-3943.

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Connecting a single-phase or three-phase inverter to the grid in distributed generation applications requires synchronization with the grid. Synchronization of an inverter-connected distributed generation units in its basic form necessitates accurate information about the frequency and phase angle of the utility grid. Phase Locked Loop (PLL) circuit is usually used for the purpose of synchronization. However, deviation in the grid frequency from nominal value will cause errors in the PLL estimated outputs, and that’s a major drawback. Moreover, if the grid is heavily distorted with low o

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18

Niezrecki, C., and H. H. Cudney. "Structural Control Using Analog Phase-Locked Loops." Journal of Vibration and Acoustics 119, no. 1 (1997): 104–9. http://dx.doi.org/10.1115/1.2889677.

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A study of the application of the phase-locked loop (PLL) to modal control of mechanical structures is performed. An analog PLL circuit is used to control the vibration of a cantilevered beam with piezoelectric sensors and actuators. By using the PLL controller, strain rate feedback is provided within a narrow and distinct frequency range about the fourth mode of the beam. The controller ignores all other modes and does not affect the phase outside of the frequency range. The PLL controller provides a simple, inexpensive, and effective method to control an individual structural mode or set of

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19

Bassam, Harb, Qudah Mohammad, Ghareeb Ibrahim, and Harb Ahmad. "Chaos and bifurcation in time delayed third order phase-locked loop." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1431–38. https://doi.org/10.11591/ijece.v11i2.pp1431-1438.

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In this paper, the modern nonlinear theory is applied to a third order phase locked loop (PLL) with a feedback time delay. Due to this delay, different behaviors that are not accounted for in a conventional PLL model are identified, namely, oscillatory instability, periodic doubling and chaos. Firstly, a Pade approximation is used to model the time delay where it is utilized in deriving the state space representation of the PLL under investigation. The PLL under consideration is simulated with and without time delay. It is shown that for certain loop gain (control parameter) and time delay val

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20

Setiawan, Iwan, Mochammad Facta, Ardyono Priyadi, and Mauridhi Hery Purnomo. "Estimator Parameter Tegangan Jaringan Tiga Fasa Berbasis D-SOGI PLL." Majalah Ilmiah Teknologi Elektro 16, no. 2 (2017): 84. http://dx.doi.org/10.24843/mite.2017.v16i02p15.

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Phase locked loop (PLL) adalah sebuah sistem umpan balik yang memegang peran penting dalam sistem-sistem konverter terkoneksi jaringan listrik. Fungsi utama PLL adalah mendapatkan beragam informasi parameter jaringan yaitu seperti phase dan magnitude tegangan. Informasi-informasi tersebut selanjutnya digunakan sebagai dasar proses sinkronisasi peralatan dengan jaringan listrik. Tujuan utama paper ini adalah memodelkan sekaligus membandingkan unjuk kerja salah satu jenis PLL yang dikenal dengan nama Dual Second Order Generalized Integrator Phase-Locked Loop dengan SRF-PLL yaitu sebuah PLL yang

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21

Luo, Zhibin, Jicheng Ding, and Lin Zhao. "Adaptive Gain Control Method of a Phase-Locked Loop for GNSS Carrier Signal Tracking." International Journal of Antennas and Propagation 2018 (2018): 1–14. http://dx.doi.org/10.1155/2018/6841285.

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The global navigation satellite system (GNSS) has been widely used in both military and civil fields. This study focuses on enhancing the carrier tracking ability of the phase-locked loop (PLL) in GNSS receivers for high-dynamic application. The PLL is a very popular and practical approach for tracking the GNSS carrier signal which propagates in the form of electromagnetic wave. However, a PLL with constant coefficient would be suboptimal. Adaptive loop noise bandwidth techniques proposed by previous researches can improve PLL tracking behavior to some extent. This paper presents a novel PLL w

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22

WOO, YOUNGSHIN, YOUNG MIN JANG, and MAN YOUNG SUNG. "A NOVEL METHOD FOR HIGH-PERFORMANCE PHASE-LOCKED LOOP." Journal of Circuits, Systems and Computers 13, no. 01 (2004): 53–63. http://dx.doi.org/10.1142/s0218126604001271.

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In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5 μm CMO

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23

Ezzidin, Hassan Aboadla, and Hassan Ali. "180 nm NMOS voltage-controlled oscillator for phase-locked loop applications." International Journal of Informatics and Communication Technology (IJ-ICT) 12, no. 3 (2023): 236–41. https://doi.org/10.11591/ijict.v12i3.pp236-241.

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The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset and a tot

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24

Cao, Na, and Wenjie Feng. "Improved Single-phase PLL Based on All-Pass Filter." Journal of Physics: Conference Series 2477, no. 1 (2023): 012060. http://dx.doi.org/10.1088/1742-6596/2477/1/012060.

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Abstract The detection accuracy of a conventional phase-locked loop for a single phase is affected by the interference of the DC component and harmonic component when the grid has a lot of problems such as harmonic interference and DC offset, and It will be unable to accurately track the grid voltage frequency and phase. The traditional APF-PLL is improved to address this problem. An improved phase-locking algorithm is proposed, combining a CSOGI and a FLL with the conventional single-phase phase-locked loop. The method incorporates CSOGI into the APF-PLL pre-stage to reduce interference from

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25

Li, Peng, Tian Tian, Bin Wu, and Tianchun Ye. "A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications." Electronics 10, no. 17 (2021): 2077. http://dx.doi.org/10.3390/electronics10172077.

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This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) c

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26

Sefraoui, Hanane, Khalid Salmi, and Abdelhak Ziyyat. "Basic Concepts of a Phase-Locked Loop Control System." International Journal of Online and Biomedical Engineering (iJOE) 18, no. 13 (2022): 25–37. http://dx.doi.org/10.3991/ijoe.v18i13.33419.

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Phase-locked loop (PLL) is one of the main components ofmodern electronic design and has been around for a considerable numberof years. It is a technique that has greatly contributed to the technological advancement of communications and control systems. This paperpresents a phase-locked loop tutorial based on a control system, it givesa concise review of basic concepts, the different types of PLLs, linearanalysis approaches of analog systems PLL is discussed, furthermore thetheoretical analysis of the steady-state error in detail is presented, and itssimulations of different phase offset valu

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27

Thool, Pooja, Dr J. D. Dhande, and Prof Y. A. Sadawarte. "A Review on Design and Analysis of Low Power PLL for Digital Applications and Multiple Clocking Circuits." International Journal for Research in Applied Science and Engineering Technology 10, no. 4 (2022): 178–82. http://dx.doi.org/10.22214/ijraset.2022.41193.

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Abstract: A phase locked loop (PLL) is a basic element of many communication and instrumentation domain. This paper discusses the challenges in designing the low power PLL for multiple frequency output for digital applications. PLL is a key element providing clocking scheme in many electronic circuits raises the requirement of decreasing the power, with the advancement in CMOS technology. In this work, we provide review on low power PLL with good stability. Keywords: Phase-locked loop, CMOS, Clocking, low Power, Digital Applications, etc.

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Charlamov, J., and R. Navickas. "Phase Locked Loop Integrated System." Solid State Phenomena 164 (June 2010): 221–26. http://dx.doi.org/10.4028/www.scientific.net/ssp.164.221.

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CMOS-MEMS integration is an indispensable technique for self-calibration of electromechanical performance to make MEMS devices independent on environmental drift or fabrication errors. The goal of single-chip integration (the “holy grail” for the semiconductor timing industry) would be to include the resonator, the oscillator, the PLL and a temperature compensation circuit (TCC) on a single silicon substrate. The current structure of silicon MEMS-based devices utilizes a stacked-die arrangement, housed in a multi-chip package [1]. MEMS-based timing circuits often use PLLs, which can succumb to

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29

Abbas, Waseem, Zubair Mehmood, and Munkyo Seo. "A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS." Electronics 9, no. 9 (2020): 1502. http://dx.doi.org/10.3390/electronics9091502.

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A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured p

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Harb, Bassam, Mohammad Qudah, Ibrahim Ghareeb, and Ahmad Harb. "Chaos and bifurcation in time delayed third order phase-locked loop." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1431. http://dx.doi.org/10.11591/ijece.v11i2.pp1431-1438.

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In this paper, the modern nonlinear theory is applied to a third order phase locked loop (PLL) with a feedback time delay. Due to this delay, different behaviors that are not accounted for in a conventional PLL model are identified, namely, oscillatory instability, periodic doubling and chaos. Firstly, a Pade approximation is used to model the time delay where it is utilized in deriving the state space representation of the PLL under investigation. The PLL under consideration is simulated with and without time delay. It is shown that for certain loop gain (control parameter) and time delay val

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31

Zubkov, I. S., V. Ya Hutsaliuk, and O. M. Yurchenko. "DIGITAL PHASE-LOCKED LOOP SYSTEM OF RESONANCE VOLTAGE INVERTER." Tekhnichna Elektrodynamika 2022, no. 2 (2022): 27–34. http://dx.doi.org/10.15407/techned2022.02.027.

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The digital phase-locked loop (PLL) system for the resonant voltage inverter with pulse density modulation of induction heating installations is developed. The proposed system for frequency determination uses the feedback signal on the collector-emitter (drain-source) voltage of the inverter transistors and on the output current of the inverter, and stores this frequency on the interval of zero output voltage. A study of the PLL system in different operating modes when changing the load parameters is presented. References 8, figures 6, table 1.

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Long, Yingwen, and Yuhong Sun. "A New PLL Simulation Validation for Three-phase Grid under Heavy Distorted Conditions." International Journal of Online Engineering (iJOE) 11, no. 7 (2015): 37. http://dx.doi.org/10.3991/ijoe.v11i7.4765.

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The precision of phase-locked loop (PLL) has a direct effect on the output performance for three-phase grid-connected inverter or three-phase active PFC. In this paper, a new three-phase digital closed-loop phase-locked algorithm is proposed on the basis of synchronous reference frame transformation. Synchronous simulation of the PLL techniques is a good choice even if the polluted three-phase grid such as the harmonics, phase jump and unbalance. Finally, MATLAB digital simulation results prove that the proposed PLL can fast and accurately track the positive sequence fundamental components of

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33

Hamood, Mostafa A., Ognjen Marjanovic, and Joaquin Carrasco. "Adaptive Impedance-Conditioned Phase-Locked Loop for the VSC Converter Connected to Weak Grid." Energies 14, no. 19 (2021): 6040. http://dx.doi.org/10.3390/en14196040.

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In this paper, an adaptive version of the impedance-conditioned phase-locked loop (IC-PLL), namely the adaptive IC-PLL (AIC-PLL), is proposed. The IC-PLL has recently been proposed to address the issue of synchronisation with a weak AC grid by supplementing the conventional synchronous reference frame phase-locked loop (SRF-PLL) with an additional virtual impedance term. The resulting IC-PLL aims to synchronise the converter to a remote and stronger point in the grid, hence increasing the upper bound on the achievable power transfer achieved by the VSC converter connected to the weak grid. How

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34

Vukadinović, Dinko, Tien Duy Nguyen, Cat Ho Nguyen, Nhu Lan Vu, Mateo Bašić, and Ivan Grgić. "Hedge-Algebra-Based Phase-Locked Loop for Distorted Utility Conditions." Journal of Control Science and Engineering 2019 (March 3, 2019): 1–17. http://dx.doi.org/10.1155/2019/3590527.

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This paper presents the first application of the hedge-algebra theory in the field of grid synchronization. For this purpose, an optimized hedge-algebra controller (HAC) is developed and incorporated within the three-phase phase-locked loop (PLL) with moving average filters (MAFs) inside its feedback loop. Optimized fuzziness parameters and linguistic rule base of the HAC are obtained by a genetic algorithm using the integral of absolute error as the performance index during optimization. Calculated optimal parameter values of the HAC depend on the most frequently occurring disturbance in the

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35

Telnov, A. A. "Designing a Phase-Locked Frequency Control System." LETI Transactions on Electrical Engineering & Computer Science 15, no. 7 (2022): 37–46. http://dx.doi.org/10.32603/2071-8985-2022-15-7-37-46.

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The article is devoted to the development of a phase locked loop (PLL) system using the CD4046 integrated circuit. To achieve this goal, the principles of operation of two types of phase detectors were investigated. In the second half of the article, the main transfer functions of the PLL system are derived, an example of calculating the feedback controller is considered. The reliability of the calculation results is confirmed by modeling a computer model of a resonant voltage inverter.

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B. S., Premananda, Dhanush T. N., Vaishnavi S. Parashar, and D. Aneesh Bharadwaj. "Design and Implementation of High Frequency and Low-Power Phase-locked Loop." U.Porto Journal of Engineering 7, no. 4 (2021): 70–86. http://dx.doi.org/10.24840/2183-6493_007.004_0006.

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Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence

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Abhuday, Parasar* Megha Kimothi. "DESIGN IMPLEMENTATION OF DIGITAL FM MODULATOR & DEMODULATOR FOR SDR USING FPGA." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 7, no. 3 (2018): 178–86. https://doi.org/10.5281/zenodo.1194275.

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This paper represents the recent advancement in the chip technology is integrating several sequential elements in System on Chip (SoC). But most of the circuits are using traditional clock distribution networks and facing the problem of skew and jitter problems. The clock signal generated by the oscillators and the flip-flops and registers are not receiving the clock pulse at the accurate time. The problem can be solved using Network of Phase-Locked Loop (PLL) oscillators coupled in phase. A phase locked loop ensures that the clock frequencies seen at the clock inputs of various registers and

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Charlamov, Jevgenij. "PLL DESIGN AND INVESTIGATION IN CMOS." Mokslas - Lietuvos ateitis 2, no. 1 (2010): 54–58. http://dx.doi.org/10.3846/mla.2010.012.

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In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm2, power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.

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Lee, Tzung-Je, and Chua-Chin Wang. "A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators." VLSI Design 2008 (September 24, 2008): 1–8. http://dx.doi.org/10.1155/2008/512946.

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A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper. Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively. By using separate regulators, the area and the power consumption of the regulator can be reduced. Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise. The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process. The peak-to-peak jitter (P2P jitter) of the proposed PLL is measu

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Tan, Guangjun, Zhi Chen, Wei Zhao, and Xiaofeng Sun. "Research on phase-locked loop technique based on three-dimensional coordinate transformation." Engineering Research Express 4, no. 1 (2022): 015013. http://dx.doi.org/10.1088/2631-8695/ac4de5.

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Abstract The traditional phase-locked loop (PLL) technique widely used in three-phase four-wire system can only obtain one phase angle, and cannot obtain other parameters of unbalanced voltages, such as the amplitude and phase angle of each phase voltage. In order to improve the performance of PLL in unbalanced three-phase four-wire system with disturbance and reduce the order of PLL to improve the stability of the system, a PLL technique based on three-dimensional (3D) coordinate transformation was proposed in this paper. Firstly, the phase detector error of three-phase unbalanced voltage was

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Liu, L., and C. Liu. "Deliberations about three-phase PLL technologies applied to a grid control of the renewable power system." Bulletin of the Polish Academy of Sciences Technical Sciences 63, no. 1 (2015): 261–67. http://dx.doi.org/10.1515/bpasts-2015-0030.

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Abstract An efficient phase locked loop (PLL) method is very important to improve the grid-connected efficiency and the locked speed of frequency, phase, and voltage. However, most of literatures only introduce one PLL or one modified PLL method. There are many grid faults due to the grid connection to the renewable power generating system. A comparison and analysis is very important to select the most effective PLL technology for the grid-connected control of the renewable power system. Three PLL technologies are compared at different grid faults, such as single phase voltage drop, two phase

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Nikitin, Y., and G. Tsygankov. "Modeling PLL Loop with Nonlinearity." Telecom IT 7, no. 4 (2019): 9–14. http://dx.doi.org/10.31854/2307-1303-2019-7-4-9-14.

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A model of a pulse phase-locked loop multiplying ring in a MicroCap11 medium is considered. The analysis uses a nonlinear model of a voltage-controlled oscillator with a user-defined control characteristic. An RS-trigger is used as a pulse-phase detector, a pulse counter in the negative feedback circuit is implemented on JK-triggers. Transient processes in the ring, as well as the spectrum of the output oscillations in the steady (stationary) mode are considered.

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CHANG, ROBERT C., LUNG-CHIH KUO, and HOU-MING CHEN. "A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP." Journal of Circuits, Systems and Computers 14, no. 05 (2005): 997–1006. http://dx.doi.org/10.1142/s0218126605002738.

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A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can b

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Miyata, Kazuki, and Takeshi Fukuma. "Quantitative comparison of wideband low-latency phase-locked loop circuit designs for high-speed frequency modulation atomic force microscopy." Beilstein Journal of Nanotechnology 9 (June 21, 2018): 1844–55. http://dx.doi.org/10.3762/bjnano.9.176.

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A phase-locked loop (PLL) circuit is the central component of frequency modulation atomic force microscopy (FM-AFM). However, its response speed is often insufficient, and limits the FM-AFM imaging speed. To overcome this issue, we propose a PLL design that enables high-speed FM-AFM. We discuss the main problems with the conventional PLL design and their possible solutions. In the conventional design, a low-pass filter with relatively high latency is used in the phase feedback loop, leading to a slow response of the PLL. In the proposed design, a phase detector with a low-latency high-pass fil

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Hassan Aboadla, Ezzidin, and Ali Hassan. "180 nm NMOS voltage-controlled oscillator for phase-locked loop applications." International Journal of Informatics and Communication Technology (IJ-ICT) 12, no. 3 (2023): 236. http://dx.doi.org/10.11591/ijict.v12i3.pp236-241.

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<p>The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset

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Ghaderi, Noushin, Hamid Reza Erfani-jazi, and Mehdi Mohseni-Mirabadi. "A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods." Journal of Electrical and Computer Engineering 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/8202581.

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A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a0.18 μmCMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-les

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Kim, Seunghwan, Hyung-In Ra, Hyun-Woo Jeong, et al. "Joint equalizer and phase-locked loop for time variability in underwater acoustic communications." Journal of the Acoustical Society of America 151, no. 4 (2022): A281. http://dx.doi.org/10.1121/10.0011346.

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In this paper, we verify the performance of the equalizer and phase-locked loop (PLL) operating jointly for channel time variability in underwater acoustic communications. We apply the decision feedback equalizer in order to eliminate channel multipath and PLL to phase rotation due to Doppler effects. In the PLL, a decision-directed tan−1 type phase detector is adopted. As shown in previous papers, it is difficult to make PLL to be steady state because of time-varying ISI occurred by multipath. Also, the phase rotation incurs the equalizer tap rotation. Therefore, we can see that the two subsy

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Zhang, Ye, Haibo Pen, and Xiaoyu Zhang. "Stability Control of Grid-Connected Converter Considering Phase-Locked Loop Frequency Coupling Effect." Energies 17, no. 14 (2024): 3438. http://dx.doi.org/10.3390/en17143438.

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Given the problems that the phase-locked loop frequency coupling effect (PLL-FCE) in a weak grid reduces the quality of the output current waveform and brings challenges to maintaining a steady running of the grid-connected converter (GCC), this paper analyzes the coupling relationship between the FCE of the PLL, grid impedance and the output impedance of GCCs under a weak grid. It elucidates the role of the above coupling relationships in system stability and then proposes a stability optimization control method. Firstly, this paper delves into the frequency coupling phenomenon and its coupli

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Sevilmiş, Fehmi, and Hulusi Karaca. "An Effective Solution to Eliminate DC-Offset for Extracting the Phase and Frequency of Grid Voltage." Mathematical Problems in Engineering 2021 (September 23, 2021): 1–9. http://dx.doi.org/10.1155/2021/9742683.

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Recently, several approaches with the ability to reject the DC-offset in phase locked loop (PLL) methods have been developed. These approaches include different filtering structures which can be classified into two categories: prefiltering before the PLL input and in-loop filtering in the PLL control loop. As highlighted in the literature, the DC-offset rejection methods based on in-loop filtering have received less attention due to their slow dynamic performance. Therefore, this paper proposes an alternative DC-offset rejection technique as in-loop filtering of the PLL. The effectiveness of t

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Fan, Sheng Wen, Chun Yu Zheng, Zheng Xi Li, and Chun Xue Wen. "A Study of Phase-Locked Technology of Wind Power Generation Three-Phase Grid-Connected Inverter." Advanced Materials Research 383-390 (November 2011): 3449–55. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.3449.

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This paper presents two phase-locked methods of wind power generation three-phase grid-connected inverter. First establishes the mathematical model of the inverter, on this basis analyzes why the power voltage phase must be known. And then studies the direct calculation method in α-β coordinates, and analyzes the shortcomings of this approach for three-phase imbalance; then focusing on the phase locked loop (PLL) approach in d-q coordinate system. To solve dynamic response problem of the PLL, a new signal delay cancellation method is put forward. With this improved method, the PLL can have a b

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