Relevant bibliographies by topics / Phase-locked loops – Design and construction

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  1. Journal articles
  2. Dissertations / Theses
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  5. Conference papers

Academic literature on the topic 'Phase-locked loops – Design and construction'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Phase-locked loops – Design and construction"

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Zhang, Chunyu, Shouxiang Wang, Ruxun He, Qianyu Zhao, and Kai Wang. "Design and Construction of a Low Cost All-Digital Phase Locked Loop Based on Field Programmable Gate Array." Journal of Physics: Conference Series 1972, no. 1 (2021): 012054. http://dx.doi.org/10.1088/1742-6596/1972/1/012054.

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Mutter, Manfred, Karl-Heinz Altmann та Thomas Vorherr. "The Construction of New Proteins. II. Design, Synthesis and Conformational Studies of Folding Units with βαβ-Topology". Zeitschrift für Naturforschung B 41, № 10 (1986): 1315–22. http://dx.doi.org/10.1515/znb-1986-1020.

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The design, synthesis and preliminary conformational studies of two polypeptides exhibiting βαβ-type folding topologies are presented. In the design of the model peptides the general concept for the construction of new proteins developed in the preceeding paper was applied. According to this strategy, amphiphilic helices and β-sheets are linked together via hydrophilic loops to attain three-dimensional structures of higher order (‘supersecondary structures’). Com­puter-assisted molecular modelling served as a valuable tool for minimizing conformational con­straints within the molecules. The 38
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Elvekrok, Dag Runar. "Concurrent Engineering in Ship Design." Journal of Ship Production 13, no. 04 (1997): 258–69. http://dx.doi.org/10.5957/jsp.1997.13.4.258.

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Concurrent engineering is a systematic approach for integration and concurrent design of products. The systematic approach intends to consider all elements influencing the products and their related processes during the product life-cycle, such as manufacturing, support, costs, quality, user requirements etc. Especially the engineering design phase should be considered for improvements. This paper presents some of the major and most acknowledged concepts, ideas and principles of concurrent engineering. They are among others:trends and demands to product development time and product life-timein
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Leicht, David, Daniel Castro-Fresno, Joaquìn Dìaz, and Christian Baier. "Multidimensional Construction Planning and Agile Organized Project Execution—The 5D-PROMPT Method." Sustainability 12, no. 16 (2020): 6340. http://dx.doi.org/10.3390/su12166340.

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Although tremendous technological and strategic advances have been developed and implemented in the construction sector in recent years, there is substantial room for improvement in the areas of productivity growth, project performance, and schedule reliability. Thus, the present paper seeks to discover why the currently applied scheduling tools and the latest agile-based project organization approaches have not yet achieved their full potential. A missing interlinkage between the project’s design, cost, and time aspects within the project design phase and its sparse utilization throughout pro
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Pai, Kai-Jun. "A Reformatory Model Incorporating PNGV Battery and Three-Terminal-Switch Models to Design and Implement Feedback Compensations of LiFePO4 Battery Chargers." Electronics 8, no. 2 (2019): 126. http://dx.doi.org/10.3390/electronics8020126.

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This study developed and implemented a LiFePO4 battery pack (LBP) rapid charger. Using the three-terminal switch and partnership for a new generation of vehicles (PNGV) battery models, this study could obtain a small-signal system matrix to derive transfer functions and further analyze frequency responses for the charge voltage and current loops; therefore, both voltage and current feedback controllers could be designed to fulfill the constant-voltage (CV) and constant-current (CC) charges. To address practical applications, the proposed equivalent model also considered the wire resistance-ind
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Турна, Рустем Юсуфович. "РАЗРАБОТКА КОНЦЕПЦИИ ДВУХФАЗНОЙ СИСТЕМЫ ТЕПЛООТВОДА СПУТНИКА". Aerospace technic and technology, № 1 (26 лютого 2021): 31–46. http://dx.doi.org/10.32620/aktt.2021.1.04.

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For spacecraft (SC) with power unit capacity more than 4 ... 6 kW promising construction of thermal control system (TCS) based on two-phase mechanically pumped loops (2PMPL). The development of 2PMPL has been carried out quite intensively since the early '80s. However, so far there are no examples of practical implementation of such high-power systems. One of the main reasons mentioned is the novelty of the system, and insufficient study of its operation in space conditions, which adds risks. The most important component of such systems is a heat rejection subsystem (HRS), whose task is to rej
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Mirabbasi, S., and K. Martin. "Design of loop filter in phase-locked loops." Electronics Letters 35, no. 21 (1999): 1801. http://dx.doi.org/10.1049/el:19991278.

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SHAHRUZ, S. M. "DESIGN OF HIGH-PERFORMANCE PHASE-LOCKED LOOPS AND SYNTHESIZERS." Journal of Sound and Vibration 244, no. 2 (2001): 367–77. http://dx.doi.org/10.1006/jsvi.2000.3494.

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Golestan, Saeed, Francisco D. Freijedo, and Josep M. Guerrero. "A Systematic Approach to Design High-Order Phase-Locked Loops." IEEE Transactions on Power Electronics 30, no. 6 (2015): 2885–90. http://dx.doi.org/10.1109/tpel.2014.2351262.

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Xu, Hao, and Asad A. Abidi. "Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 7 (2017): 1637–50. http://dx.doi.org/10.1109/tcsi.2017.2679683.

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Dissertations / Theses on the topic "Phase-locked loops – Design and construction"

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Jia, Cheng. "A Delay-Locked Loop for Multiple Clock Phases/Delays Generation." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7470.

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A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several new techniques are used to help enhance the DLLs performance, specifically, to achieve wide lock range, short locking time, and reduced jitter. The DLL can be used for a variety of applications which require precise time intervals or phase shifts. The phase detector (PD), charge pump (CP), and voltage-controlled delay line (VCDL) are the three most important blocks in a DLL. In our research, we have proposed a novel structure which integrates the functionality of both the PD and CP. By using
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Sarivisetti, Gayathri. "Design and Optimization of Components in a 45nm CMOS Phase Locked Loop." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5397/.

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A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a syste
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Nayak, Aravind Ratnakar. "Iterative Timing Recovery for Magnetic Recording Channels with Low Signal-to-Noise Ratio." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5018.

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Digital communication systems invariably employ an underlying analog communication channel. At the transmitter, data is modulated to obtain an analog waveform which is input to the channel. At the receiver, the output of the channel needs to be mapped back into the discrete domain. To this effect, the continuous-time received waveform is sampled at instants chosen by the timing recovery block. Therefore, timing recovery is an essential component of digital communication systems. A widely used timing recovery method is based on a phase-locked loop (PLL), which updates its timing estimates base
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Saint-Laurent, Martin. "Modeling and Analysis of High-Frequency Microprocessor Clocking Networks." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7271.

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Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the
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Ratcliff, Marcus Dai Foster. "Phase locked loop analysis and design." Auburn, Ala, 2008. http://hdl.handle.net/10415/1452.

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Lucas, de Peslouan Pierre-Olivier. "Conception orientée délai : étude, développement et réalisation d’une boucle à verrouillage de phase large bande stabilisée par une boucle à verrouillage de délai." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14265/document.

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L’explosion du marché des télécommunications a donné lieu, lors de ces dernières années, à la multiplication des standards de radiocommunication. De nos jours, l’ensemble de ces moyens de communication utilisés pour le transfert de voix et de données doit être intégré dans les terminaux mobiles. Cependant, cette tendance s’oppose aux contraintes de faible coût qui tendent à diminuer la taille de l’électronique embarquée dans un terminal mobile, mais aussi aux contraintes de diminution de la consommation pour une plus grande autonomie des objets sans fils. C’est donc autour de ces verrous techn
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Zhu, Peiqing. "Design and characterization of phase-locked loops for radiation-tolerant applications." Ann Arbor, Mich. : ProQuest, 2008. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3331229.

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Thesis (Ph.D. in Electrical Engineering)--S.M.U.<br>Title from PDF title page (viewed Mar. 16, 2009). Source: Dissertation Abstracts International, Volume: 69-11, Section: B Adviser: Ping Gui. Includes bibliographical references.
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Sharkia, Ahmad. "On the design of type-i integer-n phase-locked loops." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/54504.

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The phase-locked loop (PLL) is an essential building block of modern communication and computing systems. In a wireless communication system, a PLL is almost always used as the local oscillator (LO) that synthesizes the required frequency for data transmission and reception. In wireline and optical communication systems, PLL-based clock and data recovery (CDR) circuits are often employed for the extraction of the clock signal from the incoming data signal, and aligning the recovered clock edge with the incoming data for optimal bit-error rate (BER) performance. Furthermore, in microprocessor a
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Leung, Chi Tak. "Design of 1-V CMOS RF phase-locked loops and frequency synthesizers /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20LEUNG.

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Barat, Aakriti. "Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1483676715726685.

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Books on the topic "Phase-locked loops – Design and construction"

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Quemada, Carlos. Design methodology for RF CMOS phase locked loops. Artech House, 2009.

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Quemada, Carlos. Design methodology for RF CMOS phase locked loops. Artech House, 2009.

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Phase-locked loop engineering handbook for integrated circuits. Artech House, 2007.

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Microwave and wireless synthesizers: Theory and design. Wiley, 1997.

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Goldberg, Bar-Giora. Digital techniques in frequency synthesis. McGraw-Hill, 1995.

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Digital techniques in frequency synthesis. McGraw-Hill, 1996.

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Wolaver, Dan H. Phase-locked loop circuit design. Prentice Hall, 1991.

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Best, Roland E. Phase-locked loops: Design, simulation, and applications. 4th ed. McGraw-Hill, 1999.

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Phase-locked loops: Design, simulation, and applications. 5th ed. McGraw-Hill, 2003.

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Best, Roland E. Phase-locked loops: Theory, design, and applications. 2nd ed. McGraw-Hill, 1993.

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Book chapters on the topic "Phase-locked loops – Design and construction"

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Brennan, Paul V. "Digital Loop Techniques and Design Methods." In Phase-Locked Loops. Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-14006-0_8.

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Cheema, Hammad M., Reza Mahmoudi, and Arthur H. M. van Roermund. "Design of High Frequency Components." In 60-GHz CMOS Phase-Locked Loops. Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9280-9_4.

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Cheema, Hammad M., Reza Mahmoudi, and Arthur H. M. van Roermund. "Design of Low Frequency Components." In 60-GHz CMOS Phase-Locked Loops. Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9280-9_5.

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Kundert, Ken. "Modeling and Simulation of Jitter in Phase-Locked Loops." In Analog Circuit Design. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-2602-2_16.

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Märzinger, Günter, and Burkhard Neurauter. "Fractional-N Phase Locked Loops and It’s Application in the GSM System." In Analog Circuit Design. Springer US, 2003. http://dx.doi.org/10.1007/0-306-48707-1_6.

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Zhao, Feng, and Fa Foster Dai. "Design and Analysis of QVCO with Various Coupling Techniques." In Low-Noise Low-Power Design for Phase-Locked Loops. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-12200-7_4.

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Zhao, Feng, and Fa Foster Dai. "Introduction." In Low-Noise Low-Power Design for Phase-Locked Loops. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-12200-7_1.

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Zhao, Feng, and Fa Foster Dai. "Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL." In Low-Noise Low-Power Design for Phase-Locked Loops. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-12200-7_2.

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Zhao, Feng, and Fa Foster Dai. "A Wide-Band Low Power BiCMOS PLL." In Low-Noise Low-Power Design for Phase-Locked Loops. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-12200-7_3.

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Zhao, Feng, and Fa Foster Dai. "Design and Analysis of A Low Power QVCO with Capacitive-Coupling Technique." In Low-Noise Low-Power Design for Phase-Locked Loops. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-12200-7_5.

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Conference papers on the topic "Phase-locked loops – Design and construction"

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"PHASE LOCKED LOOPS DESIGN AND ANALYSIS." In 5th International Conference on Informatics in Control, Automation and Robotics. SciTePress - Science and and Technology Publications, 2008. http://dx.doi.org/10.5220/0001485401140118.

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Wey, Chin-Long, Chi-Shu Huang, and Shaolei Quan. "Design of Reliable CMOS Phase-Locked Loops." In 2006 13th IEEE International Conference on Electronics, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icecs.2006.379802.

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Easwaran, Prakash, Prasenjit Bhowmik, and Rupak Ghayal. "Specification Driven Design of Phase Locked Loops." In 2009 22nd International Conference on VLSI Design: concurrently with the 8th International Conference on Embedded Systems. IEEE, 2009. http://dx.doi.org/10.1109/vlsi.design.2009.97.

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Maffezzoni, P., S. Levantino, C. Samori, A. L. Lacaita, D. D'Amore, and M. Santomauro. "Behavioral phase-noise analysis of charge-pump phase-locked loops." In 2011 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2011. http://dx.doi.org/10.1109/ecctd.2011.6043360.

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Chou, Y. S., W. L. Mao, Y. C. Chen, and F. R. Chang. "A Novel Loop Filter Design for Phase-Locked Loops." In 2006 IEEE International Conference on Systems, Man and Cybernetics. IEEE, 2006. http://dx.doi.org/10.1109/icsmc.2006.384563.

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Park, Dongmin, and SeongHwan Cho. "Design techniques for ultra low-power phase-locked loops." In 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2011. http://dx.doi.org/10.1109/mwscas.2011.6026304.

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Daniels, Brian, Gerard Baldwin, and Ronan Farrell. "Modeling and design of high-order phase locked loops." In Microtechnologies for the New Millennium 2005, edited by Jose F. Lopez, Francisco V. Fernandez, Jose Maria Lopez-Villegas, and Jose M. de la Rosa. SPIE, 2005. http://dx.doi.org/10.1117/12.608485.

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Peumans, Dries, Adam Cooman, and Gerd Vandersteen. "Analysis of Phase-Locked Loops using the Best Linear Approximation." In 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). IEEE, 2016. http://dx.doi.org/10.1109/smacd.2016.7520652.

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Althoff, Matthias, Soner Yaldiz, Akshay Rajhans, Xin Li, Bruce H. Krogh, and Larry Pileggi. "Formal verification of phase-locked loops using reachability analysis and continuization." In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2011. http://dx.doi.org/10.1109/iccad.2011.6105400.

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Biggio, Matteo, Federico Bizzarri, Angelo Brambilla, Giorgio Carlini, and Marco Storace. "Reliable and efficient phase noise simulation of mixed-mode integer-N Phase-Locked Loops." In 2013 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2013. http://dx.doi.org/10.1109/ecctd.2013.6662284.

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