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1

Quemada, Carlos. Design methodology for RF CMOS phase locked loops. Artech House, 2009.

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2

Quemada, Carlos. Design methodology for RF CMOS phase locked loops. Artech House, 2009.

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3

Phase-locked loop engineering handbook for integrated circuits. Artech House, 2007.

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4

Microwave and wireless synthesizers: Theory and design. Wiley, 1997.

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5

Goldberg, Bar-Giora. Digital techniques in frequency synthesis. McGraw-Hill, 1995.

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6

Digital techniques in frequency synthesis. McGraw-Hill, 1996.

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7

Wolaver, Dan H. Phase-locked loop circuit design. Prentice Hall, 1991.

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8

Best, Roland E. Phase-locked loops: Design, simulation, and applications. 4th ed. McGraw-Hill, 1999.

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9

Phase-locked loops: Design, simulation, and applications. 5th ed. McGraw-Hill, 2003.

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10

Best, Roland E. Phase-locked loops: Theory, design, and applications. 2nd ed. McGraw-Hill, 1993.

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11

Best, Roland E. Phase-locked loops: Design, simulation, and applications. 3rd ed. McGraw Hill, 1997.

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12

Phase-locked loops: Design, simulation, and applications. 6th ed. McGraw-Hill, 2007.

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13

Aktas, Adem. CMOS PLLs and VCOs for 4G wireless. Kluwer Academic Publishers, 2004.

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14

Mohammed, Ismail, ed. CMOS PLLs and VCOs for 4G wireless. Kluwer, 2004.

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15

Cheema, Hammad M. 60-GHz CMOS Phase-Locked Loops. Springer Science+Business Media B.V., 2010.

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16

Blanchard, Alain. Phase-locked loops: Application to coherent receiver design. Krieger, 1992.

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17

Zhao, Feng, and Fa Foster Dai. Low-Noise Low-Power Design for Phase-Locked Loops. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-12200-7.

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18

1959-, Harjani Ramesh, ed. Design of high performance CMOS voltage-controlled oscillators. Kluwer Academic Publishers, 2003.

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19

Sansen, Willy. Analog Circuit Design: MOST RF Circuits, Sigma-Delta Converters and Translinear Circuits. Springer US, 1996.

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20

Shum, Daniel K. Model and design of cmos phase-locked loop. 1989.

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21

Monolithic phase-locked loops and clock recovery circuits: Theory and design. IEEE Press, 1996.

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22

Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design. Wiley-IEEE Press, 1996.

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23

Razavi, Behzad. Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design. Ieee, 1996.

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24

CMOS PLL Synthesizers: Analysis and Design (The Springer International Series in Engineering and Computer Science). Springer, 2004.

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25

Whitaker, Jerry, Ulrich L. Rohde, and Enrico Rubiola. Microwave and Wireless Synthesizers: Theory and Design. Wiley & Sons, Incorporated, John, 2020.

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26

Rohde, Ulrich L. Microwave and Wireless Synthesizers: Theory and Design. Wiley & Sons, Incorporated, John, 2008.

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27

Whitaker, Jerry, Ulrich L. Rohde, and Enrico Rubiola. Microwave and Wireless Synthesizers: Theory and Design. Wiley & Sons, Limited, John, 2021.

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28

Whitaker, Jerry, Ulrich L. Rohde, and Enrico Rubiola. Microwave and Wireless Synthesizers: Theory and Design. Wiley & Sons, Incorporated, John, 2020.

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29

Digital Frequency Synthesis Demystified : DDS and Fractional-N PLLs (Demystified) (Demystified). Newnes, 1999.

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30

Plassche, Rudy J. van de., Huijsing Johan H. 1938-, and Sansen Willy M. C, eds. Analog circuit design: High-speed analog-to-digital converters, mixed-signal design, PLL's and synthesizers. Kluwer Academic Publishers, 2000.

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31

Rudy J. van de Plassche (Editor), Johan H. Huijsing (Editor), and Willy M.C. Sansen (Editor), eds. High Speed Analog-to-Digital Converters; PLLs and Synthesizers. Springer, 2000.

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32

Best, Roland E. Phase Locked Loops: Theory, Design, and Applications. 3rd ed. Mcgraw-Hill (Tx), 1996.

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33

Phase Locked Loops: Theory, Design, and Applications. Mcgraw-Hill (Tx), 1996.

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34

Architectures for RF frequency synthesizers. Kluwer, 2002.

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35

Vaucher, Cicero S. Architectures for Rf Frequency Synthesizers. Springer, 2011.

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36

Aktas, Adem. Cmos Plls and Vcos for 4G Wireless. Springer, 2013.

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37

Vaucher, Cicero S. Architectures for RF Frequency Synthesizers. Springer, 2002.

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38

Banerjee, Dean. Pll Performance, Simulation, and Design. 3rd ed. Dean Banerjee Pubns, 2003.

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39

Banerjee, Dean. PLL Performance, Simulation, and Design. Dean Banerjee, 2001.

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40

Zhao, Feng, and Fa Foster Dai. Low-Noise Low-Power Design for Phase-Locked Loops: Multi-Phase High-Performance Oscillators. Springer, 2014.

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41

Kennedy, Michael Peter, and Francesco Brandonisio. Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design. Springer, 2016.

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42

Kennedy, Michael Peter, and Francesco Brandonisio. Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design. Springer, 2013.

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43

Razavi, Behzad. Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level. Cambridge University Press, 2019.

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44

Starr, Greg W. Phase Locked Loops and Clock Data Recovery Circuit Design on Nano Cmos Processes. Wiley-Interscience, 2008.

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45

Design of High-Performance CMOS Voltage-Controlled Oscillators. Springer, 2011.

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46

Dai, Liang, and Ramesh Harjani. Design of Higher-Performance CMOS Voltage Controlled Oscillators (The Springer International Series in Engineering and Computer Science). Springer, 2002.

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