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Dissertations / Theses on the topic 'Phase-locked loops – Design and construction'

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Published: 4 June 2021
Last updated: 1 February 2022

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1

Jia, Cheng. "A Delay-Locked Loop for Multiple Clock Phases/Delays Generation." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7470.

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A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several new techniques are used to help enhance the DLLs performance, specifically, to achieve wide lock range, short locking time, and reduced jitter. The DLL can be used for a variety of applications which require precise time intervals or phase shifts. The phase detector (PD), charge pump (CP), and voltage-controlled delay line (VCDL) are the three most important blocks in a DLL. In our research, we have proposed a novel structure which integrates the functionality of both the PD and CP. By using
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2

Sarivisetti, Gayathri. "Design and Optimization of Components in a 45nm CMOS Phase Locked Loop." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5397/.

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A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a syste
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3

Nayak, Aravind Ratnakar. "Iterative Timing Recovery for Magnetic Recording Channels with Low Signal-to-Noise Ratio." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5018.

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Digital communication systems invariably employ an underlying analog communication channel. At the transmitter, data is modulated to obtain an analog waveform which is input to the channel. At the receiver, the output of the channel needs to be mapped back into the discrete domain. To this effect, the continuous-time received waveform is sampled at instants chosen by the timing recovery block. Therefore, timing recovery is an essential component of digital communication systems. A widely used timing recovery method is based on a phase-locked loop (PLL), which updates its timing estimates base
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4

Saint-Laurent, Martin. "Modeling and Analysis of High-Frequency Microprocessor Clocking Networks." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7271.

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Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the
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5

Ratcliff, Marcus Dai Foster. "Phase locked loop analysis and design." Auburn, Ala, 2008. http://hdl.handle.net/10415/1452.

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6

Lucas, de Peslouan Pierre-Olivier. "Conception orientée délai : étude, développement et réalisation d’une boucle à verrouillage de phase large bande stabilisée par une boucle à verrouillage de délai." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14265/document.

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L’explosion du marché des télécommunications a donné lieu, lors de ces dernières années, à la multiplication des standards de radiocommunication. De nos jours, l’ensemble de ces moyens de communication utilisés pour le transfert de voix et de données doit être intégré dans les terminaux mobiles. Cependant, cette tendance s’oppose aux contraintes de faible coût qui tendent à diminuer la taille de l’électronique embarquée dans un terminal mobile, mais aussi aux contraintes de diminution de la consommation pour une plus grande autonomie des objets sans fils. C’est donc autour de ces verrous techn
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7

Zhu, Peiqing. "Design and characterization of phase-locked loops for radiation-tolerant applications." Ann Arbor, Mich. : ProQuest, 2008. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3331229.

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Thesis (Ph.D. in Electrical Engineering)--S.M.U.<br>Title from PDF title page (viewed Mar. 16, 2009). Source: Dissertation Abstracts International, Volume: 69-11, Section: B Adviser: Ping Gui. Includes bibliographical references.
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8

Sharkia, Ahmad. "On the design of type-i integer-n phase-locked loops." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/54504.

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The phase-locked loop (PLL) is an essential building block of modern communication and computing systems. In a wireless communication system, a PLL is almost always used as the local oscillator (LO) that synthesizes the required frequency for data transmission and reception. In wireline and optical communication systems, PLL-based clock and data recovery (CDR) circuits are often employed for the extraction of the clock signal from the incoming data signal, and aligning the recovered clock edge with the incoming data for optimal bit-error rate (BER) performance. Furthermore, in microprocessor a
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9

Leung, Chi Tak. "Design of 1-V CMOS RF phase-locked loops and frequency synthesizers /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20LEUNG.

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10

Barat, Aakriti. "Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1483676715726685.

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11

Cheng, Shanfeng. "Design of CMOS integrated phase-locked loops for multi-gigabits serial data links." Texas A&M University, 2006. http://hdl.handle.net/1969.1/4954.

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High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyze
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12

Gal, George. "Design of fractional-N phase locked loops for frequency synthesis from 30 to 40 GHz." Thesis, McGill University, 2013. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=114297.

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High-frequency fractional-N PLLs in CMOS technology in the 30 to 40 GHz are very dicult to design when considering power, area, phase noise requirements and frequency range of operation. One of the diculties is to synthesize the loop lter of the PLL such that it meets the phase noise characteristics using the information available for all the components that make up the PLL. At the same time, predicting the phase noise output of the PLL using extracted layout results takes a long time to simulate and often the solution does not converge, thereby lengthening the design cycle. This thesis propos
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13

Vollenbruch, Ulrich. "Design of reconfigurable digital phase locked loops for multi-standard, multi-band mobile radio terminals." München Verl. Dr. Hut, 2008. http://d-nb.info/992163412/04.

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14

SINGH, GUNEET. "HIGH-FREQUENCY CHARGE-PUMP BASED PHASE-LOCKED LOOP DESIGN AND IT'S CHARACTERIZATION USING VERILOG-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155077793.

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15

Lei, Feiran. "Injection Locked Synchronous Oscillators (SOs) and Reference Injected Phase-Locke Loops (PLL-RIs)." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492789278258943.

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16

Barale, Francesco. "Frequency dividers design for multi-GHz PLL systems." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24610.

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17

Brandano, Davide. "Design of Frequency divider with voltage vontrolled oscillator for 60 GHz low power phase-locked loops in 65 nm RF CMOS." Doctoral thesis, Universitat Politècnica de Catalunya, 2012. http://hdl.handle.net/10803/81303.

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Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 GHz is in today's technology a great challenge. A key reason is the inaccuracy of CMOS active and pas
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18

Shariat, Yazdi Ramin. "Mixed signal design flow, a mixed signal PLL case study." Thesis, University of Waterloo, 2001. http://hdl.handle.net/10012/916.

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Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is
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19

Long, John R. (John Robert) Carleton University Dissertation Engineering Electrical. "High frequency integrated circuit design in BICMOS for monolithic timing recovery." Ottawa, 1992.

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20

Mukherjee, Tonmoy Shankar. "High performance, low-power and robust multi-gigabit wire-line design." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/39515.

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The object of this research is to develop robust wire-line systems which demonstrate high performance while simultaneously consuming low power. The main focus of this work is the Clock and Data Recovery (CDR) system, which is the primary circuit of any modern wire-line transceiver. Different techniques starting from circuit-level to system-level have been investigated in this work to improve the performance of multi-gigabit CDRs. A 62 GHz bandwidth amplifier has been presented to address the need for a scalable amplifier for CDR needs. A new technique has been proposed to improve the radiation
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Barale, Francesco. "Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37216.

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In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either h
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22

Petura, Oto. "True random number generators for cryptography : Design, securing and evaluation." Thesis, Lyon, 2019. http://www.theses.fr/2019LYSES053.

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Les nombres aléatoires sont essentiels pour les systèmes cryptographiques modernes. Ils servent de clés cryptographiques, de nonces, de vecteurs d’initialisation et de masques aléatoires pour la protection contre les attaques par canaux cachés. Dans cette thèse, nous traitons des générateurs de nombres aléatoires dans les circuits logiques (FPGA et ASIC). Nous présentons les méthodes fondamentales de génération de nombres aléatoires dans des circuits logiques. Ensuite, nous discutons de différents types de TRNG en utilisant le jitter d’horloge comme source d’aléa. Nous faisons une évaluation r
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23

Nagam, Shravan Siddartha. "High Performance Sub-Sampling Phase Detector based Ring-Oscillator Phase-Locked Loops." Thesis, 2020. https://doi.org/10.7916/d8-7t2x-9523.

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Phase locked loops (PLLs) used to generate high precision clocks are integral components in the majority of modern day electronic systems such as Analog-to-Digital Converters (ADC), Digital-to-Analog Converters (DAC), transceivers, processors, etc. The accuracy of this clocks that effects the overall performance of the system is measured in terms of its jitter, phase noise, spurious tones, etc. For example, the jitter in an ADC sampling clock can result in uncertainty of the sampling instant and can result in degradation of the effective number of bits (ENOB) of the ADC, phase noise on the oth
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24

Jung, Seokmin. "Design of a low jitter digital PLL with low input frequency." Thesis, 2012. http://hdl.handle.net/1957/30105.

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Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as frequency synthesizers and inter-chip communication interfaces. As process technologies advance and grow in complexity, the challenge of maintaining required analog elements and performance for use in circuits such as PLLs grows. Recently, digital PLL (DPLL) has emerged as an alternative to analog PLL to overcome many constraints such as low supply voltage, poor analog transis
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25

Wang, Xin 1971. "Interference cancellation in broadband wireless systems utilizing phase aligned injection-locked oscillators." 2008. http://hdl.handle.net/2152/17986.

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Linearity enhancement, especially within the front end of a wireless receiver IC design, is highly desirable since it allows the front-end to withstand strong interferers from co-existing communication standards or other wireless radiators. We propose an interferer suppression method based on feed-forward cancellation that uses an injectionlocked oscillator (ILO) to extract the interferer from the incident spectrum. The technique is expected to be useful in environments where a strong narrowband interferer appears along with a wideband desired signal, such as ultra-wideband (UWB) and emerging
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26

"A 1.5 V, 2.4 GHz monolithic CMOS sub-integer-N frequency synthesizer for WLAN application." Thesis, 2011. http://library.cuhk.edu.hk/record=b6075113.

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This thesis presents the design of a 2.4 GHz sub-integer-N PLL for IEEE 802.llb/g WLAN applications. The proposed PLL not only acquires the advantages of the integer-N PLL, such as simple structure and good spurious performance, but also offers some benefits (for example, faster settling time and better phase noise performance) as in the fractional-N PLL design. In this design, a novel quadrature-input programmable fractional frequency divider provides fractional division ratio in steps of 0.5 by the phase-switching technique. Its key building block is a dual divide-by-4 injection-locked frequ
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27

"LTCC low phase noise voltage controlled oscillator design using laminated stripline resonators." 2002. http://library.cuhk.edu.hk/record=b5891066.

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Cheng Sin-hang.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.<br>Includes bibliographical references (leaves 90-92).<br>Abstracts in English and Chinese.<br>Chapter Chapter 1 --- Introduction --- p.1<br>Chapter Chapter 2 --- Theory of Oscillator Design --- p.4<br>Chapter 2.1 --- Open-loop approach --- p.4<br>Chapter 2.2 --- One-port approach --- p.6<br>Chapter 2.3 --- Two-port approach --- p.9<br>Chapter 2.4 --- Voltage controlled oscillator (VCO) design --- p.10<br>Chapter 2.4.1 --- Active device selection and biasing --- p.11<br>Chapter 2.4.2 --- Feedback circuit design
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28

"Design and implementation of fully integrated low-voltage low-noise CMOS VCO." 2002. http://library.cuhk.edu.hk/record=b5891102.

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Yip Kim-fung.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.<br>Includes bibliographical references (leaves 95-100).<br>Abstracts in English and Chinese.<br>Abstract --- p.I<br>Acknowledgement --- p.III<br>Table of Contents --- p.IV<br>Chapter Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Motivation --- p.1<br>Chapter 1.2 --- Objective --- p.6<br>Chapter Chapter 2 --- Theory of Oscillators --- p.7<br>Chapter 2.1 --- Oscillator Design --- p.7<br>Chapter 2.1.1 --- Loop-Gain Method --- p.7<br>Chapter 2.1.2 --- Negative Resistance-Conductance Method --- p.8<br>Chapte
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Bhagavatheeswaran, Shanthi S. "Design methodology for low-jitter phase-locked loops." Thesis, 2001. http://hdl.handle.net/1957/32786.

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This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case) and 125 times faster (worst case). The accuracy of the model depends on the accurate evaluation of the non-linear transfer function from the various noisy nodes to the output. By modeling the noise transfer function of the circuit as closely as possible, 100% accuracy for the behav
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30

Su, Chao-Yuan, and 蘇昭源. "CMOS Building Blocks Design for GHz Phase-Locked Loops." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/41505508972887326545.

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碩士<br>國立雲林科技大學<br>電子與光電工程研究所碩士班<br>101<br>A high-speed CMOS 1/2 frequency divider is presented. Using fewer transistors and only N-type MOS transistors in the regenerative circuits of the latches, the frequency divider achieves higher speed through the reduced capacitances at the output nodes and transconductance. The goal of device sizing is to achieve highest possible frequency operation. The frequency divider post-layout simulation achieves maximum input frequency of 5.2GHz. The average power consumption of this frequency divider is 3.59mW, and the active area is 128μm×130μm. It is suitable
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31

Chang, Tzu Shue, and 張子修. "Design of 900M Hz Low Jitter Phase Locked Loops." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/50837204310500182054.

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碩士<br>國立交通大學<br>電子工程系<br>90<br>The purpose of this thesis is to reduce noises and non-ideal effects on the PLL circuit operation for jitter suppression. We used a real PLL circuit simulation to analyze the reason that causes the jitter and find out possible solutions. Our study focused on the analysis of the circuit that generates delay time in a ring oscillator. We found that better noise rejection could be achieved through making the I-V characteristic of the load resistance of the buffer as linear as possible or limiting the amplitude of the VCO as small as possible. We also proved that the
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32

Lin, Chao-Zheng, and 林朝正. "The Design of Microwave CMOS Monolithic Phase-Locked Loops." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/37864x.

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碩士<br>國立中正大學<br>電機工程研究所<br>102<br>This thesis implements two types of PLL, integer-N and fractional-N. Implemented in 0.18 μm CMOS technology, the first circuit is a 1.2 GHz integer-N PLL, using push-push cross-coupled voltage-control oscillator as circuit core. In addition, the second harmonic output port can provide 2.4 GHz signal. The measured phase noise of 1.2 GHz PLL is -117.1 dBc/Hz at 1 MHz offset. Implemented in CMOS 90 nm, the second circuit based on the first one and increased VCO fundamental output frequency at 15 GHz. The second harmonic output provided sub-harmonic mixer as LO in
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liao, chih-chiang, and 廖志強. "Design and Implementaion of CMOS Adaptive-Bandwidth Phase-Locked Loops." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/81763595530317482421.

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碩士<br>國立雲林科技大學<br>電子與資訊工程研究所<br>93<br>Phase-Locked Loops are integral components of contemporary digital and mixed signals ICs. Integrating these semi-analog blocks in the environment of a large IC requires dealing effectively with clock Jitter and clock skew. Besides, PLL was to reduces to the unavoidable supply and substrate noise. A self– adapted structure was employed. Self-adapted structure is combined with a replica-bias and a width-to-digital circuit. By scaling the charge pump current and the output resistance of the regulating amplifier ,the loop of system achieve a wide ba
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34

Li, Sin-Jhih. "Design and Implementation of High-frequency CMOS Phase-locked Loops." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2508200816302900.

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Chiu, Wei-Hao, and 邱威豪. "Design of Fast-Settling and Low-Noise Phase-Locked Loops." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/76690801740410403506.

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博士<br>國立臺灣大學<br>電子工程學研究所<br>100<br>Phase-locked loops (PLL) are the key component in various systems. According to the operated principles, there are two different PLL types, the integer-N PLL and the fractional-N PLL. Both types are employed under different environments, but each type suffers from the different design tradeoffs. For the integer-N PLL, the selectable reference frequency is associated with specific channel spacing. It then suffers from narrow loop bandwidth when demanding narrow channel spacing, degrading the frequency-settling time. Next, for the fractional-N PLL, it is known
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Li, Sin-Jhih, and 黎信志. "Design and Implementation of High-frequency CMOS Phase-locked Loops." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/48353649274285072838.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>96<br>This thesis illustrates the implementation of the high frequency phase-locked loops (PLLs). In order to reduce the output jitter, several strategies are presented, which are suitable for high speed PLL design. The thesis is organized as six chapters. The first chapter is the introduction. In chapter 2, the background knowledge for the PLL design is overviewed. In chapter 3, a PLL with multi-phase control architecture is proposed. Since the proposed architecture effectively suppresses the ripple of the controlled voltage, the jitter resulted from the reference
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Yen, Wen-Chang, and 顏文章. "Design and Implementation of Wideband Synthesizers Using Offset Phase-Locked Loops." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/61919889246856679336.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>98<br>The thesis uses an up-down conversion architecture to realize a wideband frequency synthesizer for digital video broadcasting (DVB) transmission system. At first, the theoretical analysis of this architecture is performed to understand the mechanism to suppress the phase noise in an optimal way. Then, the simulations using Matlab and ADS are carried out to predict the phase noise performance. Based on the above efforts, a 50 MHz ~ 1 GHz wideband frequency synthesizer hybrid circuit is implemented and its phase noise performance, corresponding to different cho
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38

Tsai, Kun-Hung, and 蔡坤宏. "Design and Implementation of Phase-Locked Loops in Millimeter-Wave Bands." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/60031162966800926464.

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博士<br>國立臺灣大學<br>電子工程學研究所<br>99<br>Due to the remarkable development in CMOS technology, it is possible to design low-cost, low-power, and high-speed communication systems in millimeter-wave (MMW) bands by advanced CMOS process. For example, the building blocks for 60GHz indoor high-speed data link, 77GHz automotive radar, and 94GHz imaging system have been realized in nanoscale CMOS technology. In these communication systems, phase-locked loops (PLLs) usually play important roles to serve as local oscillator (LO) for signal conversion or provide reference clock for data sampling procedure. In
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CHIA-YUNG, KUO, and 郭加泳. "The Theory and Design of 5GHz CMOS Phase-Locked-Loops Prescaler." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/29719566167614755839.

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碩士<br>國立臺灣大學<br>電機工程學研究所<br>91<br>Phase-locked loops (PLL) are used extensively in communications systems, such as frequency synthesizers and clock recovery circuits. A frequency synthesizer generates a new frequency from a single stable reference frequency. Mostly a crystal oscillator is used for the reference frequency. Most of the frequency synthesizer employ a Phase Locked Loops circuit, as this technique offer many advantages such as minimum complex architecture, low power consumption and a maximum use of Large Scale Integration technology. The accuracy of the required frequencies is very
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40

Teng, Kuang-Fu, and 鄧匡復. "Design and Implementation of Delay-Locked Loops with Static Phase Error Calibration." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/51519481036341790529.

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碩士<br>國立臺灣大學<br>電機工程學研究所<br>97<br>Conventional CMOS charge-pump circuits have some current mismatch problems. The current mismatch induces a phase error which deteriorates the performance of delay-locked loop systems or phase-lock loop systems. In this dissertation, we describes on the design and application of delay-locked loop systems and we use three architectures and circuits to improve the phase error in the synchronization systems, and there is no extra replica charge-pump needed; these architectures and circuits have been fabricated in 0.18µm CMOS to verify the circuits technique and me
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Lin, Bo-Yu, and 林柏宇. "Analysis and Design of Injection-Locked Frequency Dividers and Phase-Locked Loops in Millimeter-Wave Bands." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/95775669833560948785.

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博士<br>國立臺灣大學<br>電子工程學研究所<br>100<br>Since the modern CMOS technology is advanced to a nanoscale, the speed of the active devices is dramatically increased. It inspired many millimeter-wave applications; such as 60GHz indoor high-speed data link, 24/77GHz automotive radar, 94GHz imaging system and 140GHz point-to-point communication. In these applications, it is essential to generate a clean and stable clock by using millimeter-wave Phase-Locked Loop (PLL). Furthermore, the design of the frequency divider which operates at the highest operation frequency also poses great challenge. It is a chall
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Ming, Huang, and 黃明智. "Design and Evaluation for High Performance 2.4GHz Phase Locked Loops with Modularized Scheme." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/58873554550347400220.

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碩士<br>國立高雄第一科技大學<br>電腦與通訊工程所<br>92<br>In any module of receiver, RF front-end is the most significant part in the system. It decides how the receiver uses channel, distance, communication quality, and receiving sensitivity. Among them the channel decidability of RF module depends much more on Phase Locked Loops (PLLs). In this thesis, we discuss mainly the design of multi-channel PLLs and voltage controlled oscillator IC (VOC IC), and simulate the circuits to find out the best performed multi-channel PLLs and VCO IC by using Advanced Design Software (ADS)[26]. Using the modular inductance [1],
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Chen, Huei, and 陳慧. "Design of Wide-Range Low-Power Delay- Locked Loops With Multi-Phase Outputs." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/82102389804988528038.

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碩士<br>國立東華大學<br>電機工程學系<br>101<br>According to the advances in process technology, The development of VLSI systems is toward to system-on-a-chip(SoC). The system integration of each circuit module needs accurate clock signals to be synchronized. Delay-locked loops (DLLs) and Phase-locked loops (PLLs) are widely used for clock synchronization. DLLs are more suitable for reducing the clock delay, avoiding the clock deskew, and maintaining the clock synchronization compared to PLLs. Because of its low jitter clock, easy design, and inherently stable. In this thesis, two circuits are mainly design
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Zheng, Shun-Sheng, and 鄭舜升. "Design of Charge Pump in CMOS Phase-Locked Loops for DVB-T Applications." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/462y69.

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碩士<br>國立交通大學<br>電信工程系所<br>94<br>This thesis, based on tsmc 0.18um CMOS 1P6M process , PLL, is designed to apply to Local oscillator. PLL includes phase frequency detector、charge pump、loop filter、voltage control oscillator and frequency divider. In the design of DVB-T tuner , we have chosen the input 1MHz of reference frequency, with the system supply voltage at 1.8V. What phase frequency detector adopts is operational high-frequency. Charge pump possesses fast-switching speed, adding feedback amplifier to improve the problem of mismatched current . In terms of loop filter , we adopt two order
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Chen, Yu-Cheng, and 陳佑政. "Analysis and Design of Phase-Locked Loops for Reducing Spur and Dynamic Sensitivity." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/69788565619960298207.

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博士<br>國立臺灣大學<br>電機工程學研究所<br>100<br>In addition to the phase noise, the output signal of a phase-locked loop (PLL) includes the unwanted spur. The spectral purity of the output signal is determined by the two types of noise. In wireless communication receivers, the spur is a troublesome problem, affecting the signal to noise ratio. The easiest approach to improving the spur performance is to reduce the loop bandwidth. However, this solution affects the phase noise characteristic of the output signal. Another straightforward solution is to decrease the gain of the voltage-controlled oscillator (
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Hwang, Hwong-Wen, and 黃鴻文. "Design and Performance Evaluation for Phase Locked Loops with Multi-channel in GSM band." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/64477962770776605571.

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碩士<br>國立高雄第一科技大學<br>電腦與通訊工程所<br>91<br>This thesis conducts a high performance of Phase Locked Loops (PLLs) in GSM band. It is assumed that the modulated technology to send data with high frequency but it can not transmit as long distance in wireless environment and the demodulation technology in receiver, is restored original data from RF front-end to baseband. From the wireless system, the channel band limited, we should be to solve the band limited by the multiplex technology only. In the wireless communication, we must have a high stable local oscillator as show in conventional super hete
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Lee, Hong-Bing, and 李宏斌. "Research on the Design of Low Voltage CMOS Phase Locked Loops for Clock Generator." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/99611381305822154332.

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碩士<br>中原大學<br>電子工程研究所<br>89<br>The aim of this thesis is to design a low voltage CMOS phase locked loop (PLL) for clock generator applications. The charge pump concept has been used in the PLL implementation and the core circuit blocks of the system consist of a phase frequency detector, charge pump, voltage controlled oscillator, loop filter and divider. This thesis adopts some methods below in order to improve the noise and stability performance of the PLL. Firstly, the frame of pre-charge stage is used to eliminate the noise of dead-zone in phase frequency detector. Secondly, the
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Chu, Wei-Jung, and 朱薇蓉. "Design of All-Digital Built-In Self-Test Circuit for All-Digital Phase-Locked Loops." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/22397462569087930795.

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碩士<br>國立中正大學<br>資訊工程研究所<br>99<br>In this thesis, we propose a design of an all-digital built-in self-test circuit for all-digital phase-locked loops (ADPLLs). Testing circuits are embedded on chip to test the circuit instead of using external instruments. In this way, it not only can save the cost of external instruments, but also can decrease error of measured results which needs to pass through the I/O Pads. Because the external instruments would produce the noise influence and the ground bounce caused by the I/O pad transitions affects the measurement, off-chip measurement circuits will mak
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Chen, Yan-Jin, and 陳彥瑾. "Research on the Design of Low Voltage Charge-Pump Phase Locked Loops for Clock Generator." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/t8s27k.

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碩士<br>中原大學<br>電子工程研究所<br>91<br>The aim of this thesis is to design a low voltage charge pump phase locked loop ( CP-PLL ) for clock generator applications. The core circuit blocks of the system consist of a phase frequency detector, charge pump, voltage controlled oscillator, loop filter, divider and crystal oscillator. PLLs contain several circuits: First, the frame of nc-PFD is used to eliminate the dead-zone in the PLL. With an added modified circuit, the proposed PFD overcomes the disadvantage of nc-PFD. The outputs UP and down ( DN ) will never rise at the same time. Second, the VCO is b
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Wang, Yi-Xiao, and 王義瀟. "Design of Low Power Cascaded Phase-Locked-Loops in 65nm CMOS technology for Implantable Medical Devices." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/h88736.

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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>102<br>In recent decades, with the fast development of the CMOS technology, people start to focus on the research on the probability of the combination of CMOS technology with other academic area such as medical. In this years, the implanted biomedical devices becomes a hot issue and many standards for medical devices have been published these years. The MedRadio (Medical Device Radiocommunications Service) Band is announced by Federal Communications Commission (FCC) in 2009 for implanted communication devices. In this thesis, a low power cascaded Phase-Lock
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