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Journal articles on the topic 'Phase-locked loops – Design and construction'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Zhang, Chunyu, Shouxiang Wang, Ruxun He, Qianyu Zhao, and Kai Wang. "Design and Construction of a Low Cost All-Digital Phase Locked Loop Based on Field Programmable Gate Array." Journal of Physics: Conference Series 1972, no. 1 (2021): 012054. http://dx.doi.org/10.1088/1742-6596/1972/1/012054.

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2

Mutter, Manfred, Karl-Heinz Altmann та Thomas Vorherr. "The Construction of New Proteins. II. Design, Synthesis and Conformational Studies of Folding Units with βαβ-Topology". Zeitschrift für Naturforschung B 41, № 10 (1986): 1315–22. http://dx.doi.org/10.1515/znb-1986-1020.

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The design, synthesis and preliminary conformational studies of two polypeptides exhibiting βαβ-type folding topologies are presented. In the design of the model peptides the general concept for the construction of new proteins developed in the preceeding paper was applied. According to this strategy, amphiphilic helices and β-sheets are linked together via hydrophilic loops to attain three-dimensional structures of higher order (‘supersecondary structures’). Computer-assisted molecular modelling served as a valuable tool for minimizing conformational constraints within the molecules. The 38

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3

Elvekrok, Dag Runar. "Concurrent Engineering in Ship Design." Journal of Ship Production 13, no. 04 (1997): 258–69. http://dx.doi.org/10.5957/jsp.1997.13.4.258.

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Concurrent engineering is a systematic approach for integration and concurrent design of products. The systematic approach intends to consider all elements influencing the products and their related processes during the product life-cycle, such as manufacturing, support, costs, quality, user requirements etc. Especially the engineering design phase should be considered for improvements. This paper presents some of the major and most acknowledged concepts, ideas and principles of concurrent engineering. They are among others:trends and demands to product development time and product life-timein

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4

Leicht, David, Daniel Castro-Fresno, Joaquìn Dìaz, and Christian Baier. "Multidimensional Construction Planning and Agile Organized Project Execution—The 5D-PROMPT Method." Sustainability 12, no. 16 (2020): 6340. http://dx.doi.org/10.3390/su12166340.

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Although tremendous technological and strategic advances have been developed and implemented in the construction sector in recent years, there is substantial room for improvement in the areas of productivity growth, project performance, and schedule reliability. Thus, the present paper seeks to discover why the currently applied scheduling tools and the latest agile-based project organization approaches have not yet achieved their full potential. A missing interlinkage between the project’s design, cost, and time aspects within the project design phase and its sparse utilization throughout pro

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5

Pai, Kai-Jun. "A Reformatory Model Incorporating PNGV Battery and Three-Terminal-Switch Models to Design and Implement Feedback Compensations of LiFePO4 Battery Chargers." Electronics 8, no. 2 (2019): 126. http://dx.doi.org/10.3390/electronics8020126.

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This study developed and implemented a LiFePO4 battery pack (LBP) rapid charger. Using the three-terminal switch and partnership for a new generation of vehicles (PNGV) battery models, this study could obtain a small-signal system matrix to derive transfer functions and further analyze frequency responses for the charge voltage and current loops; therefore, both voltage and current feedback controllers could be designed to fulfill the constant-voltage (CV) and constant-current (CC) charges. To address practical applications, the proposed equivalent model also considered the wire resistance-ind

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6

Турна, Рустем Юсуфович. "РАЗРАБОТКА КОНЦЕПЦИИ ДВУХФАЗНОЙ СИСТЕМЫ ТЕПЛООТВОДА СПУТНИКА". Aerospace technic and technology, № 1 (26 лютого 2021): 31–46. http://dx.doi.org/10.32620/aktt.2021.1.04.

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For spacecraft (SC) with power unit capacity more than 4 ... 6 kW promising construction of thermal control system (TCS) based on two-phase mechanically pumped loops (2PMPL). The development of 2PMPL has been carried out quite intensively since the early '80s. However, so far there are no examples of practical implementation of such high-power systems. One of the main reasons mentioned is the novelty of the system, and insufficient study of its operation in space conditions, which adds risks. The most important component of such systems is a heat rejection subsystem (HRS), whose task is to rej

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7

Mirabbasi, S., and K. Martin. "Design of loop filter in phase-locked loops." Electronics Letters 35, no. 21 (1999): 1801. http://dx.doi.org/10.1049/el:19991278.

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8

SHAHRUZ, S. M. "DESIGN OF HIGH-PERFORMANCE PHASE-LOCKED LOOPS AND SYNTHESIZERS." Journal of Sound and Vibration 244, no. 2 (2001): 367–77. http://dx.doi.org/10.1006/jsvi.2000.3494.

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9

Golestan, Saeed, Francisco D. Freijedo, and Josep M. Guerrero. "A Systematic Approach to Design High-Order Phase-Locked Loops." IEEE Transactions on Power Electronics 30, no. 6 (2015): 2885–90. http://dx.doi.org/10.1109/tpel.2014.2351262.

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10

Xu, Hao, and Asad A. Abidi. "Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 7 (2017): 1637–50. http://dx.doi.org/10.1109/tcsi.2017.2679683.

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11

CHEN, XI, BINGO WING-KUEN LING, and LI-MIN SUN. "NONLINEAR BEHAVIORS OF GEAR SHIFTING DIGITAL PHASE LOCKED LOOPS." International Journal of Bifurcation and Chaos 22, no. 08 (2012): 1250204. http://dx.doi.org/10.1142/s0218127412502045.

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Applying gear shifting algorithms to the implementation of Phase Locked Loops (PLLs) can significantly improve their performances. However, the behaviors of gear shifting digital PLLs (GSDPLLs) have not been fully studied due to the existence of newly adaptive control parameters. These parameters play a very important role in the design of GSDPLLs. In this paper, various nonlinear behaviors of GSDPLLs including the steady state periodic behaviors, divergent behaviors and chaotic behaviors, are studied. In particular, the effects of the initial conditions of GSDPLLs on their dynamical behaviors

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12

CHAU, YAWGENG A., and CHEN-FENG CHEN. "ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS." Journal of Circuits, Systems and Computers 20, no. 06 (2011): 1037–49. http://dx.doi.org/10.1142/s0218126611007748.

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The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency

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13

Golestan, Saeed, Mohammad Monfared, and Francisco D. Freijedo. "Design-Oriented Study of Advanced Synchronous Reference Frame Phase-Locked Loops." IEEE Transactions on Power Electronics 28, no. 2 (2013): 765–78. http://dx.doi.org/10.1109/tpel.2012.2204276.

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14

Loveless, T. D., L. W. Massengill, B. L. Bhuva, W. T. Holman, A. F. Witulski, and Y. Boulghassoul. "A Hardened-by-Design Technique for RF Digital Phase-Locked Loops." IEEE Transactions on Nuclear Science 53, no. 6 (2006): 3432–38. http://dx.doi.org/10.1109/tns.2006.886203.

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15

Kratyuk, Volodymyr, Pavan Kumar Hanumolu, Un-Ku Moon, and Kartikeya Mayaram. "A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 3 (2007): 247–51. http://dx.doi.org/10.1109/tcsii.2006.889443.

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16

Yu, Gui Yin, and Lu Zhang. "Design of New Automobile Rotational Speed Measuring Device." Advanced Materials Research 383-390 (November 2011): 325–28. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.325.

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The automobile rotational speed measurement device, consisting of information collecting and processing, phase-locked loops, wave shaping, frequency division and display, can be applied for measurement of the rotational speed of automobiles with various cylinders.

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17

Chou, Yung-Shan, Yu-Cheng Chen, and Fan-Ren Chang. "Loop Filter Design for Phase-Locked Loops with Guaranteed Lock-in Range." IFAC Proceedings Volumes 41, no. 2 (2008): 6410–15. http://dx.doi.org/10.3182/20080706-5-kr-1001.01081.

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18

Arakali, Abhijith, Srikanth Gondi, and Pavan Kumar Hanumolu. "Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 11 (2010): 2880–89. http://dx.doi.org/10.1109/tcsi.2010.2052507.

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19

Marucci, Giovanni, Salvatore Levantino, Paolo Maffezzoni, and Carlo Samori. "Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 1 (2014): 26–36. http://dx.doi.org/10.1109/tcsi.2013.2268514.

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20

Golestan, Saeed, Malek Ramezani, Josep M. Guerrero, Francisco D. Freijedo, and Mohammad Monfared. "Moving Average Filter Based Phase-Locked Loops: Performance Analysis and Design Guidelines." IEEE Transactions on Power Electronics 29, no. 6 (2014): 2750–63. http://dx.doi.org/10.1109/tpel.2013.2273461.

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21

Suplin, V., and U. Shaked. "MixedH?/H2 design of digital phase-locked loops with polytopic-type uncertainties." International Journal of Robust and Nonlinear Control 12, no. 14 (2002): 1239–51. http://dx.doi.org/10.1002/rnc.718.

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22

Rodriguez, Gilles, Philippe Amphoux, David Plancq, Edwige Richebois, Frédéric Varaine, and Philippe Bigeon. "The knowledge management on the design of a generation IV sodium fast reactor project at CEA. The case and methodology applied on the Astrid project." EPJ Nuclear Sciences & Technologies 6 (2020): 53. http://dx.doi.org/10.1051/epjn/2020016.

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From 2010 to 2019, the French Alternative Energies and Atomic Commission (CEA) associated with industrial partners realized the Basic Design of a prototype Sodium Fast Reactor. This project was called ASTRID (ASTRID for Advanced Sodium Technological Reactor for Industrial Demonstration). ASTRID design studies were financed through governmental funds until the end of the basic design. These funds covered also the design studies for the core manufacturing workshop, the refurbishment or construction of large test loops. One year before the term of this Basic Design phase (in 2018), industrial par

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23

Herzel, Frank, and Dietmar Kissinger. "Design and layout strategies for integrated frequency synthesizers with high spectral purity." International Journal of Microwave and Wireless Technologies 9, no. 9 (2017): 1791–97. http://dx.doi.org/10.1017/s1759078717000654.

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Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a

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24

Rashed, Mohamed, Christian Klumpner, and Greg Asher. "Dynamic phasor analysis and design of phase-locked loops for single phase grid connected converters." COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 34, no. 4 (2015): 1122–43. http://dx.doi.org/10.1108/compel-04-2014-0090.

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Purpose – The purpose of the paper is to introduce the dynamic phasor modelling (DPM) approach for stability investigation and control design of single-phase phase-locked loops (PLLs). The aim is to identify the system instabilities not predicted using the existent analysis and design methods based on the simplified average model approach. Design/methodology/approach – This paper starts by investigating the performance of three commonly used PLL schemes: the inverse park-PLL, the second-order generalised integrators (SOGI)-frequency-locked loop and the enhanced-PLL, designed using the simplifi

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25

Abdul-Niby, M., M. Alameen, and H. Baitie. "A Simple Phase Shifting Technique for an Injection Locked Oscillator." Engineering, Technology & Applied Science Research 6, no. 6 (2016): 1303–6. http://dx.doi.org/10.48084/etasr.881.

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In Self Oscillating systems, locking of the oscillators can take place for injected signals close in frequency to nth harmonics of the free-running frequency. In this paper, we present a simple design for digital phase shift control by using a harmonically injection locked oscillator (ILO) of 35MHz frequency. Phase shifters at high frequencies are essential in many communication system applications such as frequency synthesis, quadrature signal generation and phase locked loops (PLLs).

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26

Toihria, Intissar, Rim Ayadi, and Mohamed Masmoudi. "Design of an Effective Charge Pump-Phase Locked Loops Architecture for RF Applications." International Journal of Computer Applications 74, no. 3 (2013): 38–44. http://dx.doi.org/10.5120/12867-9740.

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27

Sadr, R., B. Shah, and S. Hinedi. "Design of wideband all-digital phase locked loops using multirate digital filter banks." IEEE Transactions on Communications 44, no. 6 (1996): 663–67. http://dx.doi.org/10.1109/26.506382.

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28

Zhai, Bingcong. "Understanding of the Coherent Demodulation with Phase-Locked Loop." MATEC Web of Conferences 176 (2018): 01028. http://dx.doi.org/10.1051/matecconf/201817601028.

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The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way. Therefore, more and more attentions have been paid to the research and application of all digital phase-locked loops. This paper serves as an introduction about the basic background of PLL, the basic characteristics and structure of PLL, and the basic principles of modulation and demodulation. It provides a concise application about the basic principle and

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29

Cai, Zhi Kuang, Kai Huang, Jun Yang, and Long Xing Shi. "Built-In Self-Test Scheme for All-Digital Phase-Locked Loops." Advanced Materials Research 546-547 (July 2012): 922–27. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.922.

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This paper presents a low-cost Built-In Self-Test (BIST) scheme, which is based on the principle of parity check code. The proposed circuit is consisted of a XOR network, a frequency decrease module, a BIST controller and a fault detector module. Different from the previous methods of PLL BIST, digital signals from the divide-by-N are grouped as transmission codes, and parity check codes are produced synchronously by the BIST controller. Then the results of parity checking are imported to the fault detector and final test results are generated. Purely digital design flow is adopted and hybrid

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30

Burgos-Mellado, Claudio, Alessandro Costabeber, Mark Sumner, Roberto Cárdenas-Dobson, and Doris Sáez. "Small-Signal Modelling and Stability Assessment of Phase-Locked Loops in Weak Grids." Energies 12, no. 7 (2019): 1227. http://dx.doi.org/10.3390/en12071227.

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This paper proposes a low-complexity small signal model for a 3-leg converter connected to a balanced three-phase, three-wire weak grid and synchronised to this grid using a PLL implemented in a synchronous rotating d-q axis. A thorough analysis of the system stability as a function of the PLL bandwidth and the short circuit ratio (SCR) of the grid is performed based on a linearised model. By using the proposed model, an improved design process is proposed for the commonly used dq-PLL that accounts for the potential stability issues which may occur in weak grids. Using the proposed approach, i

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31

Shah, Shahil, Przemyslaw Koralewicz, Vahan Gevorgian, and Leila Parsa. "Small-Signal Modeling and Design of Phase-Locked Loops Using Harmonic Signal-Flow Graphs." IEEE Transactions on Energy Conversion 35, no. 2 (2020): 600–610. http://dx.doi.org/10.1109/tec.2019.2954112.

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32

Zhichao, Gong, Lu Lei, Liao Youchun, and Tang Zhangwen. "Design and noise analysis of a fully-differential charge pump for phase-locked loops." Journal of Semiconductors 30, no. 10 (2009): 105013. http://dx.doi.org/10.1088/1674-4926/30/10/105013.

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33

Roncagliolo, Pedro A., Javier G. García, and Carlos H. Muravchik. "Optimized Carrier Tracking Loop Design for Real-Time High-Dynamics GNSS Receivers." International Journal of Navigation and Observation 2012 (June 3, 2012): 1–18. http://dx.doi.org/10.1155/2012/651039.

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Carrier phase estimation in real-time Global Navigation Satellite System (GNSS) receivers is usually performed by tracking loops due to their very low computational complexity. We show that a careful design of these loops allows them to operate properly in high-dynamics environments, that is, accelerations up to 40 g or more. Their phase and frequency discriminators and loop filter are derived considering the digital nature of the loop inputs. Based on these ideas, we propose a new loop structure named Unambiguous Frequency-Aided Phase-Locked Loop (UFA-PLL). In terms of tracking capacity and n

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34

Dong Dong, Bo Wen, Paolo Mattavelli, Dushan Boroyevich, and Yaosuo Xue. "Modeling and Design of Islanding Detection Using Phase-Locked Loops in Three-Phase Grid-Interface Power Converters." IEEE Journal of Emerging and Selected Topics in Power Electronics 2, no. 4 (2014): 1032–40. http://dx.doi.org/10.1109/jestpe.2014.2345783.

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35

Zhao, Jun, and Yong-Bin Kim. "A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops." VLSI Design 2010 (January 19, 2010): 1–11. http://dx.doi.org/10.1155/2010/946710.

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A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL) designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO_output and DCO_clock is measured. A carefully designed reset proces

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36

Ince, Mehmet, Ender Yilmaz, Wei Fu, et al. "Fault-based Built-in Self-test and Evaluation of Phase Locked Loops." ACM Transactions on Design Automation of Electronic Systems 26, no. 3 (2021): 1–18. http://dx.doi.org/10.1145/3427911.

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With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, there

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37

Zhao, Yi-Bo, Chi-Kong Tse, Jiu-Chao Feng, and Ye-Cai Guo. "Application of Memristor-Based Controller for Loop Filter Design in Charge-Pump Phase-Locked Loops." Circuits, Systems, and Signal Processing 32, no. 3 (2012): 1013–23. http://dx.doi.org/10.1007/s00034-012-9521-z.

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38

Bernard, Florent, Viktor Fischer, and Boyan Valtchanov. "Mathematical model of physical RNGs based on coherent sampling." Tatra Mountains Mathematical Publications 45, no. 1 (2010): 1–14. http://dx.doi.org/10.2478/v10127-010-0001-1.

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ABSTRACT Random number generators represent one of basic cryptographic primitives used in creating cryptographic protocols. Their security evaluation represents very important part in the design, implementation and employment phase of the generator. One of important security requirements is the existence of a mathematical model describing the physical noise source and the statistical properties of the digitized noise derived from it. The aim of this paper is to propose the model of a class of generators using two jittery clocks with rationally related frequencies. The clock signals with relate

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39

Razavi, B., K. F. Lee, and R. H. Yan. "Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS." IEEE Journal of Solid-State Circuits 30, no. 2 (1995): 101–9. http://dx.doi.org/10.1109/4.341736.

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40

Raphaeli, Dan, and Oded Yaniv. "Design of low update rate phase locked loops with application to carrier tracking in OFDM systems." Journal of Communications and Networks 7, no. 3 (2005): 248–57. http://dx.doi.org/10.1109/jcn.2005.6389809.

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41

Kazovsky, L. "Balanced phase-locked loops for optical homodyne receivers: Performance analysis, design considerations, and laser linewidth requirements." Journal of Lightwave Technology 4, no. 2 (1986): 182–95. http://dx.doi.org/10.1109/jlt.1986.1074698.

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42

Wang, Chua-Chin, Yu-Tsun Chien, and Ying-Pei Chen. "A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop." VLSI Design 11, no. 2 (2000): 107–13. http://dx.doi.org/10.1155/2000/52658.

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In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL) limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The paper presents a targeted 5.0V 500 MHz PLL which is implemented by a 0.6 um 1P3M digital CMOS technology. The features of the proposed design include a load-optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, thus, is reduced to 72.693 ps at 600 MHz at the presence of suppl

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43

Ahmad, Nur Syazreen. "Robust stability analysis and improved design of phase-locked loops with non-monotonic nonlinearities: LMI-based approach." International Journal of Circuit Theory and Applications 45, no. 12 (2017): 2057–72. http://dx.doi.org/10.1002/cta.2371.

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44

Tahir, Muhammad, Letizia Lo Presti, and Maurizio Fantino. "A Novel Quasi-Open Loop Architecture for GNSS Carrier Recovery Systems." International Journal of Navigation and Observation 2012 (June 3, 2012): 1–12. http://dx.doi.org/10.1155/2012/324858.

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The problem of designing robust systems to track global navigation satellite system (GNSS) signals in harsh environments has gained high attention. The classical closed loop architectures, such as phase locked loops, have been used for many years for tracking, but in challenging applications their design procedure becomes intricate. This paper proposes and demonstrates the use of a quasi-open loop architecture to estimate the time varying carrier frequency of GNSS signals. Simulation results show that this scheme provides an additional degree of freedom to the design of the whole architecture.

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45

PATEL, GOVIND S., and S. SHARMA. "PREDICTING THE JITTER OF PLL–DLL BASED FREQUENCY SYNTHESIZERS." International Journal of Wavelets, Multiresolution and Information Processing 12, no. 02 (2014): 1450016. http://dx.doi.org/10.1142/s0219691314500167.

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Phase Lock Loop (PLL) and Delay Locked Loops (DLLs) are major analog circuits used for many different communication applications such as frequency synthesizer, radio, computer, clock generation and recovery, global positioning system etc. This paper developed a methodical approach to calculate jitter of the PLL and DLL. The methodological nature of our approach would manifest itself in the development of a clear step-by-step procedure for the design of the constituent components of the same. Finally, jitter of DLL has been reduced by proposed technique.

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46

Wang, Yao Chen, Hui Wei He, Dong Chen Yan, and Jin Hui Xiong. "Design of Induction Heating Power Based on the Power Adjusting Technique and the Frequency Tracing." Advanced Materials Research 846-847 (November 2013): 13–17. http://dx.doi.org/10.4028/www.scientific.net/amr.846-847.13.

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The ultrahigh frequency (more than 1MHz) of the HF Induction Heater need to be reached for surface-heat-processing of tiny mental components, which is not available by the traditional HF Induction Heater. To satisfy these requirements, by using the high-speed field effective transistor (FET) and high-speed phase locked loops (PLL: MM74HC4046), the frequency of inverts for induction heater and the power can arrive at more than 1MHz and 5.5kW respectively at the same time. Additionally, it achieves the power adjusting technique and the frequency tracing. The experimental shows that this design c

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47

Loveless, T. Daniel, Lloyd W. Massengill, Bharat L. Bhuva, et al. "A Probabilistic Analysis Technique Applied to a Radiation-Hardened-by-Design Voltage-Controlled Oscillator for Mixed-Signal Phase-Locked Loops." IEEE Transactions on Nuclear Science 55, no. 6 (2008): 3447–55. http://dx.doi.org/10.1109/tns.2008.2005677.

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48

Li, Xing, and Hua Lin. "A Design Method of Phase-Locked Loop for Grid-Connected Converters Considering the Influence of Current Loops in Weak Grid." IEEE Journal of Emerging and Selected Topics in Power Electronics 8, no. 3 (2020): 2420–29. http://dx.doi.org/10.1109/jestpe.2019.2916002.

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Bakar, Siti Juliana Abu, Nur Syazreen Ahmad, and Patrick Goh. "Improved structured filter design and analysis for perturbed phase-locked loops via sector and H∞ norm constraints with convex computations." Computers & Electrical Engineering 81 (January 2020): 106542. http://dx.doi.org/10.1016/j.compeleceng.2019.106542.

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Park, Sungkyung, and Chester Sungchung Park. "Quantization Noise Analysis of Time-to-Digital-Converter-Based All-Digital Phase-Locked Loop and Frequency Discriminators." Journal of Circuits, Systems and Computers 25, no. 11 (2016): 1650131. http://dx.doi.org/10.1142/s0218126616501310.

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Abstract:

All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is

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