Academic literature on the topic 'Phase-locked loops. Digital electronics. Electronic noise'
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Journal articles on the topic "Phase-locked loops. Digital electronics. Electronic noise"
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CHAU, YAWGENG A., and CHEN-FENG CHEN. "ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS." Journal of Circuits, Systems and Computers 20, no. 06 (October 2011): 1037–49. http://dx.doi.org/10.1142/s0218126611007748.
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The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. An example is given to illustrate the design procedure and simulation results are presented to validate the adaptive characteristics with respect to the phase noise and varying bands of input frequency.
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Magerramov, R. V. "Method of frequency-phase detection used in ADC based on PLL circuit." Issues of radio electronics, no. 8 (August 7, 2019): 26–30. http://dx.doi.org/10.21778/2218-5453-2019-8-26-30.
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The phase‑locked loop (PLL) is an integral part of many electronic products in modern electronics and radio engineering, which is used to form and process analog and digital signals. One of the non‑standard applications of the PLL circuit is to implement an analog voltage‑to‑pulse converter. This application of the PLL circuit allows you to create an analog‑to‑digital converter (ADC) with high resolution, and the implementation features of the PLL circuit can provide a number of advantages, such as high noise immunity, compensation for the errors of passive elements, operation in a wide temperature range, etc. The accuracy of the conversion in such a device depends on both the separately designed blocks of the PLL circuit and the parameters of the system as a whole. The paper discusses the implementation of a digital frequency‑phase detector (FFD) operating in the range from 0 to 2p. The basis of his work is the method of frequency‑phase detection, which reduces the time of transients in the PLL circuit, and also eliminates the detection of coherent and multiple frequencies of the reference signal.
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Wang, Chua-Chin, Yu-Tsun Chien, and Ying-Pei Chen. "A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop." VLSI Design 11, no. 2 (January 1, 2000): 107–13. http://dx.doi.org/10.1155/2000/52658.
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In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL) limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The paper presents a targeted 5.0V 500 MHz PLL which is implemented by a 0.6 um 1P3M digital CMOS technology. The features of the proposed design include a load-optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, thus, is reduced to 72.693 ps at 600 MHz at the presence of supply noise, while the sensitivity is limited to 286.6 ps/V. This high-noise immunity design allows that the PLL can be integrated with digital circuits.
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Ince, Mehmet, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, Leroy Winemberg, and Sule Ozev. "Fault-based Built-in Self-test and Evaluation of Phase Locked Loops." ACM Transactions on Design Automation of Electronic Systems 26, no. 3 (February 2021): 1–18. http://dx.doi.org/10.1145/3427911.
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With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.
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Balikai, Vikas, and Harish Kittur. "A CMOS implementation of controller based all digital phase locked loop (ADPLL)." Circuit World 47, no. 1 (May 6, 2020): 71–85. http://dx.doi.org/10.1108/cw-11-2019-0184.
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Purpose Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose of this paper is to the design of controller-based all-digital phase-locked loop (ADPLL) in a 45 nm CMOS process. Design/methodology/approach Initially, an open-loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved. Findings The designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of −98.36 at 1-MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 µW. Research limitations/implications A time to digital converter (TDC)-less controller-based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 µW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of −98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC. Social implications The designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society. Originality/value The implementation of open-loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power.
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Cortés, Iñigo, Johannes Rossouw van der Merwe, Jari Nurmi, Alexander Rügamer, and Wolfgang Felber. "Evaluation of Adaptive Loop-Bandwidth Tracking Techniques in GNSS Receivers." Sensors 21, no. 2 (January 12, 2021): 502. http://dx.doi.org/10.3390/s21020502.
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Global navigation satellite system (GNSS) receivers use tracking loops to lock onto GNSS signals. Fixed loop settings limit the tracking performance against noise, receiver dynamics, and the current scenario. Adaptive tracking loops adjust these settings to achieve optimal performance for a given scenario. This paper evaluates the performance and complexity of state-of-the-art adaptive scalar tracking techniques used in modern digital GNSS receivers. Ideally, a tracking channel should be adjusted to both noisy and dynamic environments for optimal performance, defined by tracking precision and loop robustness. The difference between the average tracking jitter of the discriminator’s output and the square-root Cramér-Rao bound (CRB) indicates the loops’ tracking capability. The ability to maintain lock characterizes the robustness in highly dynamic scenarios. From a system perspective, the average lock indicator is chosen as a metric to measure the performance in terms of precision, whereas the average number of visible satellites being tracked indicates the system’s robustness against dynamics. The average of these metrics’ product at different noise levels leads to a reliable system performance metric. Adaptive tracking techniques, such as the fast adaptive bandwidth (FAB), the fuzzy logic (FL), and the loop-bandwidth control algorithm (LBCA), facilitate a trade-off for optimal performance. These adaptive tracking techniques are implemented in an open software interface GNSS hardware receiver. All three methods steer a third-order adaptive phase locked loop (PLL) and are tested in simulated scenarios emulating static and high-dynamic vehicular conditions. The measured tracking performance, system performance, and time complexity of each algorithm present a detailed analysis of the adaptive techniques. The results show that the LBCA with a piece-wise linear approximation is above the other adaptive loop-bandwidth tracking techniques while preserving the best performance and lowest time complexity. This technique achieves superior static and dynamic system performance being 1.5 times more complex than the traditional tracking loop.
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Ximenes, Augusto, Preethi Padmanabhan, and Edoardo Charbon. "Mutually Coupled Time-to-Digital Converters (TDCs) for Direct Time-of-Flight (dTOF) Image Sensors." Sensors 18, no. 10 (October 11, 2018): 3413. http://dx.doi.org/10.3390/s18103413.
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Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamless references, area and power consumption limit the use of more traditional synthesizers, such as phase/delay-locked loops (PLLs/DLLs). Other methods, such as relative timing measurement (start/stop), require constant foreground calibration, which is not feasible for outdoor applications, where conditions of temperature, background illumination, etc. can change drastically and frequently. In this paper, a scalable reference generation and synchronization is provided, using minimum resources of area and power, while being robust to mismatches. The suitability of this approach is demonstrated through the design of an 8 × 8 time-to-digital converter (TDC) array, distributed over 1.69 mm2, fabricated using TSMC 65 nm technology (1.2 V core voltage and 4 metal layers—3 thin + 1 thick). Each TDC is based on a ring oscillator (RO) coupled to a ripple counter, occupying a very small area of 550 μ m2, while consuming 500 μ W of power, and has 2 μ s range, 125 ps least significant bit (LSB), and 14-bit resolution. Phase and frequency locking among the ROs is achieved, while providing 18 dB phase noise improvement over an equivalent individual oscillator. The integrated root mean square (RMS) jitter is less than 9 ps, the instantaneous frequency variation is less than 0.11%, differential nonlinearity (DNL) is less than 2 LSB, and integral nonlinearity (INL) is less than 3 LSB.
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Magerramov, R. V. "APPLICATION OF THE PLL CONTROL AT THE REALIZATION OF A 16-THROUGH ADC." Issues of radio electronics, no. 8 (August 20, 2018): 6–12. http://dx.doi.org/10.21778/2218-5453-2018-8-6-12.
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This article describes the method of converting an analog signal into a digital code using a phase locked loop (PLL) circuit. The functional structure of the voltage-to-digital conversion circuit is considered. The application of the principle of phase-locked loop for controlling the duty cycle of the output signal of a phase detector when the voltage at the positive input of the operational amplifier included in the low-pass filter is investigated. In the modern world, analog-to-digital converters (ADCs) are available in almost every electronic device. The application of different ADC architectures is determined by their parameters and features by circuit and technological implementation. The phase-locked loop with a digital part (16-bit counter, storage register and data transfer interface) allows to obtain a precision analog-to-digital converter, based on a relatively simple circuit design, which has high accuracy and low noise level. Negative feedback of the PLL loop makes it possible to level the error of the passive elements of the low-pass filter (LPF) and the voltage controlled oscillator (VCO). The result of this work is an analysis of the ADC characteristics in the technological basis of 250 nm.
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Jang, Taekwang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, and David Blaauw. "A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector." IEEE Journal of Solid-State Circuits 53, no. 1 (January 2018): 50–65. http://dx.doi.org/10.1109/jssc.2017.2776313.
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Syrjälä, Ville, and Mikko Valkama. "Analysis and mitigation of phase noise and sampling jitter in OFDM radio receivers." International Journal of Microwave and Wireless Technologies 2, no. 2 (April 2010): 193–202. http://dx.doi.org/10.1017/s1759078710000309.
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This article addresses the analysis and digital signal processing (DSP)-based mitigation of phase noise and sampling clock jitter in orthogonal frequency division multiplexing (OFDM) radios. In the phase noise studies, the basic direct-conversion receiver architecture case is assumed with noisy downconverting oscillator. In the sampling jitter case, on the other hand, the so-called direct-radio-frequency-sampling receiver architecture is deployed utilizing bandpass sub-sampling principle. The basis for the DSP-based impairment mitigation techniques is first formed using analytical receiver modeling with incoming OFDM waveform, where the effects of both oscillator phase noise and sampling clock jitter are mapped to certain type subcarrier cross-talk and distortion compared to ideal receiver case. Then iterative detection principles and interpolation techniques are developed to essentially estimate and cancel the subcarrier distortion. Also some related practical aspects, like channel estimation, are addressed. The performance of the proposed mitigation techniques is analyzed and verified with extensive computer simulations. In the simulations, realistic phase-locked-loop-based oscillator models are used for phase noise and sampling clock jitter. In addition, different received signal conditions like plain additive white Gaussian noise channel and extended ITU-R Vehicular A multipath channel are considered for practical purposes. Altogether the obtained results indicate that the effects of oscillator and sampling clock instabilities can be efficiently reduced using the developed signal processing techniques.
Dissertations / Theses on the topic "Phase-locked loops. Digital electronics. Electronic noise"
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Jiang, Bo. "A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration." ScholarWorks @ UVM, 2016. http://scholarworks.uvm.edu/graddis/562.
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The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the phase lock loop (PLL) frequency synthesizer. In order to access various standards, the frequency synthesizer needs to have wide frequency tuning range, fast tuning speed, and low phase noise and frequency spur. The traditional analog charge pump frequency synthesizer circuit design is becoming diffcult due to the continuous down-scalings of transistor feature size and power supply voltage. The goal of this project was to develop an all digital phase locked loop (ADPLL) as the alternative solution technique in RF transceivers by taking advantage of digital circuitry's characteristic features of good scalability, robustness against process variation and high noise margin. The targeted frequency bands for our ADPLL design included 880MHz-960MHz, 1.92GHz-2.17GHz, 2.3GHz-2.7GHz, 3.3GHz-3.8GHz and 5.15GHz-5.85GHz that are used by wireless communication standards such as GSM, UMTS, bluetooth, WiMAX and Wi-Fi etc.
This project started with the system level model development for characterizing ADPLL phase noise, fractional spur and locking speed. Then an on-chip jitter detector and parameter adapter was designed for ADPLL to perform self-tuning and self-calibration to accomplish high frequency purity and fast frequency locking in each frequency band. A novel wide band DCO is presented for multi-band wireless application. The proposed wide band adaptive ADPLL was implemented in the IBM 0.13µm CMOS technology. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was assessed and agrees well with the theoretical analysis.
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Ok, Kerem. "A stochastic time-to-digital converter for digital phase-locked loops." Thesis, 2005. http://hdl.handle.net/1957/482.
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Graduation date: 2006Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter (STDC) for a digital PLL to attain high resolution. The converter is intended to comprise the fine loop of the phase-frequency detector, whose coarse loop would be comprised of a time-to-digital converter designed using the conventional delay-chain approach. The STDC is designed, simulated and sent for fabrication in a 0.35μm SOI CMOS process. System level simulations in MATLAB are verified by device level simulations in Spectre on circuits extracted from layout. The results support the viability of using the proposed circuit for high resolution time-to-digital conversion.
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Elshazly, Amr. "Performance enhancement techniques for low power digital phase locked loops." Thesis, 2012. http://hdl.handle.net/1957/31116.
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Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions.
In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques.Graduation date: 2013
Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014
Books on the topic "Phase-locked loops. Digital electronics. Electronic noise"
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1959-, Harjani Ramesh, ed. Design of high performance CMOS voltage-controlled oscillators. Boston: Kluwer Academic Publishers, 2003.
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Dai, Liang, and Ramesh Harjani. Design of Higher-Performance CMOS Voltage Controlled Oscillators (The Springer International Series in Engineering and Computer Science). Springer, 2002.
Find full textConference papers on the topic "Phase-locked loops. Digital electronics. Electronic noise"
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Meier, Jonas, Fabian Maul, Markus Scholl, Christoph Beverstedt, Ralf Wunderlich, and Stefan Heinen. "Simulating Phase Noise in Multi-Gigahertz High Precision All-Digital Phase-Locked Loops." In 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2020. http://dx.doi.org/10.1109/icecs49266.2020.9294980.
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Gallacher, Barry J., Zhongxu Hu, Kiran Mysore Harish, Stephen Bowles, and Harry Grigg. "The Application of Parametric Excitation in MEMS Gyroscopes." In ASME 2013 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/detc2013-12029.
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Parametric excitation, via electrostatic stiffness modulation, can be exploited in resonant MEMS gyroscopes. In the case of the Rate gyroscope, which is by far the most common type of MEMS gyro, parametric excitation may be used to amplify either the primary mode of the gyro or the response to the angular rate. Both approaches will be discussed. In the more complex mode of operation, known as “Rate Integrating” the output of the gyro is angle directly as opposed to angular velocity in the case of Rate gyro. In this rate integrating mode of operation parametric excitation does offer an effective energy control used to initiate, sustain the vibration and minimise damping perturbations. Parametric amplification of the primary mode of the rate gyroscope is presented and supported with experimental results. In this implementation parametric excitation is combined with external harmonic forcing of the primary mode in order to reduce electrical feedthrough of the driving signal to the sense electrodes. A practical parametric excitation scheme implemented using Digital Signal Processing has been developed to enable either amplification of the primary mode of the gyroscope or amplification of the response to the applied angular velocity. Parametric amplification of the primary mode of the gyroscope is achieved by frequency tracking and regulation of the amplitudes of the harmonic forcing and parametric excitation to maintain a desired parametric gain by closed loop PID control. Stable parametric amplification of the primary mode by a factor of 20 is demonstrated experimentally. This has important benefits regarding the minimisation of electrical feedthrough of the drive signal to the sense electrodes of the secondary mode. By taking advantage of the phase dependence of parametric amplification and the orthogonality of the Coriolis force and quadrature forcing, the response to the applied angular velocity may be parametrically amplified by applying excitation of a particular phase directly to the sensing mode. The major advantage of parametric amplification applied to MEMs gyroscopes is that it can mechanically amplify the Coriolis response before being picked off electrically. This is particularly advantageous for sensors where electronic noise is the major noise contributor. In this case parametric amplification can significantly improve the signal to noise ratio of the secondary mode by an amount approximately equal to the parametric amplification. Preliminary rate table tests performed in open loop demonstrate a magnification of the signal to noise ratio of the secondary mode by a factor of 9.5.