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CHAU, YAWGENG A., and CHEN-FENG CHEN. "ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS." Journal of Circuits, Systems and Computers 20, no. 06 (October 2011): 1037–49. http://dx.doi.org/10.1142/s0218126611007748.
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The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. An example is given to illustrate the design procedure and simulation results are presented to validate the adaptive characteristics with respect to the phase noise and varying bands of input frequency.
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Magerramov, R. V. "Method of frequency-phase detection used in ADC based on PLL circuit." Issues of radio electronics, no. 8 (August 7, 2019): 26–30. http://dx.doi.org/10.21778/2218-5453-2019-8-26-30.
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The phase‑locked loop (PLL) is an integral part of many electronic products in modern electronics and radio engineering, which is used to form and process analog and digital signals. One of the non‑standard applications of the PLL circuit is to implement an analog voltage‑to‑pulse converter. This application of the PLL circuit allows you to create an analog‑to‑digital converter (ADC) with high resolution, and the implementation features of the PLL circuit can provide a number of advantages, such as high noise immunity, compensation for the errors of passive elements, operation in a wide temperature range, etc. The accuracy of the conversion in such a device depends on both the separately designed blocks of the PLL circuit and the parameters of the system as a whole. The paper discusses the implementation of a digital frequency‑phase detector (FFD) operating in the range from 0 to 2p. The basis of his work is the method of frequency‑phase detection, which reduces the time of transients in the PLL circuit, and also eliminates the detection of coherent and multiple frequencies of the reference signal.
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Wang, Chua-Chin, Yu-Tsun Chien, and Ying-Pei Chen. "A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop." VLSI Design 11, no. 2 (January 1, 2000): 107–13. http://dx.doi.org/10.1155/2000/52658.
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In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL) limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The paper presents a targeted 5.0V 500 MHz PLL which is implemented by a 0.6 um 1P3M digital CMOS technology. The features of the proposed design include a load-optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, thus, is reduced to 72.693 ps at 600 MHz at the presence of supply noise, while the sensitivity is limited to 286.6 ps/V. This high-noise immunity design allows that the PLL can be integrated with digital circuits.
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Ince, Mehmet, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, Leroy Winemberg, and Sule Ozev. "Fault-based Built-in Self-test and Evaluation of Phase Locked Loops." ACM Transactions on Design Automation of Electronic Systems 26, no. 3 (February 2021): 1–18. http://dx.doi.org/10.1145/3427911.
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With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.
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Balikai, Vikas, and Harish Kittur. "A CMOS implementation of controller based all digital phase locked loop (ADPLL)." Circuit World 47, no. 1 (May 6, 2020): 71–85. http://dx.doi.org/10.1108/cw-11-2019-0184.
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Purpose Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose of this paper is to the design of controller-based all-digital phase-locked loop (ADPLL) in a 45 nm CMOS process. Design/methodology/approach Initially, an open-loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved. Findings The designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of −98.36 at 1-MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 µW. Research limitations/implications A time to digital converter (TDC)-less controller-based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 µW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of −98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC. Social implications The designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society. Originality/value The implementation of open-loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power.
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Cortés, Iñigo, Johannes Rossouw van der Merwe, Jari Nurmi, Alexander Rügamer, and Wolfgang Felber. "Evaluation of Adaptive Loop-Bandwidth Tracking Techniques in GNSS Receivers." Sensors 21, no. 2 (January 12, 2021): 502. http://dx.doi.org/10.3390/s21020502.
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Global navigation satellite system (GNSS) receivers use tracking loops to lock onto GNSS signals. Fixed loop settings limit the tracking performance against noise, receiver dynamics, and the current scenario. Adaptive tracking loops adjust these settings to achieve optimal performance for a given scenario. This paper evaluates the performance and complexity of state-of-the-art adaptive scalar tracking techniques used in modern digital GNSS receivers. Ideally, a tracking channel should be adjusted to both noisy and dynamic environments for optimal performance, defined by tracking precision and loop robustness. The difference between the average tracking jitter of the discriminator’s output and the square-root Cramér-Rao bound (CRB) indicates the loops’ tracking capability. The ability to maintain lock characterizes the robustness in highly dynamic scenarios. From a system perspective, the average lock indicator is chosen as a metric to measure the performance in terms of precision, whereas the average number of visible satellites being tracked indicates the system’s robustness against dynamics. The average of these metrics’ product at different noise levels leads to a reliable system performance metric. Adaptive tracking techniques, such as the fast adaptive bandwidth (FAB), the fuzzy logic (FL), and the loop-bandwidth control algorithm (LBCA), facilitate a trade-off for optimal performance. These adaptive tracking techniques are implemented in an open software interface GNSS hardware receiver. All three methods steer a third-order adaptive phase locked loop (PLL) and are tested in simulated scenarios emulating static and high-dynamic vehicular conditions. The measured tracking performance, system performance, and time complexity of each algorithm present a detailed analysis of the adaptive techniques. The results show that the LBCA with a piece-wise linear approximation is above the other adaptive loop-bandwidth tracking techniques while preserving the best performance and lowest time complexity. This technique achieves superior static and dynamic system performance being 1.5 times more complex than the traditional tracking loop.
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Ximenes, Augusto, Preethi Padmanabhan, and Edoardo Charbon. "Mutually Coupled Time-to-Digital Converters (TDCs) for Direct Time-of-Flight (dTOF) Image Sensors." Sensors 18, no. 10 (October 11, 2018): 3413. http://dx.doi.org/10.3390/s18103413.
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Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamless references, area and power consumption limit the use of more traditional synthesizers, such as phase/delay-locked loops (PLLs/DLLs). Other methods, such as relative timing measurement (start/stop), require constant foreground calibration, which is not feasible for outdoor applications, where conditions of temperature, background illumination, etc. can change drastically and frequently. In this paper, a scalable reference generation and synchronization is provided, using minimum resources of area and power, while being robust to mismatches. The suitability of this approach is demonstrated through the design of an 8 × 8 time-to-digital converter (TDC) array, distributed over 1.69 mm2, fabricated using TSMC 65 nm technology (1.2 V core voltage and 4 metal layers—3 thin + 1 thick). Each TDC is based on a ring oscillator (RO) coupled to a ripple counter, occupying a very small area of 550 μ m2, while consuming 500 μ W of power, and has 2 μ s range, 125 ps least significant bit (LSB), and 14-bit resolution. Phase and frequency locking among the ROs is achieved, while providing 18 dB phase noise improvement over an equivalent individual oscillator. The integrated root mean square (RMS) jitter is less than 9 ps, the instantaneous frequency variation is less than 0.11%, differential nonlinearity (DNL) is less than 2 LSB, and integral nonlinearity (INL) is less than 3 LSB.
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Magerramov, R. V. "APPLICATION OF THE PLL CONTROL AT THE REALIZATION OF A 16-THROUGH ADC." Issues of radio electronics, no. 8 (August 20, 2018): 6–12. http://dx.doi.org/10.21778/2218-5453-2018-8-6-12.
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This article describes the method of converting an analog signal into a digital code using a phase locked loop (PLL) circuit. The functional structure of the voltage-to-digital conversion circuit is considered. The application of the principle of phase-locked loop for controlling the duty cycle of the output signal of a phase detector when the voltage at the positive input of the operational amplifier included in the low-pass filter is investigated. In the modern world, analog-to-digital converters (ADCs) are available in almost every electronic device. The application of different ADC architectures is determined by their parameters and features by circuit and technological implementation. The phase-locked loop with a digital part (16-bit counter, storage register and data transfer interface) allows to obtain a precision analog-to-digital converter, based on a relatively simple circuit design, which has high accuracy and low noise level. Negative feedback of the PLL loop makes it possible to level the error of the passive elements of the low-pass filter (LPF) and the voltage controlled oscillator (VCO). The result of this work is an analysis of the ADC characteristics in the technological basis of 250 nm.
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Jang, Taekwang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, and David Blaauw. "A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector." IEEE Journal of Solid-State Circuits 53, no. 1 (January 2018): 50–65. http://dx.doi.org/10.1109/jssc.2017.2776313.
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Syrjälä, Ville, and Mikko Valkama. "Analysis and mitigation of phase noise and sampling jitter in OFDM radio receivers." International Journal of Microwave and Wireless Technologies 2, no. 2 (April 2010): 193–202. http://dx.doi.org/10.1017/s1759078710000309.
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This article addresses the analysis and digital signal processing (DSP)-based mitigation of phase noise and sampling clock jitter in orthogonal frequency division multiplexing (OFDM) radios. In the phase noise studies, the basic direct-conversion receiver architecture case is assumed with noisy downconverting oscillator. In the sampling jitter case, on the other hand, the so-called direct-radio-frequency-sampling receiver architecture is deployed utilizing bandpass sub-sampling principle. The basis for the DSP-based impairment mitigation techniques is first formed using analytical receiver modeling with incoming OFDM waveform, where the effects of both oscillator phase noise and sampling clock jitter are mapped to certain type subcarrier cross-talk and distortion compared to ideal receiver case. Then iterative detection principles and interpolation techniques are developed to essentially estimate and cancel the subcarrier distortion. Also some related practical aspects, like channel estimation, are addressed. The performance of the proposed mitigation techniques is analyzed and verified with extensive computer simulations. In the simulations, realistic phase-locked-loop-based oscillator models are used for phase noise and sampling clock jitter. In addition, different received signal conditions like plain additive white Gaussian noise channel and extended ITU-R Vehicular A multipath channel are considered for practical purposes. Altogether the obtained results indicate that the effects of oscillator and sampling clock instabilities can be efficiently reduced using the developed signal processing techniques.
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Colodro, F., and A. Torralba. "Frequency-to-digital conversion based on sampled phase-locked loop with third-order noise shaping." Electronics Letters 47, no. 19 (2011): 1069. http://dx.doi.org/10.1049/el.2011.1524.
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WALL, RICHARD W., and HERBERT L. HESS. "DESIGN AND MICROCONTROLLER IMPLEMENTATION OF A THREE PHASE SCR POWER CONVERTER." Journal of Circuits, Systems and Computers 06, no. 06 (December 1996): 619–33. http://dx.doi.org/10.1142/s0218126696000431.
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A single processor controls a three phase silicon controlled rectifier (SCR) power converter. An inexpensive, dual optoisolator interface to the power line provides noise rejection and an improved measure of the zero crossing. A dynamic digital phase-locked loop (PLL) algorithm implemented in an Intel 87C196KD-20 processor achieves frequency tracking, dynamically changing characteristics for improved performance. Dynamically modifying the PLL characteristics permits independent capture and locked dynamics. A feedforward method provides command tracking for improved response without loss of performance. This three-component design (processor, optoisolator, and SCR gate drivers) represents a minimal implementation with potential for closed loop voltage and current control. High speed input and output resources included on the 87C196KD processor make an efficient single-device implementation possible. The processor is less than 1% utilized allowing for additional functions to be added in the future. This system operates on both 50 Hz and 60 Hz power systems without modification or loss of performance.
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Lee, Minjae, Mohammad E. Heidari, and Asad A. Abidi. "A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution." IEEE Journal of Solid-State Circuits 44, no. 10 (October 2009): 2808–16. http://dx.doi.org/10.1109/jssc.2009.2028753.
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Jiao, Hongchen, Lishuang Feng, Qingjun Zhang, Jie Liu, Tao Wang, Ning Liu, Chunqi Zhang, Xindong Cui, and Xiaoning Ji. "Realization of Hollow-Core Photonic-Crystal Fiber Optic Gyro Based on Low-Noise Multi-Frequency Lasers with Intermediate-Frequency Difference." Sensors 20, no. 10 (May 16, 2020): 2835. http://dx.doi.org/10.3390/s20102835.
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Mainly focusing on the demand for a novel resonator optic gyro based on a hollow-core photonic-crystal fiber (HC-RFOG), we achieve a multi-frequency lasers generation with low relative phase noise via an acousto-optic modulation of light from a single laser diode. We design a homologous heterodyne digital optical phase-locked loop (HHD-OPLL), based on which we realize the low-noise multi-frequency lasers (LNMFLs) with an intermediate frequency difference. The noise between the lasers with a 20 MHz difference is 0.036 Hz, within the bandwidth of 10 Hz, in a tuning range of 120 kHz, approximately 40 dB lower than that produced without the HHD-OPLL. Finally, based on the LNMFLs, an HC-RFOG is realized and a bias stability of 5.8 °/h is successfully demonstrated.
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Sahani, Jagdeep Kaur, Anil Singh, and Alpana Agarwal. "A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology." Journal of Circuits, Systems and Computers 29, no. 08 (October 14, 2019): 2050130. http://dx.doi.org/10.1142/s0218126620501303.
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A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.
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Salarpour, Mahdi, Forouhar Farzaneh, and Robert Bogdan Staszewski. "Synchronization-Phase Alignment of All-Digital Phase-Locked Loop Chips for a 60-GHz MIMO Transmitter and Evaluation of Phase Noise Effects." IEEE Transactions on Microwave Theory and Techniques 67, no. 7 (July 2019): 3187–99. http://dx.doi.org/10.1109/tmtt.2019.2910060.
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PAP, L. "LOW FREQUENCY FALSE-LOCK PHENOMENON IN SAMPLED COSTAS-LOOPS." Journal of Circuits, Systems and Computers 02, no. 04 (December 1992): 359–82. http://dx.doi.org/10.1142/s0218126692000222.
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The effect of the low frequency false-lock phenomenon has been considered in sampled decision feedback Costas-loops used in BPSK direct sequence spread spectrum (DS SS) systems. This new physical phenomenon can occur in each arm-filtered nonlinear sampled PLL applying digital signal processing algorithms for phase detector implementations. This contribution provides details of calculation of false-locking phase detector characteristics of the sampled Costas-loops without and with hard-limited in-phase channel (the latter system will be referred to as sampled decision feedback loop) and analyzes different methods of filterless subharmonic false-lock detection. Besides in the case of white Gaussian noisy environment the phase detector characteristics at the false-lock frequencies, and the false alarm and false detection probabilities of the filterless subharmonic false-lock detectors are derived based on the new circuit models. The theoretical results have been checked by experimental implementations.
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Wang, Yihang, Qiang Fu, Yufeng Zhang, Wenbo Zhang, Dongliang Chen, Liang Yin, and Xiaowei Liu. "A Digital Closed-Loop Sense MEMS Disk Resonator Gyroscope Circuit Design Based on Integrated Analog Front-end." Sensors 20, no. 3 (January 27, 2020): 687. http://dx.doi.org/10.3390/s20030687.
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A digital closed-loop system design of a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) is proposed in this paper. Vibration models with non-ideal factors are provided based on the structure characteristics and operation mode of the sensing element. The DRG operates in force balance mode with four control loops. A closed self-excited loop realizes stable vibration amplitude on the basis of peak detection technology and phase control loop. Force-to-rebalance technology is employed for the closed sense loop. A high-frequency carrier loaded on an anchor weakens the effect of parasitic capacitances coupling. The signal detected by the charge amplifier is demodulated and converted into a digital output for subsequent processing. Considering compatibility with digital circuits and output precision demands, a low passband sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented with a 111.8dB signal-to-noise ratio (SNR). The analog front-end and digital closed self-excited loop is manufactured with a standard 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology. The experimental results show a bias instability of 2.1 °/h and a nonlinearity of 0.035% over the ± 400° full-scale range.
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Gianni, Pablo, Laura Ferster, Graciela Corral-Briones, and Mario R. Hueda. "Efficient Parallel Carrier Recovery for Ultrahigh Speed Coherent QAM Receivers with Application to Optical Channels." Journal of Electrical and Computer Engineering 2013 (2013): 1–14. http://dx.doi.org/10.1155/2013/240814.
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This work presents a new efficient parallel carrier recovery architecture suitable for ultrahigh speed intradyne coherent optical receivers (e.g., ≥100 Gb/s) with quadrature amplitude modulation (QAM). The proposed scheme combines a novel low-latency parallel digital phase locked loop (DPLL) with a feedforward carrier phase recovery (CPR) algorithm. The new low-latency parallel DPLL is designed to compensate not only carrier frequency offset but also frequency fluctuations such as those induced by mechanical vibrations or power supply noise. Such carrier frequency fluctuations must be compensated since they lead to higher phase error variance in traditional feedforward CPR techniques, significantly degrading the receiver performance. In order to enable a parallel-processing implementation in multigigabit per second receivers, a new approximation to the DPLL computation is introduced. The proposed technique reduces the latency within the feedback loop of the DPLL introduced by parallel processing, while at the same time it provides a bandwidth and capture range close to those achieved by a serial DPLL. Simulation results demonstrate that the effects caused by frequency deviations can be eliminated with the proposed low latency parallel carrier recovery architecture.
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Sahani, Jagdeep Kaur, Anil Singh, and Alpana Agarwal. "A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology." Journal of Circuits, Systems and Computers 29, no. 09 (November 26, 2019): 2050142. http://dx.doi.org/10.1142/s021812662050142x.
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This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-[Formula: see text][Formula: see text]m CMOS technology with supply voltage of 1.8[Formula: see text]V. The output clocks with cycle-to-cycle jitter of 2.13[Formula: see text]ps at 1.6[Formula: see text]GHz. The phase noise of VCO is [Formula: see text]137[Formula: see text]dBc/Hz at an offset of 100[Formula: see text]MHz and total power consumed by the proposed PLL is 2.63[Formula: see text]mW at 1.6[Formula: see text]GHz.
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Kim, Sung Jin, Dong Gyu Kim, Seong Jin Oh, Dong Soo Lee, Young Gun Pu, Keum Cheol Hwang, Youngoo Yang, and Kang Yoon Lee. "A Fully Integrated Bluetooth Low-Energy Transceiver with Integrated Single Pole Double Throw and Power Management Unit for IoT Sensors." Sensors 19, no. 10 (May 27, 2019): 2420. http://dx.doi.org/10.3390/s19102420.
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This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.
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Yan, Chenggang, Jianhui Wu, Jie Sun, Jin Jin, and Chen Hu. "A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 3 (March 2020): 455–59. http://dx.doi.org/10.1109/tcsii.2019.2913023.
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Agarwal, Neeraj, Neeru Agarwal, Chih-Wen Lu, and Masahito Oh-e. "A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application." Electronics 10, no. 14 (July 20, 2021): 1743. http://dx.doi.org/10.3390/electronics10141743.
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This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range.
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Selvajyothi, K., and P. A. Janakiraman. "FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters." VLSI Design 2010 (January 24, 2010): 1–14. http://dx.doi.org/10.1155/2010/512312.
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This paper presents a single chip FPGA (Altera Cyclone II) controlled single phase inverter, programmed for the reduction of harmonics in the output voltage. Separate composite digital observers have been designed for extracting the fundamental and harmonic components of the voltage and the highly distorted current signals, particularly when the inverter supplies nonlinear loads. These observers have been embedded into the FPGA along with the controllers and I/O interfaces. The multiple observers yield very pure in-phase and quadrature voltage signals for use in the outer loop and similar signals for stabilizing the inner current loop. The Inverter could be modeled as a feed back control system with the fundamental component of the voltage as the desired output while the voltage harmonics take the role of noise creeping into the output. To obtain a very low total harmonic distortion in the voltage waveform, the well-known control strategy of using a very large feed back around the noise signal has been employed.
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Huang, Geng, Zhang, Chen, Cai, Wang, Zhu, and Wang. "A Wide-Band Digital Lock-In Amplifier and Its Application in Microfluidic Impedance Measurement." Sensors 19, no. 16 (August 11, 2019): 3519. http://dx.doi.org/10.3390/s19163519.
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In this work, we report on the design of a wide-band digital lock-in amplifier (DLIA) of up to 65 MHz and its application for electrical impedance measurements in microfluidic devices. The DLIA is comprised of several dedicated technologies. First, it features a fully differential analog circuit, which includes a preamplifier with a low input noise of 4.4 nV/√Hz, a programmable-gain amplifier with a gain of 52 dB, and an anti-aliasing, fully differential low-pass filter with −76 dB stop-band attenuation. Second, the DLIA has an all-digital phase lock loop, which features a phase deviation of less than 0.02° throughout the frequency range. The phase lock loop utilizes an equally accurate period-frequency measurement, with a sub-ppm precision of frequency detection. Third, a modified clock link is implemented in the DLIA to improve the signal-to-noise ratio of the analog-to-digital converter affected by clock jitter of up to 20 dBc. A series of measurements were performed to characterize the DLIA, and the results showed an accurate performance. Additionally, impedance measurements of standard-size microparticles were performed by frequency sweep from 300 kHz to 30 MHz, using the DLIA in a microfluidic device. Different diameters of microparticle could be accurately distinguished according to the relative impedance at 2.5 MHz. The results confirm the promising applications of the DLIA in microfluidic electrical impedance measurements.
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Ruppert, Michael G., David M. Harcombe, Michael R. P. Ragazzon, S. O. Reza Moheimani, and Andrew J. Fleming. "A review of demodulation techniques for amplitude-modulation atomic force microscopy." Beilstein Journal of Nanotechnology 8 (July 10, 2017): 1407–26. http://dx.doi.org/10.3762/bjnano.8.142.
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In this review paper, traditional and novel demodulation methods applicable to amplitude-modulation atomic force microscopy are implemented on a widely used digital processing system. As a crucial bandwidth-limiting component in the z-axis feedback loop of an atomic force microscope, the purpose of the demodulator is to obtain estimates of amplitude and phase of the cantilever deflection signal in the presence of sensor noise or additional distinct frequency components. Specifically for modern multifrequency techniques, where higher harmonic and/or higher eigenmode contributions are present in the oscillation signal, the fidelity of the estimates obtained from some demodulation techniques is not guaranteed. To enable a rigorous comparison, the performance metrics tracking bandwidth, implementation complexity and sensitivity to other frequency components are experimentally evaluated for each method. Finally, the significance of an adequate demodulator bandwidth is highlighted during high-speed tapping-mode atomic force microscopy experiments in constant-height mode.
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Tang, Taiwen, Chen Wu, and Janaka Elangage. "A Signal Processing Algorithm of Two-Phase Staggered PRI and Slow Time Signal Integration for MTI Triangular FMCW Multi-Target Tracking Radars." Sensors 21, no. 7 (March 25, 2021): 2296. http://dx.doi.org/10.3390/s21072296.
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In this paper, a novel signal processing algorithm for mitigating the radar blind speed problem of moving target indication (MTI) for frequency modulated continuous wave (FMCW) multi-target tracking radars is proposed. A two-phase staggered pulse repetition interval (PRI) solution is introduced to the FMCW radar system. It is implemented as a time-varying MTI filter using twice the hardware resources as compared to a uniform PRI MTI filter. The two-phase staggered PRI FMCW waveform is still periodic with a little more than twice the period of the uniform PRI radar. We also propose a slow time signal integration scheme for the radar detector using the post-fast Fourier transformation Doppler tracking loop. This scheme introduces 4.77 dB of extra signal processing gain to the signal before the radar detector compared with the original uniform PRI FMCW radar. The validation of the algorithm is done on the field programmable logic array in the loop test bed, which accurately models and emulates the target movement, line of sight propagation and radar signal processing. A simulation run of tracking 16 s of the target movement near or at the radar blind speed shows that the total degradation from the raw post-fast Fourier transformation received signal to noise ratio is about 2 dB. With a 20 dB post-processing signal to noise ratio of the proposed algorithm for the moving target at around a 20 km range and with about a −3.5 dB m2 radar cross section at a 1.5 GHz carrier frequency, the tracking errors of the two-dimensional angles with a 4×4 digital phased array are less than 0.2 degree. The range tracking error is about 28 m.
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Soni, Umesh Kumar, and Ramesh Kumar Tripathi. "High Load Fast Startup Sensorless Control of Wheel BLDC Motor with Line-to-Line Back EMF Extraction Using Least Pth-Norm IIR Digital Filter." Journal of Circuits, Systems and Computers 29, no. 09 (November 19, 2019): 2050145. http://dx.doi.org/10.1142/s0218126620501455.
Full textAbstract:
In this paper, an effective scheme of on-load startup with reduced current has been proposed for BLDC motor and the steady as well as dynamic performance in all four quadrants was verified. Hysteresis band-limited back EMF noise provides the starting pulses, the frequency of which depends on the threshold factor in speed proportional threshold. Scheme is quite fast, comparatively to the state-of-the art schemes of startup and less complex than time-consuming initial position detection (IPD) algorithm. Second-order least [Formula: see text]th-norm infinite impulse response (IIR) digital low pass filter realized in MATLAB/Simulink has been used for extraction of line-to line back EMF from line-to-line terminal voltages measured with two voltage sensors. Proposed filter has wide flexibility of online variation of cut-off frequency, gain and phase without any circuit-based modification due to variability of filter coefficients. This enables the smooth filtering with minimized phase delay in low speed range irrespective of any duty cycle and PWM frequency. Linear compensation of phase error or phase advancement for desired current profile can easily be achieved by the varying the threshold factor. In this experiment, the threshold factor of 1/1460 has been found most suitable for smooth sensorless startup without jerk, vibration and reverse rotation, as the motor operates in advanced mode with this value. First, the performance of Hall sensor-based drive was studied using open loop variable duty cycle speed control. The controller was designed in MATLAB/Simulink platform and implemented using TMS320F28069M DSP control stick with Code composer Studio V5. Later on, a complete controller for proposed sensorless scheme was developed in MATLAB/Simulink environment and was implemented using NI-PCI6221 Controller installed in PC. The proposed sensorless drive has been found capable of operating at very low speed of 50[Formula: see text]rpm in voltage control mode and 85[Formula: see text]rpm in current chopping PWM mode. Approximately 85[Formula: see text]ms less time was taken by sensorless drive to reach the same speed when compared with Hall-based control for identical loading. Also less overshoots during startup was observed. Overlap time of 0.05[Formula: see text]ms between phase currents has been achieved during commutation period.
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Balikai, Vikas, and Harish Kittur. "Capacitive Boosted Ring Oscillators for All-Digital Phase-Locked Loops (ADPLLs)." Journal of Circuits, Systems and Computers, June 2, 2021, 2150273. http://dx.doi.org/10.1142/s021812662150273x.
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Ring oscillator (RO)-based digital phase-locked loops (DPLLs) are very attractive for system-on-chip applications due to their tuning range, good phase noise property but suffer from compactness and power requirements. In this work, the concept of capacitive boosting as one of the key solutions which enhances the amplitude of oscillations of the RO is proposed, making it a suitable solution to the biomedical applications, specifically for medical implant communication system (MICS) band of operation ranging from 400[Formula: see text]MHz to 405[Formula: see text]MHz. With coarse and fine-tuning blocks, this digitally controlled oscillator (DCO) promises a good resolution. The coarse tuning is achieved using conventional MOS capacitors and the fine-tuning is achieved by controlling the fractional metal oxide semiconductor (MOS) capacitances. To benchmark the performance metrics of the single-stage RO in this work, simulations were performed for 680[Formula: see text]mV supply voltage in 45[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The output varies in the range from [Formula: see text]0.422[Formula: see text]V to [Formula: see text][Formula: see text]V, indicating about 224% amplitude enhancement. Despite process voltage temperature (PVT) variations, we can see little impact on the boosted output levels. The designed DCO operates up to a maximum frequency of 495[Formula: see text]MHz at 0.68[Formula: see text]V. The proposed RO has lesser power consumption than any conventional RO, operating at a center frequency of 402[Formula: see text]MHz, thus making it better suitable for the MICS band of applications. Phase noise of [Formula: see text][Formula: see text]dBc/Hz at an offset of 200[Formula: see text]kHz was obtained. The proposed differential DCO consumed power was 95.26[Formula: see text][Formula: see text]W. The figure of merit (FoM) for this DCO is [Formula: see text] (dBc/Hz). The area consumed by the DCO is 0.01872[Formula: see text]mm2.
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"Phase Locking in Millimeter Wave Frequency Synthesizers - Design overview of Charge Pump Phase Locked Loops." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 19 (May 22, 2020). http://dx.doi.org/10.37394/23201.2020.19.15.
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Phase Locked Loops are key blocks which are widely adopted in all area of electronics, especially transceivers in wireless communication systems. The application of Phase Locked Loop varies from generation of local oscillator signal for upconversion and down conversion, generation and distribution of clock signals and jitter reduction. The most extensive use of Phase Locked Loop is for frequency synthesis. The requirements of synthesizer architectures depend on various system requirements and specifications which are based on regulatory standards. The design of Phase Locked Loop components involves the consideration of various techniques to resolve the nonidealities at front end high frequency components as well as back end low frequency components. This paper presents the background and importance of a Phase Locked Loop, various approaches over the years, design choices for each block and practical design methodology for Charge Pump Phase Locked Loops. This paper also presents the system level design of Phase Locked Loop and supply noise interactions among sub modules inside a charge pump Phase Locked Loop
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КОЗЛОВ, В. И. "FREQUENCY SYNTHESIS WITH DIGITAL-TO-ANALOG COMPENSATION OF FRACTIONAL NOISE IN THE PLL SYSTEM." Электросвязь, no. 6(7) (July 6, 2020). http://dx.doi.org/10.34832/elsv.2020.7.6.007.
Full textAbstract:
Идея цифроаналоговой компенсации помех дробности состоит в том, что и компенсирующий, и управляющий частотой генератора в петле фазовой автоподстройки частоты (ФАПЧ) сигналы формируются одновременно и совместно в цифровом виде и лишь на последнем этапе трансформируются в аналоговый сигнал, чем достигается высокая спектральная чистота сигнала, зависящая исключительно от точности ЦАП. Приведен расчет спектра сигнала. Проведено сравнение с существующими широко применяемыми DDS и Fractional-N PLL синтезаторами. The idea of digital-to-analog fractional noise cancellation is to construct a phase detector circuit in such a way that the compensating and main frequency control phase-locked loop (PLL) signals are both generated together and simultaneously in digital form and only at the last stage are transformed into an analog signal. Calculation of the signal spectrum is given. Comparison is made with the existing widely used DDS and Fractional-N PLL synthesizers.
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Xu, Daiguo, Han Yang, Xing Sheng, Ting Sun, Guangbing Chen, Shiliu Xu, Can Zhu, Jianan Wang, and Dongbin Fu. "A Noise Reduction 12-bit 125-MSPS SAR ADC with Modified Asynchronous Logic Regulation Technique." Journal of Circuits, Systems and Computers, August 8, 2020, 2150040. http://dx.doi.org/10.1142/s0218126621500407.
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This paper presents noise reduction and modified asynchronous logic regulation techniques used in successive approximation register (SAR) analog-to-digital converter (ADC). With a transconductance enhanced structure, noise reduction is provided in the dynamic comparator. The input referred noise of the proposed comparator is about 165[Formula: see text][Formula: see text]V rms at 60∘C (typical corner). An enhanced-positive-feedback loop is introduced to reduce the regeneration delay of the comparator. In addition, a modified asynchronous logic regulation technique is exhibited, a clock with adaptable delay is driving the comparator in approximation phase. Consequently, the settling accuracy of DAC (Digital-to-Analog Converter) is enough and the conversion speed of SAR ADC is increased without any redundant cycles. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 4[Formula: see text]mW from 1.2[Formula: see text]V power supply with a [Formula: see text][Formula: see text]dB and [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.048[Formula: see text]mm2, and the corresponding FoM is 27.2[Formula: see text]fJ/conversion-step at Nyquist rate.