Dissertations / Theses on the topic 'Photonic Design Automation Tools'

The demand for customised products that meet different markets and different customers is steadily increasing. Also, the demand for shorter lead times for the delivery of these customised products puts strains on design departments whose work tends to become increasingly repetitive. At the same time, designing variants takes time from innovative, original design, and/or problem-solving tasks. A powerful tool in the endeavour to cut lead times, workloads, and ultimately costs in order to become more competitive in an increasingly globalised market is Design Automation. Automating tedious and repetitive design tasks will free the designers to focus on the tasks that require skill, creativity, intuition, and cooperation to be solved. Consequently, seeing a need for design automation systems is not difficult. What becomes a lot more difficult is identifying the type, scope, and format of the system implementation, as well as the actual design tasks and activities to support or automate. Therefore, there is a need for structured and systematic approaches for the realisation and implementation of design automation systems. This research work is aimed at presenting such approaches, methods, and aids. It also addresses the importance of identifying the exact tasks to be automated. This has to be done in order to find the method and implementations best suited for solving the tasks, something that is especially important for companies whose human and financial resources might not allow them to invest in a system with functionality that vastly exceeds their actual needs. The contribution of this work is a structured method for planning for design automation implementation. First, the design process is discussed from an automation perspective. Following this is a presentation of a framework of design automation. This framework has the purpose of serving as a common base for consensual discussions about design automation. In addition, it supports the setting-up of system specifications. The framework is followed by the introduction of a set of identifiers of system needs and potentials, focusing on the existing processes that need to be broken down and identified in order to specify the tasks to be automated. Following this is a set of criteria of system characteristics, focusing on properties of the intended system implementation. Finally, some realisation and implementation issues are addressed and exemplified through a number of pilot system implementations. The presented method for planning design automation, together with the presented framework of design automation, provides implementers with issues to address regarding potential, need, scope, and format of system implementations. Further, it supports the weighing of desired system characteristics in order to find the right balance between system complexity and functionality.

Photonic networks form the backbone of the data communication infrastructure. In particular, in current and future wireless communication systems, photonic networks are becoming increasingly popular for data distribution between the central office and the remote antenna units at base stations. As wireless-photonic systems become increasingly more popular, not only low-cost implementation of such systems is desirable, but also a reliable electronic-photonic design automation (EPDA) framework supporting such complex circuits and systems is crucial. This work investigates the foundation and presents implementation of various aspects of such EPDA framework. Various building blocks of silicon-photonic systems are reviewed in the first chapter of the thesis. The review discusses an example of a 60-GHz wireless system based on photonic technology, which could be suitable for the emerging 5th-generation (5G) cellular networks, and also provides design use cases that need to be supported by the EPDA framework. Integrated photonic circuits, which are the building blocks of wireless-photonic systems, will achieve their potential only if designers can efficiently and reliably design, model, simulate, and tune the performance of electro-optical components. The developed EPDA framework supports an integrated optical solver, INTERCONNECT, to provide optical time and frequency domain simulations so that a designer would be able to simulate electrical, optical, and electro-optical circuits using two developed and implemented methodologies: sequential electro-optical simulation and co-simulation. We propose an algorithm to enhance the performance of electronic simulation engines that can be integrated into the EPDA simulation methods such as Harmonic Balance. It will be shown that body-biasing of CMOS transistors can be used as an effective method for tuning the performance of the electronic section of an electro-optical design. This can help designers adjusting the performance of their designs after fabrication. Modelling of electro-optical components is discussed in this thesis; It is shown that some traditional passive components such as inductors, which take a large amount of space in CMOS processes, could be fabricated in the much lower cost photonic process and consequently the overall cost of silicon-photonic systems can be reduced significantly.<br>Applied Science, Faculty of<br>Electrical and Computer Engineering, Department of<br>Graduate

La electrónica orgánica/impresa está continuamente creciendo en interés, con la aparición de nuevas propuestas y aplicaciones. Este tipo de tecnologías no pretenden competir directamente con las que provienen de la industria tradicional basada en Silicio, sino que tienen como propósito complementarla con nuevos dispositivos que proporcionen ciertas ventajas en determinadas situaciones, ya sea en términos de coste u otras. Sin embargo, en lo que se refiere al campo del procesado digital queda mucho trabajo por hacer para, paulatinamente, ir siguiendo los pasos del modelo ‘fabless’ que rige el mercado de semiconductores actual. Este modelo consiste en la deslocalización entre los equipos de diseño y los fabricantes. Respecto a dicho progreso me refiero no solo a las mejoras que acontecen a nivel de procesos de fabricación, sino también en el campo de la automatización de los procesos de diseño. Nuestro grupo de investigación concibió una novedosa estrategia para producir, de manera eficiente, diseños de circuitos digitales para electrónica impresa, basados en lo que denominamos Inkjet-configurable Gate Arrays, aprovechando las ventajas de la impresión digital. Estos Inkjet Gate Arrays consisten en matrices de transistores sobre sustratos flexibles que, una vez conectados mediante impresión digital, conforman puertas lógicas; las cuales, en su conjunto, materializan circuitos. El trabajo presentado en esta tesis se centra en una etapa específica de cualquier flujo de diseño común de circuitos integrados, llamada síntesis física. En concreto, este trabajo proporciona una novedosa metodología para resolver el problema de ubicar y conectar, ‘Placement and Routing’, los circuitos sobre las mencionadas matrices de transistores, teniendo en cuenta su rendimiento, y con independencia de la tecnología de fabricación. Se aborda la manera de cómo tratar con tecnologías impresas diferentes, que puedan presentar distintos niveles de rendimiento, normalmente debidos a la alta variabilidad intrínseca a los procesos de fabricación actuales. En tales casos, un factor clave para asegurar que la colocación de los circuitos sea funcionalmente correcta es poder procesar de manera efectiva la información sobre la distribución de fallos de las matrices. Además del concepto de mapeo según el rendimiento, la novedosa heurística aquí propuesta proporciona la capacidad de personalizar los circuitos, lo que permite mayor flexibilidad en su construcción, dependiendo de distintas razones u objetivos posibles (p. ej. congestión). Esta metodología no solo es conveniente para los primeros pasos que, en la actualidad, se están llevando a cabo en el desarrollo de prototipos de circuitos digitales para la electrónica orgánica, sino que también es escalable hacia nuevas mejoras en el rendimiento de las tecnologías de fabricación, así como en tamaños y densidad de integración.<br>Organic/Printed Electronics are, day by day, increasing on interest, as new applications are being proposed and developed. This kind of technologies do not intend to compete directly with the Silicon-based well-established industry, but rather to complement it with new devices that are advantageous for certain situations, whether in terms of cost or others. However, in the digital processing domain there is still much work to be done to, slowly but steadily, follow the steps of the conventional fabless model that rules today’s semiconductor market. I am referring not only to progresses at fabrication level, but also on the field of Electronic Design Automation. Our research group conceived a novel strategy to efficiently produce Printed Electronics digital circuit designs based on what we called Inkjet-configurable Gate Arrays, which takes advantage of digital printing techniques. The Inkjet Gate Arrays consist in matrices of transistors over flexible substrates that, after being connected by digital printing techniques, they describe logic gates, and thus circuits. The work presented in this dissertation targets a specific stage of any common Integrated Circuit design flow, referred to as physical synthesis. Specifically, my contribution provides a new approach to the Placement and Routing problem, where circuits are mapped onto the Inkjet Gate Arrays in a technology independent yield-aware manner. I tackle the issue of dealing with different Printed Electronics technologies that might present distinct yield properties, usually due to the intrinsic high variability of current fabrication processes. In such cases, being able to effectively process the IGA’s fault distribution information is key to ensure that the mapped circuits will be capable of working correctly, from a functional perspective. In addition to the yield awareness concept, the circuit personalization capabilities of the novel P&R heuristic proposed herein allow more mapping flexibility, depending on different possible reasons/purposes (e.g. congestion). This approach is not only convenient for today’s first steps of digital circuit prototyping over Organic Electronics, but also scalable to future technological improvements at yield level, and on sizes and integration density.

Product development is continually becoming more challenging as global competition requires more efficient design methods. The reuse of company knowledge, specifically the design rationale that occurs during projects is essential to success. This thesis presents a method for integrating engineering and communication tools for purposes of automating the capture of communication-based design rationale. The method is based on four basic principles: to integrate, to make data retrievable, to minimize user interaction, and to store as much DR as possible. The core method consists of two primary operations, the first being to capture the design rationale, and the second being to provide for effective retrieval. An implementation of this method that uses NX as the engineering tool and Skype VoIP software as the communication tool was created for the purpose of testing integration as a means of DR capture. The implementation was evaluated using four separate tests, which focus on efficiency of capture and retrieval, cost analysis, and user satisfaction. These results show that the tool provides improvement in each of the tested categories. From this testing I conclude that integrating communication and engineering tools is an excellent way to capture communication-based design rationale. The tool presented is more efficient than traditional methods in the test cases and provides a user-friendly solution to DR capture. This tool also has various other important applications, such as global collaboration and expectation management. It also provides an excellent framework for upcoming multi-user CAx tools.

This research studies the three market-leading RPA-tools, Automation Anywhere, Blue Prism and UiPath, in order to fill the lack of literature regarding methods for evaluating and comparing RPA-tools. Design science research was performed by designing and creating artefacts in the form of process implementations and an evaluative model. A typical process representing a common area of use was implemented using each of the three RPA-tools, in order to create an evaluative model. Official documentation, along with the three implementations, were studied. Evaluative questions specific to RPA-tool evaluation were created based on a quality model for product quality found in the ISO/IEC 25010 standard. Characteristics dependant on organisational context were not included in the evaluation, in order to create an evaluative model which is not dependant on any specific business environment. The results of the research provide knowledge of (1) how RPA-tools can be implemented and (2) the differences that exist between the three market-leading RPA tools. The research also contributes in the form of a method for investigating and evaluating the RPA-tools. When creating the evaluative model, some of the criteria found in the ISO/IEC 25010 quality model were concluded to be of low relevance and, therefore, not included in the model. By analysing and evaluating the created evaluative model, using a theoretical concept of digital resources and their evaluation, the validity of the evaluative model was reinforced. From an evaluative perspective, this research emphasises the need to appropriate and change existing evaluative methods in order to successfully evaluate the most relevant characteristics of RPA-tools.<br>Denna forskning studerar de tre marknadsledande RPA-verktygen, Automation Anywhere, Blue Prism och UiPath, för att fylla bristen på litteratur om metoder för utvärdering och jämförelse av RPA-verktyg. Design science research genomfördes genom att utforma och skapa artefakter i form av processimplementeringar och en utvärderingsmodell. En typisk process som representerar ett vanligt användningsområde implementerades med användning av vart och ett av de tre RPA-verktygen för att skapa en utvärderingsmodell. Officiell dokumentation, tillsammans med de tre implementeringarna, studerades. Utvärder-ingsfrågor specifika för RPA-verktygsutvärdering skapades baserat på en kvalitetsmodell för produktkvalitet som finns i ISO/IEC 25010-standarden. Egenskaper som är beroende av organisatoriskt sammanhang ingick inte i utvärderingen för att skapa en utvärderingsmodell som inte är beroende av någon specifik affärsmiljö. Resultaten av forskningen ger kunskap om (1) hur RPA-verktyg kan implementeras och (2) skillnaderna som finns mellan de tre marknadsledande RPA-verktygen. Forskningen bidrar också i form av en metod för att undersöka och utvärdera RPA-verktygen. Vid skapandet av utvärderingsmodellen drogs slutsatsen att några av kriterierna i kvalitetsmodellen i ISO/IEC 25010 var av låg relevans och de är därför inte inkluderade i den resulterande modellen. Genom att analysera och utvärdera den skapade utvärderingsmodellen, med hjälp av ett teoretiskt koncept av digitala resurser och deras utvärdering, förstärktes utvärderingsmodellens validitet. Ur ett utvärderingsperspektiv betonar denna forskning behovet av att anpassa och ändra befintliga utvärderingsmetoder för att framgångsrikt utvärdera de mest relevanta egenskaperna hos RPA-verktyg.

In this thesis, will be presented BioCAD, a novel computational tool able to design optimal and robust biological circuits. In BioCAD, the main idea is to use Pareto optimality and the Electronic Design Automation methods for Systems and Synthetic Biology. However, BioCAD is a general purpose tool and can be seen as well as a black box able to receive in input a generic model and analyze its components and submodules, estimate its parameters, or optimize specific functions. BioCAD implements novel and state-of-the-art algorithms performing: (i) Optimization, by analyzing continuous, discrete or hybrid (continuous and discrete) variable spaces, for Single- and Multi-objective optimization problems and for local or global search; (ii) Sensitivity Analysis, for evaluating the importance of the parameters by ranking them according to their influence on the model; (iii) Robustness Analysis, for estimating the global and local fragility and robustness of optimal synthetic circuits; (iv) Identifiability Analysis, that finds functional relations among parameters, by analyzing the values of the decision variables after and before the optimization. Additionally, BioCAD implements the epsilon-dominance analysis, able to relax the Pareto condition and expand the solution space to neighborhood region of the Pareto surface. Optimization core contains novel tools for engineering enzymes, genes and fluxes in biological systems, while Sensitivity Analysis can reveal the main genes, enzymes, species or pathways. BioCAD can be adopted and used with various modeling techniques: flux balance analysis with or without the gene protein reaction mappings, ordinary differential equations, differential algebraic equations and partial differential equations. In this thesis will be reported several experiments applied on Synthetic Biology, such as the design of the novel 1,4-butanediol synthetic pathway.

Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain. Development of a cell library is laborious, prone to errors and even a small error on a library cell can possibly be disastrous due to repeated use of the cell in a design. In this thesis, we investigated ways to automate the process for development of a cell library, specifically TSMC 0.18-micron CMOS standard cell library. We examined various steps in the design flow to identify required repetitive tasks for individual cells. Those steps include physical verification, netlist extraction, cell characterization, and generation of Synopsys Liberty Format file. We developed necessary scripts in Skill, Tcl, Perl and Shell to automate those steps. Additionally, we developed scripts to automate the quality assurance process of the cell library, where quality assurance consists of verifying the entire ASIC design flow adopted for the Virginia Tech VLSI Telecommunications (VTVT) lab. Our scripts have been successfully used to develop our TSMC 0.18-micron library and to verify the quality assurance. The first version of the cell library was released on November 1, 2007 to universities worldwide, and as of March 2008, 20 universities have received the library from us.<br>Master of Science

Durant els últims anys, les tecnologies d’electrònica impresa (PE) estan atraient molta atenció, principalment degut a que es poden fabricar grans àrees, i són una alternativa de baix cost a la microelectrònica tradicional. D’entre totes les tecnologies disponibles, la fabricació emprant impresores d’injecció de tinta (inkjet) resulta particularment interessant, al ser un mètode d’impressió digital (reduint els residus generats al fabricar), i no tenir contacte amb el substrat (per tant permet la utilització de molts tipus diferents de substrats). La tecnologia inkjet encara està patint un gran desenvolupament, cosa que fa difícil que es puguin dissenyar circuits i sistemes sense tenir un gran coneixement sobre els processos que hi ha al darrere. A més a més, la mancança d’eines específicament dissenyades per a inkjet crea un gran distància entre els dissenyadors i els tecnòlecs responsables de desenvolupar la tecnologia, dificultant així una adopció generalitzada de la tecnologia inkjet. Aquesta tèsi contribueix a apropar els dissenyadors a la tecnologia, proposant i adaptant fluxes i kits de disseny existents i basats en microelectrònica, a les tecnologies inkjet, complementant-los amb eines específiques per adaptar-los a les peculiaritats de l’inkjet. D’aquesta manera aconseguim un camí directe des del disseny a la fabricació, abstraient els detalls tecnològics del disseny. A més a més, per tancar el camí entre disseny i la fabricació, aquesta tèsi proposa un entorn semi-automàtic de caracterització, que es fa servir per analitzar el comportament de la tinta dipositada, inferint quines correccions són necessàries per a què el resultat fabricat correspongui tant com sigui possible al disseny. El coneixement extret d’aquest pas s’incorporarà en una eina EDA específica que analitza i aplica automàticament les correccions extretes a un disseny.<br>During last years, Printed Electronics technologies have attracted a great deal of attention due to being a low-cost, large area electronics manufacturing process. From all available technologies, inkjet printing is of special interest, because of its digital nature, which reduces material waste; and being a non-contact process, which allows printing on a great variety of substrates. Inkjet printing is still on heavy development, thus making designing for it difficult without an in-depth knowledge of how the manufacturing process works. In addition, currently there is a lack of specific tools aiding to design for it, creating a large gap between designers and technology developers and difficulting a wide adoption of this particular technologies. The work presented on this thesis contributes to bridge the existing gap between designers and technology developers by proposing and adapting existing microelectronics-based design flows and kits, while complementing them with custom, PE specific Electronic Design Automation tools; to achieve a direct path from design to manufacturing, and abstract technology specific details from the design stages. This is achieved by combining a design flow with a PE Process/Physical Design Kit, and a set of EDA tools adapted to PE. In addition, to finally bridge design and manufacturing, this thesis proposes a semi-automated characterization methodology, used to analyze the deposited ink behavior, and infer all necessary corrections needed to ensure that the final fabricated result corresponds as much as possible to the intended design. This knowledge is then integrated into an specific EDA framework which will perform the aformentioned corrections automatically.

Lab exercises are a pedagogically essential component of engineering and technology education. Distance education remote labs are being developed which enable students to access lab facilities via the Internet. Collaboration, students working in teams, enhances learning activity through the development of communication skills, sharing observations and problem solving. Web meeting communication tools are currently used in remote labs. The problem identified for investigation was that no standards of practice or paradigms exist to guide remote lab designers in the selection of collaboration tools that best support learning achievement. The goal of this work was to add to the body of knowledge involving the selection and use of remote lab collaboration tools. Experimental research was conducted where the participants were randomly assigned to three communication treatments and learning achievement was measured via assessments at the completion of each of six remote lab based lessons. Quantitative instruments used for assessing learning achievement were implemented, along with a survey to correlate user preference with collaboration treatments. A total of 53 undergraduate technology students worked in two-person teams, where each team was assigned one of the treatments, namely (a) text messaging chat, (b) voice chat, or (c) webcam video with voice chat. Each had little experience with the subject matter involving automation, but possessed the necessary technical background. Analysis of the assessment score data included mean and standard deviation, confirmation of the homogeneity of variance, a one-way ANOVA test and post hoc comparisons. The quantitative and qualitative data indicated that text messaging chat negatively impacted learning achievement and that text messaging chat was not preferred. The data also suggested that the subjects were equally divided on preference to voice chat verses webcam video with voice chat. To the end of designing collaborative communication tools for remote labs involving automation equipment, the results of this work points to making voice chat the default method of communication; but the webcam video with voice chat option should be included. Standards are only beginning to be developed for the design of remote lab systems. Research, design and innovation involving collaboration and presence should be included.

In future high-performance computing systems, congruent multiples in GOPS/W are expected more from the improvement of system integration levels (such as 3D stacking or 2.5D integration) rather than from the scaling of device dimensions. The expected outcome will be large chip-scale multiprocessors that will pose unprecedented bandwidth requirements for intra and inter-die communications. In this context, system performance needs to be sustained by a scalable on-chip communication infrastructure capable of delivering large bandwidth capacities and stringent latency requirements in a power efficient fashion. By capitalizing on the latest advances of silicon photonics, optical networks-on-chip (ONoCs) stand out as a promising solution to overcome the interconnect limitations and enable the continued scaling of many-core architectures. With respect to traditional electronic NoCs, they preserve the chip-scale networking paradigm while changing the technology substrate. However, ONoCs currently suffer from a huge gap between device developers and system designers which prevents their "system ability", that is the capability to do system level design with them. A research investment on design automation and on system-level integration methods is the only way to bridge the abstraction gap and enable system designers to work out efficient solutions for the connectivity problem at hand. For this purpose, the thesis aims at improving the "system ability" of a specific family of ONoCs that holds promise of all-optical, predictable and low-latency communications, namely wavelength-routed ONoCs (WRONoCs). In this context, the thesis aims at addressing two correlated aspects of this abstraction gap: 1)On the one hand, the thesis will pursue cross-layer synthesis methodologies to enable the design space exploration and the specification of abstract solutions for the connectivity problem at hand, as well as their refinement into an actual physical structure. This represents a milestone contribution to shed light on a design space which is currently limited to the few topology design points that researchers' intuition was able to unveil. The enabling approach is to bring design automation beyond its electronic roots. 2)On the other hand, the thesis will investigate how to compose silicon nanophotonic networks with the other system-level components. This integration issue is typically overlooked in literature, since it is oversimplified as a stage of E/O and O/E conversion circuits. This thesis demonstrates that the interface of such networks to the electronic part of the system is much more complex than that, and implies a new multi-technology architecture building block that we call "the bridge", with major impact upon the network power budget and performance. In practice, an energy-efficient, low-latency and flexible bridge is designed to connect an ONoC with the baseline electronic NoC in a 3D-stacked parallel computing system. In addition to this, the configuration space of the bridge is explored in terms of aggregate connection data rate and bit-level parallelism in optics, in search for the most energy-efficient configuration for the bridge and for the network as a whole. To expand the configuration space, we add a unique technology optimization plane, where we consider two successive CMOS process nodes (40nm and 28nm) and a high-performance 130nm BiCMOS node. An interesting outcome of the thesis is the characterization of the trade-offs arising from the partitioning of the bridge among these technologies. To pursue the above goals, a systematic approach has been adopted that continuously correlates the design choices at the architectural and / or topological level with the corresponding effects in terms of layout efficiency, power consumption and performance.<br>L’incremento delle prestazioni e dell’efficienza energetica dei futuri sistemi di elaborazione non sarà raggiunto solo tramite la tradizionale riduzione delle dimensioni dei dispositivi, ma soprattutto attraverso il miglioramento dei metodi di integrazione a livello sistema (come l’integrazione 2.5D o 3D). L’esito di questo trend saranno sistemi multiprocessore ad elevato parallelismo che richiederanno una banda altissima sia per le comunicazioni all’interno del chip sia per quelle tra il chip e l’esterno. In questo contesto, le prestazioni aggregate del sistema dovranno essere sostenute da un'infrastruttura di comunicazione scalabile a livello chip che sia in grado di fornire alte densità di banda, di estendersi alla comunicazione off-chip in modo trasparente, di ridurre la latenza ed il consumo energetico. Considerando i recenti progressi della fotonica del silicio, le reti di interconnessioni ottiche integrate (ONoCs) risultato la tecnologia più promettente per superare il collo di bottiglia della comunicazione e per continuare lo scaling delle architetture many-core esistenti. Rispetto alle tradizionali NoC elettroniche, le ONoCs preservano il paradigma del networking tra gli attori della comunicazione a livello chip, ma cambiano il substrato tecnologico. Tuttavia, le ONoCs attualmente soffrono di un enorme divario tra gli sviluppatori della tecnologia e i progettisti a livello sistema, che impedisce la loro "system-ability", ovvero la capacità di progettare a livello sistema utilizzando questa tecnologia emergente. Un investimento di ricerca sulla automazione della progettazione e sui metodi di integrazione a livello sistema è l'unico modo per colmare il divario e per consentire ai progettisti di fornire soluzioni efficienti e non-intuitive per i problemi di connettività che devono affrontare. A tal fine, la mia tesi di dottorato mira a migliorare la "system-ability" di una specifica famiglia di ONoC, ossia il wavelength-routed (WRONoCs). In particolare, la tesi affronta due aspetti correlati del divario: 1)Da un lato, la tesi persegue metodologie di sintesi ad elevata integrazione verticale per consentire l'esplorazione dello spazio di progetto e la specifica di soluzioni astratte per il problema di connettività sotto esame, oltre al loro raffinamento progressivo in strutture fisiche reali. Questo rappresenta un contributo fondamentale per conoscere uno spazio di progetto che è attualmente limitato ai pochi punti che l’intuizione dei ricercatori riesce a concepire. Ultimamente, questo approccio consiste nel portare la consolidata disciplina dell’automazione della progettazione oltre le sue radici elettroniche. 2)D'altro lato, la tesi studia il metodo di integrare le reti nanofotoniche al silicio con gli altri componenti a livello architetturale. Questo problema di integrazione “orizzontale” è tipicamente trascurato dalla letteratura scientifica, poiché è risolto in maniera semplicistica tramite uno stadio di circuiti di conversione da elettronica a ottica (E/O) e viceversa (O/E). Questa tesi dimostra che l'interfacciamento di tali reti con la parte elettronica del sistema è molto più complesso di questo modello semplificato, dal momento che richiede la progettazione di un nuovo blocco architetturale implementato mediante tecnologie potenzialmente eterogenee, e che ho chiamato " Bridge". Questo bridge in realtà ha un impatto significativo sul bilancio energetico e sulle prestazioni dell’intera rete ottica integrata. La mia tesi ha esplorato lo spazio delle configurazioni del bridge in un piano di ottimizzazione bidimensionale che include la velocità di trasmissione complessiva di un segnale ottico ed il livello di parallelismo dei dati su una connessione, con lo scopo di quantificare i trade-off performance-energia sia per il bridge sia per la rete completa.

This thesis introduces the development of an integrated system for the design of layouts for special purpose machines (SPMs). SPMs are capable of performing several machining operations (such as drilling, milling, and tapping) at the same time. They consist of elements that can be arranged in different layouts. Whilst this is a unique feature that makes SPMs modular, a high level of knowledge and experience is required to rearrange the SPM elements in different configurations, and also to select appropriate SPM elements when product demand changes and new layouts are required. In this research, an integrated system for SPM layout design was developed by considering the following components: an expert system tool, an assembly modelling approach for SPM layouts, an artificial intelligence tool, and a CAD design environment. SolidWorks was used as the 3D CAD environment. VisiRule was used as the expert system tool to make decisions about the selection of SPM elements. An assembly modelling approach was developed with an SPM database using a linked list structure and assembly relationships graph. A case-based reasoning (CBR) approach was developed and applied to automate the selection of SPM layouts. These components were integrated using application programing interface (API) features and Visual Basic programming language. The outcome of the application of the novel approach that was developed in this thesis is reducing the steps for the assembly process of the SPM elements and reducing the time for designing SPM layouts. As a result, only one step is required to assemble any two SPM elements and the time for the selection process of SPM layouts is reduced by approximately 75% compared to the traditional processes. The integrated system developed in this thesis will help engineers in design and manufacturing fields to design SPM layouts in a more time-effective manner.

Chip-scale photonics has emerged as an exciting field which can potentially solve many of the problems plaguing the high-performance computing industry, from large-scale to embedded. In theory, photonics is a superior communication medium because of its higher bandwidth density using wave-division multiplexing and bandwidth-power translucency to distance traveled. In practice, physical-layer design and engineering issues such as optical loss, crosstalk, and packaging have slowed its entry into widespread adoption at the chip and board scale. In this work, we present these issues and potential design improvements. The major contributions, however, are the tools and methods we have developed for the design of photonic interconnection networks, including a system-level simulator and CAD and modeling environment for layout, both of which are publicly available to the research community.

To solve these issues, in this thesis the consistent effort in developing a quick tools assisted IC design platform is presented. First, a reconfigurable solution is proposed for some analog/mixed-signal (AMS) system which requires flexibility to a certain extent, such as a reconfigurable RFID solution for different communicating distances. Second, for further demand of increasing the flexibility, a novel approach for ADA is presented, which provides a highly automatic design flow for analog circuits to realize the "SPEC (Specification) in, GDS out" goal. Considering all kinds of higher order effects and uncertainties under deep submicron or even more advanced technologies, reliable design and fastness in processing are the two major concerns instead of the traditional pure optimization for best performance. To get a good balance among performance, reliability and turnaround time, an Application-Specific design flow with in-built knowledge-based algorithms is applied to deal with ADA issues under advanced technologies, which can quickly provide a reliable design with performance good enough to meet the SPECs for common use.<br>Unlike the highly automatic flow for digital circuits design, analog design automation (ADA) is still far from mature. For mixed-signal applications, analog circuit occupies only a small part on the layout, but the design requires a considerable amount of time and effort, making ADA extremely attractive. However, there are a lot more considerations to cover in analog design flow than its digital counterparts. In addition, the ever downscaling IC means analog circuits have to face more and more small-size effects, insufficient modelings, and the inaccuracy of classic formulas, which are quite difficult to handle. To solve the problem, various tools and methods have been proposed, but all in a digital-like flow, which are trying to develop general algorithms to realize circuit and layout synthesis. Up to now there is still a lot of problems.<br>Hong, Yang.<br>Adviser: C.S. Choy.<br>Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: .<br>Thesis (Ph.D.)--Chinese University of Hong Kong, 2011.<br>Includes bibliographical references (leaves 140-150).<br>Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Abstract also in Chinese.

碩士<br>崑山科技大學<br>機械工程研究所<br>96<br>The purpose of this research is to present the applications of several engineering software tools to improve design processes. The first of these applications treats with the design automation by parametric sketching and design associability in 3D CAD software whilst the second application is related with fluid dynamics. As stated above, the first application revolves around the automation of the design flow process, which is possible by parametric sketching and design associability in 3D CAD. Applications of the technology in liquid food packaging machinery and its advantages are presented in this document. For regular shapes such as circles or lines, parameters are used to link dimensions of relative parts while for irregular shapes, such as curves and surfaces, associability is used to do the work in an assembly. Same merit applies to designs of other machineries, on reducing design time and design mistake, enhancing consistency and ease of documentation, therefore liberating designers from redundant day-to-day routine computer-paperwork to make more innovative contributions to their jobs. Several 3D design tools and database software were applied in the research. Moving on to the second application, it’s important to mention that liquid cooling systems are currently the most viable option for heat extraction in non uniform heat sources such a multi-core microprocessors. The thermal characteristics of the new generation of high-power-density CPUs, used in today’s high-end computing applications, are rapidly outpacing the cooling capabilities of the best commercially available strategies. This project intends to develop a new generation of efficient liquid cooling systems which can be produced cheaply and installed inside the computer case. However, this project is focused in the computational simulation, which in turn decreases time and cost design by employing commercial simulation software (Comsol Multiphysics). The internal cooling system development is focused basically in the pump design, and also the best suited water-block design. The major dimensions, as well as different internal geometries, were simulated and tested in order to determine the optimum working conditions of the system as well as its performance. This study numerically investigates the fluid dynamics in an Active-Liquid-Heat-Sink (ALHS) for a computer microprocessor cooling system. Principal concepts, basic design, and the integration of the ALHS technology into an internal CPU liquid cooling system are presented. Basic assumptions and numerical methods, especially for rotating machinery in fluid dynamics in the numerical simulation, are discussed in detail. From the numerical simulation, the stirring effect by the impeller on the velocity field is quite significant. The maximum velocity, which occurs in the vicinity of the impeller, can be well over five times the average velocity. Since convective heat transfer is largely dependent on liquid velocity, much higher cooling efficiency is expected, especially in the neighborhood of the impeller that could be located on top of the CPU heat source. The simulation also revealed that with the increase of impeller rpm, the velocity as well the flow rate increase almost linearly. This result is very useful for the design and optimization of the cooling system.

碩士<br>國立臺灣科技大學<br>工程技術研究所<br>83<br>This study proposes CAD environment for traditional architecture design studio. The environment, based upon current architecture design education criteria, is facilitated with CAD tools and established to assist students efficiently process design

<p>FRET-enabled optical computing is a new computing paradigm that uses the energy of incident photons to perform computation in molecular-scale circuits composed of inter-communicating photoactive molecules. Unlike conventional computing approaches, computation in these circuits does not require any electric current; instead, it relies on the controlled-migration of energy in the circuit through a phenomenon called Förster Resonance Energy Transfer (FRET). This, coupled with other unique features of FRET circuits can enable computing in new domains that are unachievable by the conventional semiconductor-based computing, such as in-cell computing or targeted drug delivery. In this thesis, we explore novel FRET-based multiplexing techniques to significantly increase the storage density of optical storage media. Further, we develop analysis algorithms, and computer-aided design tools for FRET circuits.</p><p>Existing computer-aided design tools for FRET circuits are predominantly ad hoc and specific to particular functionalities. We develop a generic design-automation framework for FRET-circuit optimization that is not limited to any particular functionality. We also show that within a fixed time-budget, the low-speed of Monte-Carlo-based FRET-simulation (MCS) algorithms can have a potentially-significant negative impact on the quality of the design process, and to address this issue, we design and implement a fast FRET-simulation algorithm which is up to several million times faster than existing MCS algorithms. We finally exploit the unique features of FRET-enabled optical computing to develop novel multiplexing techniques that enable orders of magnitude higher storage density compared to conventional optical storage media, such as DVD or Blu-Ray.</p><br>Dissertation

<p>Digital microfluidics is an emerging technology that provides fluid-handling capability on a chip. Biochips based on digital microfluidics have therefore enabled the automation of laboratory procedures in biochemistry. By reducing the rate of sample and reagent consumption, digital microfluidic biochips allow continuous sampling and analysis for real-time biochemical analysis, with application to clinical diagnostics, immunoassays, and DNA sequencing. Recent advances in technology and applications serve as a powerful driver for research on computer-aided design (CAD) tools for biochips.</p><p>This thesis research is focused on a design automation framework that addresses chip synthesis, droplet routing, control-pin mapping, testing and diagnosis, and error recovery. In contrast to prior work on automated design techniques for digital microfluidics, the emphasis here is on practical CAD optimization methods that can target different design problems in a unified manner. Constraints arising from the underlying technology and the application domain are directly incorporated in the optimization framework.</p><p>The avoidance of cross-contamination during droplet routing is a key design challenge for biochips. As a first step in this thesis research, a droplet-routing method based on disjoint droplet routes has been developed to avoid cross-contamination during the design of droplet flow paths. A wash-operation synchronization method has been developed to synchronize wash-droplet routing steps with sample/reagent droplet-routing steps by controlling the order of arrival of droplets at cross-contamination sites.</p><p>In pin-constrained digital microfluidic biochips, concurrently-implemented fluidic operations may involve pin-actuation conflicts if they are not carefully synchronized. A two-phase optimization method has been proposed to identify and synchronize these fluidic operations. The goal is to implement these fluidic operations without pin-actuation conflict, and minimize the duration of implementing the outcome sequence after synchronization.</p><p>Due to the interdependence between droplet routing and pin-count reduction, this thesis presents two optimization methods to concurrently solve the droplet-routing and the pin-mapping design problems. First, an integer linear programming (ILP)-based optimization method has been developed to minimize the number of control pins. Next an efficient heuristic approach has been developed to tackle the co-optimization problem.</p><p>Dependability is an important system attribute for microfluidic biochips. Robust testing methods are therefore needed to ensure correct results. This thesis presents a built-in self-test (BIST) method for digital microfluidic biochips. This method utilizes digital microfluidic logic gates to implement the BIST architecture. A cost-effective fault diagnosis method has also been proposed to locate a single defective cell, multiple</p><p>rows/columns with defective cells, as well as an unknown number of rows/columns-under-test with defective cells. A BIST method for on-line testing of digital microfluidic biochips has been proposed. An automatic test pattern generation (ATPG) method has been proposed for non-regular digital microfluidic chips. A pin-count-aware online testing method has been developed for pin-constrained designs to support the execution of both fault testing and the target bioassay protocol.</p><p>To better monitor and manage the execution of bioassays, control flow has been incorporated in the design and optimization framework. A synthesis method has been developed to incorporate control paths and an error-recovery mechanism during chip design. This method addresses the problem of recovering from fluidic errors that occur</p><p>during on-chip bioassay execution.</p><p>In summary, this thesis research has led to a set of unified design tools for digital microfluidics. This work is expected to reduce human effort during biochip design and biochip usage, and enable low-cost manufacture and more widespread adoption for laboratory procedures.</p><br>Dissertation

碩士<br>國立中央大學<br>資訊管理學系在職專班<br>105<br>In the semiconductor industry, electronic design automation tools are used for designing the integrated circuits. The infrastructure of design automation tools includes computing nodes, network and storage system. As the IC design improves continuously, the data volume on a wafer increases with the same ratio. In order to accelerate the IC design and shorten the production time, the integration of electronic design automation software with its infrastructure becomes important. The purpose of this study is to find out the suitable parameters and configuration for the computing environment of electronic design automation so as to enhance the overall performance the overall system configuration. The case - R Company is an IC design company. It focuses on IC research and design. Its product lines span communications network ICs, computer peripheral ICs and multimedia ICs. In-depth interviews were applied to understand R Company’s EDA tool software environment and storage system architecture. R Company's real project data were used to test different storage system configurations in order to find out the best configuration for the company’s computing environment. The results of the tests reveal that the Flash Pool cache always performs better than the Flash Cache for the NetApp storage system. Also, when a NetApp storage system configured two data "aggregates" and more than four "volumes" under one controller, the project run time reduced significantly. Therefore, using Flash Pool cache with the above storage configuration can improve the overall performance of electronic design automation project. The results of this study can be a guideline for other industries in procuring and planning storage systems. Applying the results will improve the overall system performance by reducing the performance problem caused by the storage system, avoiding the delay of the IC design and production.

Στην παρούσα διπλωματική εργασία ασχοληθήκαμε με την μελέτη, ανάλυση και εξομοίωση του πιο διαδεδομένου αναλογικού κυκλώματος, του Τελεστικού Ενισχυτή. Αρχικά επιχειρήθηκε μια ανάλυση της επιμέρους δομής ενός Τ.Ε, ενώ παράλληλα γίνεται μια παρουσίαση κάποιων βασικών αναλογικών κυκλωμάτων που χρησιμοποιούνται στον σχεδιασμό του. Ακολούθως επεξηγούνται οι βασικές καθώς και οι προηγμένες επιδόσεις και τεχνικά χαρακτηριστικά του Τ.Ε και δίνονται παραδείγματα για την διασαφήνιση των φαινομένων που τις επηρεάζουν καθώς και των τεχνικών βελτίωσής τους. Σε όλες τις εξομοιώσεις χρησιμοποιήθηκαν EDA (Electronic design automation) tools και η όλη προσέγγιση γίνεται με την χρήση της CMOS τεχνολογίας. Τέλος, παρουσιάζονται οι κατευθύνσεις που τείνει να ακολουθεί σήμερα η τεχνολογία των Τ.Ε. καθώς και θέματα που απασχολούν ή και πρόκειται να απασχολήσουν και στο μέλλον τους σχεδιαστές.<br>In this Diploma Thesis, I studied, analyzed and simulated today’s most widely used analog circuit block, the Operational Amplifier. In the beginning an analysis of the basic OpAmp structure is presented and various analog circuits that are commonly used during the design process of an OpAmp are described. Then, basic as well as more advanced technical characteristics of the OpΑmp are explained and simulation results are presented to illustrate the phenomena and the parameters that affect the performance of the OpAmp. In simulations EDA (Electronic design automation) tools were used and the whole approach was made with the use of CMOS technology. Concluding, technology trends and issues that designers will face in the future are presented.