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Dissertations / Theses on the topic 'Pipeline code'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 May 2024

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1

HU, PING. "Code garde : traduction, analyse statique, pipeline logiciel." Paris 6, 2000. http://www.theses.fr/2000PA066217.

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Cette these etudie et developpe les techniques de compilation pour des processeurs ilp avec execution gardee. Ces techniques comprennent la traduction, l'analyse, ainsi que la parallelisation du code garde. En ce qui concerne la traduction, nous proposons un algorithme pour traduire des codes sequentiels en codes gardes. Cette traduction tient aussi compte des constructions de boucles dans les graphes de flots de controle. La correction de l'algorithme a ete prouvee formellement en employant une semantique operationnelle pour specifier la signification des codes sequentiels et des codes gardes

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2

Fellahi, Mohammed. "Des réseaux de processus cyclo-statiques à la génération de code pour le pipeline multi-dimensionnel." Phd thesis, Université Paris Sud - Paris XI, 2011. http://tel.archives-ouvertes.fr/tel-00683224.

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Les applications de flux de données sont des cibles importantes de l'optimisation de programme en raison de leur haute exigence de calcul et la diversité de leurs domaines d'application: communication, systèmes embarqués, multimédia, etc. L'un des problèmes les plus importants et difficiles dans la conception des langages de programmation destinés à ce genre d'applications est comment les ordonnancer à grain fin à fin d'exploiter les ressources disponibles de la machine.Dans cette thèse on propose un "framework" pour l'ordonnancement à grain fin des applications de flux de données et des boucl

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3

Strand, Anton. "Continuous Integration Pipelines to Assess Programming Assignments : Test Like a Professional." Thesis, Linnéuniversitetet, Institutionen för datavetenskap och medieteknik (DM), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-96713.

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Examiners of programming assignments in higher education and people in the software industry both need to test and review code. However, the assessing techniques used are often quite different. The IT industry often uses agile work methods like continuous integration and automated tests, while examiners either do manual assessments or rely on code grading tools. The students will most likely become developers and work using agile processes. Therefore, there are possible benefits of universities trying to imitate the work processes of the software industry. The purpose of this study was to deve

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4

Endo, Fernando Akira. "Génération dynamique de code pour l'optimisation énergétique." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAM044/document.

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Dans les systèmes informatiques, la consommation énergétique est devenue le facteur le plus limitant de la croissance de performance observée pendant les décennies précédentes. Conséquemment, les paradigmes d'architectures d'ordinateur et de développement logiciel doivent changer si nous voulons éviter une stagnation de la performance durant les décennies à venir.Dans ce nouveau scénario, des nouveaux designs architecturaux et micro-architecturaux peuvent offrir des possibilités d'améliorer l'efficacité énergétique des ordinateurs, grâce à la spécialisation matérielle, comme par exemple les co

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5

Руденко, Людмила Дмитрівна, Людмила Дмитриевна Руденко та Liudmyla Dmytrivna Rudenko. "До питання про визначення поняття магістральних трубопроводів". Thesis, Десна Полиграф, 2015. http://essuir.sumdu.edu.ua/handle/123456789/60178.

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Запропоновано у Законі України «Про трубопровідний транспорт» закріпити визначення магістральних трубопроводів: магістральним трубопроводом є технологічний комплекс, що функціонує як єдина система і до якого входить окремий трубопровід з усіма об'єктами і спорудами, зв'язаними з ним єдиним технологічним процесом, або кілька трубопроводів, спроектованих та збудованих згідно з державними будівельними вимогами щодо магістральних трубопроводів, якими здійснюються транзитні, міждержавні, міжрегіональні поставки продуктів транспортування споживачам, підготовлених відповідно до вимог для транспортува

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Ageneau, Paul-Louis. "Fiabilité et problèmes de déploiement du codage réseau dans les réseaux sans fil." Thesis, Paris, ENST, 2017. http://www.theses.fr/2017ENST0007/document.

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Même si les réseaux de données ont beaucoup évolué au cours des dernières décennies, les paquets sont presque toujours transmis d’un nœud à l’autre comme des blocs de données inaltérables. Cependant, ce paradigme fondamental est aujourd’hui remis en question par des techniques novatrices comme le codage réseau, qui promet des améliorations de performance et de fiabilité si les nœuds sont autorisés à mixer des paquets entre eux. Les réseaux sans fil manquent de fiabilité en raison des obstacles ou interférences que subissent les liens sans fil, et ces problèmes peuvent empirer dans des topologi

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Ageneau, Paul-Louis. "Fiabilité et problèmes de déploiement du codage réseau dans les réseaux sans fil." Electronic Thesis or Diss., Paris, ENST, 2017. http://www.theses.fr/2017ENST0007.

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Même si les réseaux de données ont beaucoup évolué au cours des dernières décennies, les paquets sont presque toujours transmis d’un nœud à l’autre comme des blocs de données inaltérables. Cependant, ce paradigme fondamental est aujourd’hui remis en question par des techniques novatrices comme le codage réseau, qui promet des améliorations de performance et de fiabilité si les nœuds sont autorisés à mixer des paquets entre eux. Les réseaux sans fil manquent de fiabilité en raison des obstacles ou interférences que subissent les liens sans fil, et ces problèmes peuvent empirer dans des topologi

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Gao, Guang Rong. "A pipelined code mapping scheme for static data flow computers." Thesis, Massachusetts Institute of Technology, 1986. http://hdl.handle.net/1721.1/37165.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1986.<br>MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING<br>Bibliography: leaves 245-252.<br>by Gao Guang Rong.<br>Ph.D.

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Mamon, Andrei. "Graphical visualization of softwarepipelined code execution on pipelined andclustered VLIW DSP processors." Thesis, Linköping University, PELAB - Programming Environment Laboratory, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-57642.

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<p>This report follows the development, testing and evaluation of a retargetable compilervisualization framework Optvis which can be used to visualize compiler generated code fordifferent VLIW architectures. Optvis is implemented in C++ programming language andfunctions as both standalone application and as plug-in for the retargetable compilerframework OPTIMIST.The purpose of this thesis work is to present the Optvis framework, to give a detailed viewover its internal structure and interaction with an end user. Additionally Optvis-OPTIMISTintegration is discussed. Testing and evaluation round

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TOUATI, Sid-Ahmed-Ali. "La consommation en registres en présence de parallélisme d'instructions." Phd thesis, Université de Versailles-Saint Quentin en Yvelines, 2002. http://tel.archives-ouvertes.fr/tel-00007405.

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Aujourd'hui, le fait que la mémoire constitue un goulot d'étranglement pour les performances des programmes est un truisme. Les compilateurs doivent donc optimiser les programmes afin d'éviter de recourir à la mémoire, et ceci en utilisant au mieux les registres disponibles dans le processeur à parallélisme d'instructions (ILP).<br /><br />Cette thèse réexamine le concept de la pression des registres en lui donnant une plus forte priorité par rapport à l'ordonnancement d'instructions, sans ôter à ce dernier ses possibilités d'extraction de parallélisme. Nous proposons de traiter le problème de

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Tournavitis, Georgios. "Profile-driven parallelisation of sequential programs." Thesis, University of Edinburgh, 2011. http://hdl.handle.net/1842/5287.

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Traditional parallelism detection in compilers is performed by means of static analysis and more specifically data and control dependence analysis. The information that is available at compile time, however, is inherently limited and therefore restricts the parallelisation opportunities. Furthermore, applications written in C – which represent the majority of today’s scientific, embedded and system software – utilise many lowlevel features and an intricate programming style that forces the compiler to even more conservative assumptions. Despite the numerous proposals to handle this uncertainty

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TOUATI, Sid-Ahmed-Ali. "Méthodes d'optimisations de programmes bas niveau." Habilitation à diriger des recherches, Université de Versailles-Saint Quentin en Yvelines, 2010. http://tel.archives-ouvertes.fr/tel-00665897.

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Ce manuscrit synthétise plus d'une décade de notre recherche académique sur le sujet d'optimisation de codes bas niveau, dont le but est une intégration dans un compilateur optimisant ou dans un outil d'optimisation semi-automatique. Dans les programmes bas niveau, les caractéristiques du processeur sont connues et peuvent être utilisées pour générer des codes plus en harmonie avec le matériel. Nous commençons notre document par une vue générale sur le problème d'ordonnancement des phases de compilation. Actuellement, des centaines d'étapes de compilation et d'optimisation de codes existent; u

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Jahn, Janmartin [Verfasser], and J. [Akademischer Betreuer] Henkel. "Resource Allocation for Software Pipelines in Many-core Systems / Janmartin Jahn. Betreuer: J. Henkel." Karlsruhe : KIT-Bibliothek, 2014. http://d-nb.info/1050767497/34.

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Wyngaard, Janet Ruth. "An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline." Doctoral thesis, University of Cape Town, 2014. http://hdl.handle.net/11427/13265.

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Includes bibliographical references.<br>In light of the power, memory, ILP, and utilisation walls facing the computing industry, this work examines the hypothetical many-core approach to finding greater compute performance and efficiency. In order to achieve greater efficiency in an environment in which Moore’s law continues but TDP has been capped, a means of deriving performance from dark and dim silicon is needed. The many-core hypothesis is one approach to exploiting these available transistors efficiently. As understood in this work, it involves trading in hardware control complexity for

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Avdic, Kenan. "On-chip Pipelined Parallel Mergesort on the Intel Single-Chip Cloud Computer." Thesis, Linköpings universitet, Programvara och system, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-111513.

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With the advent of mass-market consumer multicore processors, the growing trend in the consumer off-the-shelf general purpose processor industry has moved away from increasing clock frequency as the classical approach for achieving higher performance. This is commonly attributed to the well-known problems of power consumption and heat dissipation with high frequencies and voltage. This paradigm shift has prompted research into a relatively new field of "many-core" processors, such as the Intel Single-chip Cloud Computer. The SCC is a concept vehicle, an experimental homogenous architecture emp

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Malenta, Mateusz. "Exploring the dynamic radio sky with many-core high-performance computing." Thesis, University of Manchester, 2018. https://www.research.manchester.ac.uk/portal/en/theses/exploring-the-dynamic-radio-sky-with-manycore-highperformance-computing(fe86c963-e253-48c0-a907-f8b59c44cf53).html.

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As new radio telescopes and processing facilities are being built, the amount of data that has to be processed is growing continuously. This poses significant challenges, especially if the real-time processing is required, which is important for surveys looking for poorly understood objects, such as Fast Radio Bursts, where quick detection and localisation can enable rapid follow-up observations at different frequencies. With the data rates increasing all the time, new processing techniques using the newest hardware, such as GPUs, have to be developed. A new pipeline, called PAFINDER, has been

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Li, Yunming. "Machine vision algorithms for mining equipment automation." Thesis, Queensland University of Technology, 2000.

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Jaber, Houssein. "Conception architecturale haut débit et sûre de fonctionnement pour les codes correcteurs d'erreurs." Thesis, Metz, 2009. http://www.theses.fr/2009METZ042S/document.

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Les systèmes de communication modernes exigent des débits de plus en plus élevés afin de traiter des volumes d'informations en augmentation constante. Ils doivent être flexibles pour pouvoir gérer des environnements multinormes, et évolutifs pour s'adapter aux normes futures. Pour ces systèmes, la qualité du service (QoS) doit être garantie malgré l'évolution des technologies microélectroniques qui augmente la sensibilité des circuits intégrés aux perturbations externes (impact de particules, perte de l'intégrité du signal, etc.). La tolérance aux fautes devient un critère important pour améli

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Broich, René. "A Soft-core processor architecture optimised for radar signal processing applications." Diss., University of Pretoria, 2013. http://hdl.handle.net/2263/40821.

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Current radar signal processor architectures lack either performance or flexibility in terms of ease of modification and large design time overheads. Combinations of processors and FPGAs are typically hard-wired together into a precisely timed and pipelined solution to achieve a desired level of functionality and performance. Such a fixed processing solution is clearly not feasible for new algorithm evaluation or quick changes during field tests. A more flexible solution based on a high-performance soft-core processing architecture is proposed. To develop such a processing architecture,

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Kreutz, Marcio Eduardo. "Geração de processador para aplicacao especifica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1997. http://hdl.handle.net/10183/17752.

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Este trabalho propõe a geração de uma arquitetura dedicada a aplicações específicas, baseadas no microcontrolador MCS8051. Por ser utilizado na solução de problemas em indústrias locais, este processador foi escolhido para servir como base em um sistema dedicado. O 8051 dedicado gerado deverá permitir a integração completa do sistema, proporcionando um aumento do valor agregado e, conseqüentemente, a diminuição do custo. Busca-se com a otimização da arquitetura obter um conjunto de instruções reduzido, construído com as instruções mais utilizadas em cada aplicação. O objetivo principal da otim

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Santos, Ronaldo Gonçalves dos. "Avaliação da molhabilidade de superficies de oleodutos atraves de medidas de angulo de contato : efeito de aslfaltenos e de acidos naftenicos." [s.n.], 2003. http://repositorio.unicamp.br/jspui/handle/REPOSIP/267190.

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Orientadores: Rahoma Sadeg Mohamed, Watson Loh<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Quimica<br>Made available in DSpace on 2018-08-06T20:10:23Z (GMT). No. of bitstreams: 1 Santos_RonaldoGoncalvesdos_M.pdf: 2592752 bytes, checksum: 0b29b2d43cb92bfcf2b5329b8efb1f8c (MD5) Previous issue date: 2003<br>Resumo: O alto custo de produção e transporte dos óleos pesados é a principal barreira para a exploração das suas abundantes reservas mundiais. Tecnologias de fluxo de petróleo em oleodutos baseadas no confinamento do óleo em uma seção anular aquosa

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LI, HONG-ZHANG, and 李鴻璋. "MARS architecture code optimization under pipeline constraints." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/49390125536653154042.

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博士<br>國立臺灣大學<br>電機工程研究所<br>80<br>MARS處理機是一種流線化的架構，以加快控制轉換以乃在Lisp語言中串列進出的處理。MARS的結構中包含有指令擷取單元，整數處理單元，串列處理單元，和記憶／快速記憶體控制單元；以及可隨和之浮點運算單元。指令在MARS處理機或是其他的管線化的處理機上都被分割成串小的管線階，不同的指令可在不同的管線階上同時地執行。這樣的架構會構成管線危障如果下一個指令需要上一個指令執行的結果。在類似MARS的流線化的處理機上，管線危障可以被細分成三種：分別是資料、構造、以及循序危障。構造的危障源於硬體資料的不足夠，資料危障源於執行資料的相依性，而循序危障則源於對分岐指令的潛在不正確的執行。針對資料與構造危障重組方面，我們指出一個稱做強式資料相依圖(EDAG)來表示指令在指述層次和管線層次的相依以及限制的關係。我們採用的是在後指令產生的重組方式，並且證明在MARS處理機上這個重組是屬於NP完備

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Li, Ko-Yin, and 李克穎. "Pipeline Decoding of New LDPC-HDPC Product Code for MIMO-OFDM System." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/39814782478456407970.

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碩士<br>立德管理學院<br>應用資訊研究所<br>94<br>We comprise a new structure of product code with low-density parity-check (LDPC) codes and high-density parity-check (HDPC) codes to develop a new linear block code family for MIMO channels. And, a pipeline decoding mechanism for the new code is also proposed to get higher error performance than only LDPC code. Since the traditional LDPC decoding schedule need a large storage depended on the total number of edges in Tanner graph, our decoding scheme applies parallel processing technique to reduce required memory and enhance the decoding performance. Meanwhile,

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"Algoritmos de sintese de Pipeline de processadores para sistemas embutidos : minimização de custos, numero de processadores e latencia." Tese, Biblioteca Digital da Unicamp, 2006. http://libdigi.unicamp.br/document/?code=vtls000402860.

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Mullapudi, Ravi Teja. "Polymage : Automatic Optimization for Image Processing Pipelines." Thesis, 2015. http://etd.iisc.ac.in/handle/2005/3757.

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Image processing pipelines are ubiquitous. Every image captured by a camera and every image uploaded on social networks like Google+or Facebook is processed by a pipeline. Applications in a wide range of domains like computational photography, computer vision and medical imaging use image processing pipelines. Many of these applications demand high-performance which requires effective utilization of modern architectures. Given the proliferation of camera enabled devices and social networks optimizing these emerging workloads has become important both at the data center and the embedded device

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Mullapudi, Ravi Teja. "Polymage : Automatic Optimization for Image Processing Pipelines." Thesis, 2015. http://etd.iisc.ernet.in/2005/3757.

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Image processing pipelines are ubiquitous. Every image captured by a camera and every image uploaded on social networks like Google+or Facebook is processed by a pipeline. Applications in a wide range of domains like computational photography, computer vision and medical imaging use image processing pipelines. Many of these applications demand high-performance which requires effective utilization of modern architectures. Given the proliferation of camera enabled devices and social networks optimizing these emerging workloads has become important both at the data center and the embedded device

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Ting, Chien-Tung, and 丁建同. "A Comparative Study of the Management Mechanism of the National Army''s Underground Oil Pipeline and the Current Code--Based on the Kaohsiung Gas Explosion Event." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/4k9dsy.

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碩士<br>義守大學<br>公共政策與管理學系<br>107<br>On the night of July 31, 103, the public reported that there was a suspected gas leak. A few hours later, a series of explosions occurred in the area, killing 32 people and injuring 321 people, causing serious damage to at least three important roads including the three major ones, two roads, the Kaixuan three roads, and one heart and one road. The surrounding stores were also damaged by the explosion. And caused significant economic losses. After investigation, it was found that the tetra-propylene pipeline was improperly covered in the drain tank culvert, ca

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Fonseca, Nelson Ricardo Matos. "PACE: Domain-Specific Language to Enable Developers Autonomy in Dealing with Complex Build Pipelines." Master's thesis, 2019. http://hdl.handle.net/10400.6/10051.

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The complexity of the product developed makes its validation processes too complex, namely build pipelines. This complexity of build pipelines, coupled with the lack of knowledge in different teams about their manipulation, means that teams cannot be fully independent. This independence makes one team responsible for maintaining build pipelines. The lack of independence on the teams means that they can not develop their components from end to end, which can lead to a delay in development if the team responsible for maintaining pipelines cannot fulfill all requests in a short time. Since the so

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Huang, Che Chi, and 黃哲奇. "VLSI pipelined Reed-Solomon CODEC implementation." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/13804087131293266390.

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Zhan, Ren-Hao, and 詹仁豪. "A Study on Pipeline Sharing for Multi-core Computing Environments." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/00100616808468459297.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>102<br>A pipeline is a set of data processing stages, which is popular for improving system performance by paralleling processing units. In this thesis we study a novel optimize problem, called pipeline sharing, which considers the problem of allocating cores between different packet types in order to minimize the average delay. The system we designed is a pipeline-based and multi-core computing model to serve several packet types. Each pipeline in the system processes one or more packet types. Given the number of cores provided, our goal is to design the pipeline a

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Chen, Kuan-Lin, and 陳冠琳. "Genetic Algorithm for Pipeline Sharing in Multi-core Computing Environments." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/ecb67s.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>106<br>As multi-core architectures and parallel computing become more and more popular, how to effectively increase throughput is a challenge for developer. Pipeline architecture has long been widely used in various fields; the concept of pipeline architecture can help us greatly enhance the system throughput. However, when the number of packets increase, developer has limited number of cores for pipelines. In this thesis we study a novel optimize problem, called pipeline sharing, which is a trade off between the number of needed cores and the average delay. Our goa

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Lin, Yong-Zong, and 林永宗. "An Efficient Field-Partition Based Code Compression and Its Pipelined Decompression System." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/61488311040867842491.

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碩士<br>國立高雄應用科技大學<br>電子與資訊工程研究所碩士班<br>94<br>In this paper, we propose an efficient code compression and decompression system. The instruction density of ARM7TDMI can be increased that using our field partition compression method, put the program memory with effect and then reduce the rate of memory on the chip further. In the first place, we accord to the branch instruction to demarcate the basic block which defined in the machine code. And then calculate the appearance probability of the symbols of each field in the machine code. Base on the level of probability to re-integrate each field, and

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Yin-TzChen and 陳胤孜. "A 13-stage Pipeline Soft Processor Core Verified by Linux OS." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/98561821649737080209.

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碩士<br>國立成功大學<br>電腦與通信工程研究所<br>101<br>This thesis is mainly about building a high-speed processor with register transfer level (RTL) under ARM instruction set architecture. In terms of register-transfer level design, this processor is implemented with a 13-stage pipeline architecture along with a forwarding unit and a branch predictor. The best way to verify the integrality and correctness of the processor is through running programs. However, due to the characteristics of normal programs, they can verify only the basic functions of the processor, and leaving many advanced functions unverified.

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Nagarakatte, Santosh G. "Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques." Thesis, 2007. https://etd.iisc.ac.in/handle/2005/507.

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Instruction scheduling and Software pipelining are important compilation techniques which reorder instructions in a program to exploit instruction level parallelism. They are essential for enhancing instruction level parallelism in architectures such as very Long Instruction Word and tiled processors. This thesis addresses two important problems in the context of these instruction reordering techniques. The first problem is for general purpose applications and architectures, while the second is for media and graphics applications for tiled and multi-core architectures. The first problem deals

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Nagarakatte, Santosh G. "Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques." Thesis, 2007. http://hdl.handle.net/2005/507.

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Instruction scheduling and Software pipelining are important compilation techniques which reorder instructions in a program to exploit instruction level parallelism. They are essential for enhancing instruction level parallelism in architectures such as very Long Instruction Word and tiled processors. This thesis addresses two important problems in the context of these instruction reordering techniques. The first problem is for general purpose applications and architectures, while the second is for media and graphics applications for tiled and multi-core architectures. The first problem deals

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Chih-Tsun, Huang, and 黃稚存. "VLSI Design of A New High Speed Pipelined Reed-Solomon CODEC." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/51969443591245080602.

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Das, Ansuman DiptiSankar. "Efficient multiplier-less VLSI architectures for folded pipelined complex FFT core." Thesis, 2013. http://ethesis.nitrkl.ac.in/4911/1/211EC2077.pdf.

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Fast Fourier transform (FFT) has become ubiquitous in many engineering applications. FFT is one of the most employed blocks in many communication and signal processing systems. Efficient algorithms are being designed to improve the architecture of FFT. Higher radix FFT algorithms have the traditional advantage of using less number of computational elements and are more suitable for calculating FFT of long data sequence. Among the different proposed algorithms, the split-radix FFT has shown considerable improvement in terms of reducing hardware complexity of the architecture compared to radix-2

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Chang, Yu-Sung, and 張祐菘. "The Design and Verification of an IP Core for Pipeline AES Based on AXI4 Interface." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/t2z5np.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>107<br>In this thesis, a pipelined architecture of AES Encryption/Decryption based on AXI4 interface is proposed. This architecture emphasizes area and throughput, reduces hardware cost and improves its computing performance. According to the AES algorithm, the input data is 128 bits and the cipher key has three options: 128, 192 or 256 bits. In order to reduce area and improve its computing performance, we use an inner-round pipelining architecture, combining Encryption and Decryption to share hardware. The composite field arithmetic is used in Subbytes transformati

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dolph and 林榮壕. "A Design and Test of Pipeline DSP Processor with Special Application in H.263 Codec Processor." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/14096330985781279645.

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碩士<br>中華大學<br>電機工程學系碩士班<br>89<br>In this design of DSP, the instruction set and addressing modes are defined in RISC approach, and except the regular DSP instructions, we add a couple of multimedia instructions in our DSP design, such as DCT、Motion Estimation and Butterfly instructions. The instruction length is 20-bit and data is 8-bit long. The instruction cycle is then proposed and the five-stage pipeline architecture is developed. The problems of data dependency、resource conflict、conditional branch and interrupt in the design of pipeline architecture are addressed. An interrupt controller

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Yeh, Li-Ting, and 葉力廷. "A Parameterized and Dynamic Pipelined Low-Power Transform IP Core Design and Its Performance Analysis Platform." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/13299032388972450627.

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Boscardin, Adriane G. "Development of miniature full flow and model pipeline probes for testing of box core samples of surficial seabed sediments." 2013. https://scholarworks.umass.edu/dissertations/AAI3588996.

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The box corer is a relatively new tool used in the geotechnical community for collection of soft seabed sediments. Miniature full flow and model pipeline probes were developed as tools to characterize and obtain soil parameters of soft seabed sediments collected in the box core for design of offshore pipelines and analysis of shallow debris flows. Probes specifically developed for this study include the miniature t-bar, ball, motorized vane (MV), and toroid. The t-bar, ball, and MV were developed to measure intact and remolded undrained shear strengths (su and sur). The t-bar and ball can obta

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Ngwenya, Themba M. A. "An investigation into the improvement in WCDMA system performance using multiuser detection and interference cancellation." Diss., 2004. http://hdl.handle.net/2263/25329.

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WCDMA is typically characterised as a system capable of providing mobile users with data rates up to 2 Mb/s and beyond. It has been termed an ultra high-speed, ultra high-capacity radio technology that will be able to carry a new range of fast, colourful media, such as colour graphics, video, animations, digital audio, Internet and e-mail that consumers will be able to access over their mobiles devices. This current study has researched on the various existing Multiuser detection (MUD) processes or proposals conducted by various research institutions around the world. It has identified the adv

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Mahale, Gopinath Vasanth. "Algorithm And Architecture Design for Real-time Face Recognition." Thesis, 2016. http://etd.iisc.ac.in/handle/2005/2743.

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Face recognition is a field of biometrics that deals with identification of subjects based on features present in the images of their faces. The factors that make face recognition popular and favorite as compared to other biometric methods are easier operation and ability to identify subjects without their knowledge. With these features, face recognition has become an integral part of the present day security systems, targeting a smart and secure world. There are various factors that de ne the performance of a face recognition system. The most important among them are recognition accuracy of

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Mahale, Gopinath Vasanth. "Algorithm And Architecture Design for Real-time Face Recognition." Thesis, 2016. http://etd.iisc.ernet.in/handle/2005/2743.

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Face recognition is a field of biometrics that deals with identification of subjects based on features present in the images of their faces. The factors that make face recognition popular and favorite as compared to other biometric methods are easier operation and ability to identify subjects without their knowledge. With these features, face recognition has become an integral part of the present day security systems, targeting a smart and secure world. There are various factors that de ne the performance of a face recognition system. The most important among them are recognition accuracy of

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