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Nicklous, Francis Edward. "The Design, Simulation and Synthesis of Pipelined Floating-Point Radix-4 Fast Fourier Transform Data Path in VHDL." Master's thesis, Temple University Libraries, 2010. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/96963.
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Electrical Engineering<br>M.S.E.<br>The Fast Fourier Transform (FFT) converts time or spatial information into the frequency domain. The FFT is one of the most widely used digital signal processing (DSP) algorithms. DSPs are used in a number of applications from communication and controls to speech and image processing. DSPs have also found their way into toys, music synthesizers and in most digital instruments.
Many applications have relied on Digital Signal Processors and Application Specific Integrated Circuits (ASIC) for most of the signal processing needs. DSPs provide an adequate means of performance and efficiency for many applications as well as robust tools to ease the development process. However, the requirements of important emerging DSP applications have begun to exceed the capabilities of DSPs. With this in mind, system developers have begun to consider alternatives such as ASICs and Field Programmable Gate Arrays (FPGA). Although ASICs can provide excellent performance and efficiency, the time, cost and risk associated with the design of ASICs is leading developers towards FPGAs. A number of significant advances in FPGA technology have improved the suitability of FPGAs for DSP applications. These advances include increased device capacity and speed, DSP-oriented architectural enhancements, better DSP-oriented tools, and increasing availability of DSP-oriented IP libraries.
The thesis research focuses on the design of a single precision floating-point radix-4 FFT FPGA using VHDL for real time DSP applications. The paper will go into further detail pertaining to the FFT algorithm used, the description of the design steps taken as well as the results from both simulation and synthesis.<br>Temple University--Theses
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Stuart, David Charles. "VLSI design for pipelined FFT processors." Thesis, Monterey, California: Naval Postgraduate School, 1990. http://hdl.handle.net/10945/28644.
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A system of custom cell building blocks utilizing scaleable CMOS technology is decribed. The cells are design to support the high speed, pipelined addition, subtraction, and multiplication operations neccessary in a cyclic spectral analyser or other applications involving the FFT. The cells are structured in such a manner as to permit a designer to tailor the bit-length of the operations and the number of pipline stages used. Both fixed and floating operations are supported by the system. The size and performance characteristics of devices produced using the cells are compared with previously produced Genesil Silicon Complier pipelined desings. The appendix contains designs of 16-bit mantissa, 12-bit exponent floating point multiplier and adder produced from the standard cells. If fabricated in 1.2(symbol) feature size technology, the theoretical maximum clock speed and throughput rate is 102 MHz with an asymmetric clock and 61 MHz using a symmetric clock waveform. Devices with clock speeds up to 178 MHz are possible if the number of logic cells between a pipeline stage is reduced to one
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Claesson, Jonas. "Design and Implementation of an Asynchronous Pipelined FFT Processor." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1812.
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<p>FFT processors are today one of the most important blocks in communication equipment. They are used in everything from broadband to 3G and digital TV to Radio LANs. This master's thesis project will deal with pipelined hardware solutions for FFT processors with long FFT transforms, 1K to 8K points. These processors could be used for instance in OFDM communication systems. </p><p>The final implementation of the FFT processor uses a GALS (Globally Asynchronous Locally Synchronous) architecture, that implements the SDF (Single Delay Feedback) radix-22 algorithm. </p><p>The goal of this report is to outline the knowledge gained during the master's thesis project, to describe a design methodology and to document the different building blocks needed in these kinds of systems.</p>
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Bone, Ryan T. "FPGA DESIGN OF A HARDWARE EFFICIENT PIPELINED FFT PROCESSOR." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1221855371.
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Pilch, Martin. "Simulace vlnění vody v reálném čase." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2011. http://www.nusl.cz/ntk/nusl-236955.
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Task of this thesis is creation of real-time simulation of the water waves. It is implemented on Mac OS X platform using OpenGL. This thesis is based on height map surface. Heigh map is computed by suming of sinusoids with complex, time-based amplitudes. Fast Fourier transformation, Phillips spectrum and gauss random generator are used to solve this problem. The thesis is also implemented on iOS platform and optimized to run on mobile devices thanks to using programmable graphic pipeline and other drawing and computing optimizations.
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Thangella, Praneeth Kumar, and Aravind Reddy Gundla. "Complex-Multiplier Implementation for Resource Flexible Pipelined FFTs in FPGAs." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16547.
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<p>AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.</p>
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Patwardhan, Anagha. "Fast multipliers-Pipeline Wallace /." Available to subscribers only, 2007. http://proquest.umi.com/pqdweb?did=1453188901&sid=3&Fmt=2&clientId=1509&RQT=309&VName=PQD.
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Flores, Ronald D. "Patching the United States STEM Pipeline| How a Person-Centered Analysis of "Fit" Supports Undergraduate Science Career Motivation." Thesis, California State University, Long Beach, 2018. http://pqdtopen.proquest.com/#viewpdf?dispub=10976055.
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<p> Researchers are learning how to prevent the projected United States shortage of science, technology, engineering, and mathematics (STEM) professionals by retaining more undergraduates in STEM majors. Specifically, since undergraduates generally want to give back to their communities, they experience heightened science career motivation once they "fit" their communal goals with their views of science careers. However, testing the quality of fit is challenging because individuals differ in communal goals and views of science. For the present study, therefore, a person-centered analytical approach was used to identify groups of STEM undergraduates defined by combinations of communal goal endorsement and perceived communal goal affordances. Four groups were identified: Low Incongruent, Moderately Low Incongruent, Average Congruent, and Moderately High Incongruent. Results showed that undergraduates were optimally motivated when both communal goal endorsement and perceived communal goal affordances were moderately high and incongruent. Results also showed that gender and cultural identity could predict group membership.</p><p>
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Sahoo, Bibhudatta. "A new calibration technique for pipelined ADCs." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=1904964641&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Holz, Dan. "FACTORS AFFECTING EROSION ON A NATURAL GAS PIPELINE IN THE CENTRAL APPALACHIANS." Available to subscribers only, 2009. http://proquest.umi.com/pqdweb?did=1885467581&sid=4&Fmt=2&clientId=1509&RQT=309&VName=PQD.
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Harmse, Ingrid. "The management whisperer: Ensuring organisational sustainability, viability and competitive advantage through management development via a practice based future fit talent pipeline." Master's thesis, University of Cape Town, 2017. http://hdl.handle.net/11427/25293.
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The researcher was appointed into the position of General Manager within the Clothing and General Merchandise Supply Chain in a large retail organisation as part of a transformation strategy to turn around a business unit which had historically been delivering substandard performance and had led to significant impacts on organisational performance. Despite the organisation having a number of mechanisms in place to assist line managers to manage the life cycle of an employee during their employment, the performance measures as well as selection of a talent pipeline were measured against the framework of an underperforming environment. Competence was therefore benchmarked on overrated performance against underrated goals which led to ineffective performance and no validity in talent identification. Critical Realism was chosen as an ontological philosophy. Data was generated through four research cycles and processed through grounded theory meta-synthesis methodology. Four core variables emerged from the research: Identification of inherent DNA required for talent succession development, Quality of leadership, Effectiveness of a performance plan and Leading with heart. The driving variable within the balancing loop identified in the causal mechanism was Quality of leadership which is the initial point of influence in the system, and sets off a chain of cause and effect interactions between all the other variables, resulting in either a positive or negative stabilization within this system. This research suggests interventions and mechanisms to improve performance while simultaneously developing a future fit workforce who have the ability to focus on a number of moving parts at the same time. Efficiency is created through their competence in ensuring outstanding operational performance, the engagement and effective management of staff as well as the ability to handle constant change, complexity and uncertainty. The theory built, as well as the proposed interventions and mechanisms were tested and modified within the environment and delivered significant business results. The results achieved as a result of the implementation of the theory, are therefore concrete evidence of relevance, validity and utility. Contributions to practice, theory and research are discussed in this closing chapter of this dissertation.
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Kim, Jintae. "Multi-level design optimizations of pipelined A/D converter." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1790313751&sid=9&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Razzaghi, Alireza. "A single-channel 10b 1GS/s ADC with 2-cycle latency using pipelined cascaded folding architecture." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1566903241&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Espinosa, Lorelle L. "Pipelines and pathways women of color in STEM majors and the experiences that shape their persistence /." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=1971757771&sid=24&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Starý, Petr. "Deferred Shading." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2009. http://www.nusl.cz/ntk/nusl-236795.
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Work deals with design and implementation a tutorial for demonstration deferred shading technique and its possibilities. It explains lighting and shading principles in intuitive and interactive way. Deferred shading is a technique which determines pixel color after the geometry rasterization of the entire scene. In other words the processing of geometry does not interfere with the shading process.
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李秋樺. "FPGA implementation of pipeline Radix-4 FFT." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/48686456757959967313.
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碩士<br>中華大學<br>電機工程學系碩士班<br>92<br>The 802.11a standard is regarded as the standard of high-speed Wireless LAN in next generation, its modulation uses OFDM. IFFT/FFT processor is the key component in the implementation of OFDM system, because it performs the transformation very efficiently and provides a simply way of ensuring the carrier signals produced are orthogonal. This paper introduces Radix-4 DIF FFT algorithm ,it has the smaller numbers of multiplier then radix-2 algorithm and coordinate pipeline processing technology to meet the fast and real time processing demand. In the first chapter we discuss the principle of OFDM and introduce relation between OFDM and fast fourier transform; In second chapter we explain the paper used architecture of FFT; Third chapter mainly uses Matlab to simulation ,then we seeks the best bit length of the data and twiddle factor. In the fourth chapter we use hardware description language (Verilog) to complete circuit design of IFFT/FFT , and gives the hardware implementation by the FPGA technology
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huan, liang zhang, and 梁章桓. "The Implementation of Pipeline FFT Using Booth-Wallace Multiplier." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/56060104273061814023.
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碩士<br>中華大學<br>電機工程學系碩士班<br>94<br>Fast Fourier Transform plays an important role in many applications of digital signal processing. The purpose of this thesis is to design an efficient FFT processor. The calculation speed, number of multipliers, gate count, write, read and latency are taken into account in the design. The algorithm of Radix- 4 DIF FFT is employed, because the circuit complexity is lower than Radix-2 and the construction is simpler than Radix-8. The pipeline construction and Booth-Wallace tree multiplier are employed. We use Verilog HDL to design the circuit of the FFT processor and use Simulink blocksets, Modelsim, Xilinx blocksets, Lyrtech SignalWAVe to implement and verify the hardware. Finally, the calculation speed of the FFT processor can achieve 73.52MHz.
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蘇士傑. "Design and Implementation of Low Power Pipeline FFT Processor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/23097285062682862490.
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碩士<br>中華大學<br>電機工程學系(所)<br>94<br>The FFT processor is the key component for the OFDM systems . How to reduce the power consumption of FFT Processor has been ceaselessly attention . In this thesis , the Radix-4 DIF FFT algorithm is considered since it needs a smaller number of multipliers than the Radix-2 algorithm . Together with the pipeline and low power design , the needs for real-time and low power IFFT / FFT computation can be satisfied . Using 802 .11a standard as a sample of Raix-4 pipeline IFFT / FFT processor , hardware was implemented by the Verilog hardware description language designed on DSP/FPGA development board ( Lyrtech TMS32OC6713 / Vitex-II-Based XCZV3000 SignalWAVe］
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Zeng, Guo-Hua, and 曾國華. "FPGA Implementation of Pipeline Split-Radix(SRFFT) IFFT/FFT." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/14491161826738563376.
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碩士<br>中華大學<br>電機工程學系碩士班<br>93<br>Orthogonal Frequency Division Multiplixing (OFDM) modulation makes use of a longer symbol duration with a guard interval to reduce frequency selective fading and inter symbol interference (ISI). Multipath transmission results in frequency selective fading. In OFDM, subchannel signals with narrow frequency bandwidth will suffer amplitude attenuation only; therefore, much simpler frequency equalizers are enough to compensate the amplitude distortion, which greatly reduces the receiver complexity. In OFDM, the transmitter needs to calculate the IFFT of the input signal to generate the baseband (complex-valued) signals; and the receiver needs to calculate the FFT. If the IDFT/DFT is calculated directly, it will waste the computation resources; thus, the application of the IFFT/FFT is necessary. One of the key techniques in the OFDM system is the IFFT/FFT. The purpose of this thesis is to design an efficient OFDM IFFT/FFT processor for the system. The calculation speed, number of multipliers, gate count, write, read and latency are taken into account in design. The pipeline structure used in this design involves the real-time process of the four-path input and cascade-delay-commutator. To get the optimum realization of the factor： ( ) in the IFFT calculation , we propose to use the adaptive shift dividing concept.
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Hu, Bing-Ren, and 胡秉仁. "CPLD Design and Implementation of a Pipeline FFT Processor." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/80823302262973626608.
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碩士<br>義守大學<br>電子工程學系<br>89<br>Based on the Decimation-in-frequency method, the design of FFT pipeline VLSI architecture is proposed in this work. As compared with traditional parallel architecture, the proposed architecture has the advan-tage of reducing the computational complexity. This proposed pipeline circuit structure can input and output one data during one clock cycle, thus the execution speed would apply for the real time digital signal processing. The circuit architecture is implemented and analyzed by using Max+plusII software and is verified by altera CPLD devices.
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wang, Ken, and 王興潭. "Pipeline Radix-22 IFFT/FFT for OFDM (De)Modulation." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/21220756787821609443.
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碩士<br>中華大學<br>電機工程學系碩士班<br>90<br>IFFT/FFT processor is the key component in the implementation of wideband OFDM systems. Architectures with structured Pipeline have been used to meet the fast and real time processing demand. In this paper, introduces Radix-22 DIF FFT algorithm, it has the same multiplicative complexity as radix-4 algorithm, but retains the butterfly structure of radix-2 algorithm. The Radix-22 Single-path Delay Feedback uses simplify for pipeline implementation. The hardware circuits are verified by a Altera APEX 20K200EFC484-2X FPGA chip and the maximum frequency is 45MHz. This hardware design is to fit the OFDM systems specification.
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-WEN, CHEN HSIAO, and 陳曉雯. "Pipeline Radix-4 IFFT/FFT for OFDM (De)Modulation." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/71401809215396516029.
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碩士<br>中華大學<br>電機工程學系碩士班<br>90<br>IFFT/FFT processor is the key component in the implementation of wide-band OFDM(Orthogonal Frequency IFFT/FFT processor is the key component in the implementation of wide-band OFDM(Orthogonal Frequency Division Multiplexing,OFDM) systems because it performs the transformation very efficiently and provides a simply way of ensuring the carrier signals produced are orthogonal. In this paper, introduces Radix-4 DIF FFT algorithm,it has the smaller numbers of multiplier then radix-2 algorithm.The validity and efficiency of the architecture have been verified by Simulation in Matlab program and hardware description language VHDL.It can compute complex point forward and inverse FFT in real time with up to 43MHz sampling frequency.
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Lai, Chi-Chen, and 賴祈成. "Energy-Aware Pipeline-based Reconfigurable Mixed-Radix FFT/IFFT Processor Design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/74797731315570576077.
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碩士<br>國立交通大學<br>電子工程系所<br>94<br>In this thesis, we present a novel FFT/IFFT processor, called reconfigurable mixed-radix (RMR) FFT. It can be easily reconfigured as from 16-point to 4096-point FFT/IFFT with proper mixed-radix algorithm assigned for each mode. The proposed architecture is characterized with scalable energy dissipation for different FFT/IFFT sizes. Unlike general pipeline-based architectures which use a larger internal wordlength to achieve a high signal-to-noise ratio (SNR), our processor keeps the internal wordlength the same as the wordlength of the input data while the block-floating-point (BFP) approach is adopted to maintain the SNR. The pipeline-based architecture with 8-parallel datapath results in low computation cycles.
The simulation result shows that RMR FFT maintain the SNR above 110dB as the FFT size varies. The proposed RMR FFT processor is implemented using TSMC 0.13μm technology with a supply voltage of 1.2V. With the maximum clock rate of 110MHz, the throughput rate can reach 440Msample/s, which is 4 times of the input clock rate. The energy dissipation per FFT ranges from 4.34nJ to 5.115μJ with increasing FFT sizes.
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Neili, Chokri. "Conception et implémentation sur FPGA de structures multiplexes de la FFT en pipeline." Thèse, 2017. http://depot-e.uqtr.ca/8209/1/031873480.pdf.
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Wang, Jui-Lin, and 王瑞麟. "Circuit Sharing of OFDM and IMDCT by Modified Pipeline FFT Processor for DAB Receiver." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/cc657t.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>90<br>In this Thesis, a fast implementation algorithm for inverse modified discrete cosine transform (IMDCT), stated as a 32*64 matrix operation in the DAB receiver is adopted. Comparing to the existed fast algorithm, this fast algorithm is easy to achieve the function of circuit sharing of combining the fast Fourier transform (FFT) circuit in the orthogonal frequency division multiplexing (OFDM) with synthesis filter in the audio decoder to achieve a highly integrated, low gate count and small ROM size DAB receiver.
Verse a not circuit-sharing approach, the design here saves almost an IMDCT circuit. In addition to this, the size of memory for storing 2048-points FFT (OFDM) coefficients is further reduced from 1024 to 512 by using symmetric property of twiddle coefficient.
The design applies pipeline architecture to the butterfly unit. It consists of only one multiplier, one adder, and one subtractor. At the same time, it is capable of computing one butterfly computation every 4 cycles. Then the circuit meets the low area and high speed requirement for DAB receiver.
Finally, we implement the IMDCT and the OFDM circuit that is based on the circuit sharing method by single process element with pipeline structure for DAB receiver.
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Chen, Hung-Yen, and 陳宏彥. "The Application of Novel Parallel-Pipeline Architecture to Achieve FFT of UWB System on FPGA." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/2evzya.
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碩士<br>南台科技大學<br>電子工程系<br>96<br>Fast Fourier Transform (FFT) has been the most important functions widely used in the Multi-Band Orthogonal Frequency Division Multiplexing Ultra-Wide Band (MB-OFDM UWB) system and image compression, especially in the exponential growth of mobile and handheld devices. The higher throughput requirements for video broadcasting and wireless network will consume ever more power. Since Fast Fourier Transform algorithm was first proposed in 1965 by Cooley-Tuke and promoted the development in the areas of digital communication, the design of FFT hardware has also evolved from the pipeline to the parallel-pipeline structure. This thesis will be contributing on proposing a new parallel-pipeline structure to the Multiple-Path Delay Commutator (MDC), that will have double rate of the FFT operation, achieve 100% hardware utility rate and at the same time reduce the hardware area, and produce parallel-input and parallel-output that can be applied to the MIMO system. In addition, the new parallel structure can also be applied on more communication systems. The ultimate goal of this thesis is to use the new parallel-pipeline structure to realize a FFT mechanism that conforms to the IEEE 802.15.3a standard of high performance, high efficiency, low delay, and low power and also implementation complete circuit simulation and verification utilizing Xilinx Virtex-4-xc4vlx60 FPGA.
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Wang, Chong-Sing, and 王崇興. "Novel High Efficient and Low Power Memory Structures for Parallel-Pipeline FFT Input module Implementation." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/52032835039014825735.
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碩士<br>南台科技大學<br>電子工程系<br>98<br>Abstract More than thousands of papers have been published to discuss the FFT/IFFT designs based on the requirement of speed, chip area, and power consumption. However, the I/O module of the FFT processor has not been thoroughly investigated. The pipeline architecture is appropriate for the real-time application. Nevertheless, most of the designs employ the decimation-in-frequency (DIF) instead of decimation-in-time (DIT) FFT algorithm. Lack of an efficient input module for the DIT is the main reason. This paper will conquer the problem. A novel input data module to efficiently support the highly parallel-pipeline FFT/IFFT processors will be presented. Therefore, designers can have the alternative choice for their FFT design. Including the proposed input module, the FFT can have the linear input and linear output I/O sequences .Our proposed FFT input modules are implemented by using TSMC 0.18μm 1P6M CMOS technology with core size of 934730 and 938898 , respectively. They process the 64-point FFT with clock rates of 5MHz and 2.5MHz, and consume of 0.08mW and 0.55mW, respectively.
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Lin, Tson-Yee, and 林忠毅. "On Wordlength Optimization of Pipelined FFT Processors." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/16072366214848044171.
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碩士<br>國立交通大學<br>電子工程系<br>91<br>Despite the wide use of Fast Fourier Transform (FFT) processors in modern communication system, image and signal processing, much research is still undertaken to improve its performance. Because of the time pressure of system design, it is important to reduce design time of FFT processors through design automation. Furthermore, subject to the effect of finite wordlength in hardware, a trade-off between precision and hardware resource has to be made. Accordingly, it is a key issue to maximize the precision at the minimal cost of hardware complexity. This thesis presents a solution to automate the design flow for pipelined FFT processors that are characterized by the regularity in each stage. We can adjust the wordlength in each stage to obtain the optimization of the area or the power for specified pipelined FFT processors by using the constraints of point of FFT, signal-to-quantization-noise ratio (SQNR), and speed of processors. To decrease the design time, our flow is capable of generating automatically a timing accuracy model which can be simulated. This feature provides designers a flexible simulation environment. The experimental results indicate that this flow can reduce the area or the power of pipelined FFT processors and improve the efficiency in system design.
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WU, WEI-CHENG, and 吳緯政. "The Design of a Pipelined FFT processor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/16903734790579144212.
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碩士<br>義守大學<br>資訊工程學系碩士班<br>94<br>The purpose of this research is to design a pipeline Fast Fourier Transform Intellectual property (FFT IP).
The main works are:
1. Planning the systematic architecture.
2. Developing the IP using Verilog hardware description language.
3. Set up the testing platform and verify the FFT IP.
This research has successfully integrated the FFT IP, testing signals, VGA controller on a signal FPGA chip.
We used a static signal, i.e a waveform of know amplitude and shape, to test the accuracy of the FFT processor. Compared with previous referenced design, this project is running faster.
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Kuo, Chin-Bin, and 郭志彬. "Hybrid Wordlength Optimization Methods of Pipelined FFT Processors." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/26281229979920624302.
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碩士<br>國立交通大學<br>電機資訊學院碩士在職專班<br>93<br>The Fast Fourier Transform (FFT) processor is a key component in many communication systems. To reduce design time of FFT processors through design automation is to reduce the time pressure of system designers. When implementing a pipelined FFT processor the wordlength is of great importance. This thesis describes a statistical error model of pipelined FFT processors that calculates the signal to quantization noise ratio (SQNR) with wordlength of each process element (PE) stage. Furthermore, to speed up the design of specified FFT processor, a hybrid optimization method with statistical and simulation-based error analysis is presented. Under constraints of the number of FFT points, SQNR, and required processors speed, the optimized wordlength set for each PE stage can be generated within several seconds. The experimental results designate that this speedy flow can reduce 24% area of 8192-point pipelined FFT processors.
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曹堉棋. "Memory-Efficient Pipelined FFT Processor for OFDM Systems." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/47620698514646903439.
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Chen, Chiu-Kuo, and 陳秋國. "Design and Implementation of A Pipelined FFT Processor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/53463286965326271451.
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碩士<br>國立交通大學<br>電機學院碩士在職專班電機與控制組<br>94<br>In this thesis, a novel architecture of reducing the hardware cost to the ROM stored the twiddle factor used in a pipelined 4096-point radix-2 fast Fourier transform (FFT) /IFFT processor is presented. The proposed method mainly combines the mapping function and the lookup table. Based on this design method, the hardware complexity of the ROM stored twiddle factor only demands 682 words. Compared with the hardware complexity that demands 14337 words in theory, it is reduced up to 95.24%.
Moreover, a novel architecture of the high signal-to-noise ratio (SNR) is also presented. The adopted design method divides the output of each pipelined butterfly process unit into several sections and then separately normalizes them with different normalized bases according to the maximum corresponding to each section. Under the limitation of both twiddle factor ROMs and pipelined data paths that are adopted fixed point design with 16-bit word length, the SNR of the output of the 4096-point pipelined FFT is 76.68dB.
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Chen, Sheng-wei, and 陳聖偉. "An Efficient High Speed Double-Rate Pipelined FFT/IFFT Architecture." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/80892243900038757124.
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碩士<br>國立中興大學<br>電機工程學系<br>93<br>Abstract
Currently, the most popular WLAN products are using 802.11 a/g standards with Orthogonal Frequency Division Multiplexing (OFDM) evolved from multi-carrier transmission technology. It can provide the transmission rate up to 54Mbps.
However, the requirement of higher transmission rate is always desired. In this thesis an efficient high speed double-rate pipelined fast fourier transform / inverse fast fourier transform (FFT/IFFT) architecture with radix-2 algorithm in this thesis is proposed for OFDM communication systems in the future Gbps muti-input muti-output (MIMO) WLAN. It doubles the throughput by using dual-input architecture with the concept of “process division” to share the hardware. Furthermore, it reduces the hardware cost of double-data inputs and makes the utilization rate of pipelined multipliers and the processing elements reaching 100%. The throughput of the efficient high speed double-rate pipelined FFT/IFFT architecture is ten times of the traditional architecture for single input by higher operation frequency and efficient utilization of the hardware.
The core size of the proposed architecture is 1.21mm2 with the power consumption of 406mW at clock of 83MHz for dual-path data inputs with 16-bit word length using UMC 0.18m 1P6M CMOS technology.
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Wu, Wei-jr, and 吳韋志. "DESIGN OF LOW POWER FIXED-WIDTH MULTIPLIERS FOR PIPELINED FFT PROCESSORS." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/68675675934914597777.
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碩士<br>大同大學<br>通訊工程研究所<br>96<br>Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This thesis presents a novel approach to reduce power consumption of digital multiplier based on dynamic by passing of partial products. We present three methods for designing low power error-compensated fixed-width multipliers which keep the input and the output the same bit width. By applying the unsigned row-and-column-bypassing structure or two’s-complement row-and-column-bypassing structure or row-and-column- bypassing CSD structure, the columns and rows are passed and the switching power will be saved. The truncated part that produces the carry-out bits is replaced with several AND gates and OR gates. In other words, given two n-bit inputs, the fixed-width multipliers generate n-bit products with low product error, but use less power when compared with a standard parallel multiplier. A physical implementation of the proposed design used a standard TSMC 0.35mμ 2P4M CMOS process. Simulation results show that our two methods has 13% and 6% power reduction when supply voltage is 3.3V. We have used our methodology to design a low-power parallel multiplier for the 64-point Fast Fourier Transform processor. Simulation results show that our approach can result in significant power savings over conventional multipliers.
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Das, Ansuman DiptiSankar. "Efficient multiplier-less VLSI architectures for folded pipelined complex FFT core." Thesis, 2013. http://ethesis.nitrkl.ac.in/4911/1/211EC2077.pdf.
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Fast Fourier transform (FFT) has become ubiquitous in many engineering applications. FFT is one of the most employed blocks in many communication and signal processing systems. Efficient algorithms are being designed to improve the architecture of FFT. Higher radix FFT algorithms have the traditional advantage of using less number of computational elements and are more suitable for calculating FFT of long data sequence. Among the different proposed algorithms, the split-radix FFT has shown considerable improvement in terms of reducing hardware complexity of the architecture compared to radix-2 and radix-4 FFT algorithms. Here radix-4, radix-8, and split-radix algorithms have been used in the design of different proposed complex FFT cores. The growing popularity of adopting virtual instrumentation (modular, customizable, software-defined instrumentation) has only became possible due to the use of LabVIEW with a highly interactive process known as graphical system design. The CompactRIO programmable automation controller is an advanced embedded control and data acquisition system designed for applications that require high performance and reliability. The work explains the real-time implementation of 256-point FFT and finding the power spectrum using LabVIEW and CompactRIO. New distributed arithmetic (NEDA) is one of the most used techniques in implementing multiplier-less architectures of many digital systems. In this thesis, four architectures for different FFT cores have been proposed: • Real-time implementation of FFT using CompactRIO • 32-Point Complex FFT Core Using Split-Radix Algorithm • 64-Point Complex FFT Core Using Radix-4 Algorithm • 64-Point Complex FFT Core Using Radix-8 Algorithm The proposed designs have implemented in both FPGA as well as ASIC design flows. 180nm process technology is being used for ASIC implementation. The results show the improvements of proposed designs compared to the other existing architectures.
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JUNG-LU, CHENG, and 鄭榮錄. "Comparison and FPGA Implementation of Single/Double Rate Pipelined FFT/IFFT Architecture." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/79782159600307660910.
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碩士<br>國立中興大學<br>電機工程學系<br>93<br>In the past few years, the wireless network had already occupied a significant niche in the local area network market. It is widely adopted in both various wireless systems research and commercial WLAN product development. It is thus the key to open the new or existing systems. Currently, the major new WLAN products are followed by 802.11 a/g standards. Due to the OFDM (Orthogonal Frequency Division Multiplexing) technology, it makes the access rate up to 54Mbps. In addition, the OFDM technology can resist multi-path effects effectively. so, the OFDM technology has already been widely used in various kinds of advancement digital communication system.
This thesis utilizes the signal processing structure of OFDM technology with the radix-2 and radix-2/4/8 algorithms of FFT/IFFT to design the circuits for Single-Input-Single-Output & Dual-Input-Dual-Output, with verification by FPGA. During verification, 64 pieces of data for transmission and receiving from the standard of 802.11a were duplicated using our program to convert to hexadecimal format. These data are the input data streams. After Post-Place & Route simulations, the results were converted to be compared with the 802.11a standard. After the functional verification, the real signals were measured, through LA to verify the functions and speed.
In addition, the areas of 4 circuit structures were compared. For radix-2 algorithm, the double-rate circuit is only 1.2 times to the single-rate circuit in terms of area. Furthermore, since every stage is very similar, it is very easy to be expanded and programmable. The radix-2 circuit structure can be applied to any 2n-point FFT very easily. Even though, radix-2/4/8 utilizes the similar area, but it does not have such flexibility.
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Li, Yueh-Shu, and 李岳書. "An Efficient FFT Processor Using Pipelined Multi-radix architecture for DVB-T/H Systems." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/78862273908249244063.
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碩士<br>逢甲大學<br>電子工程所<br>97<br>Orthogonal Frequency Division Multiplexing (OFDM) technique provides an efficient way to overcome noise interference and achieve high bandwidth utilization, therefore, it has been adopted in many wireless communication systems such as worldwide interoperability for microwave access (WiMAX), digital audio broadcasting (DAB), digital video broadcasting (DVB) and etc. The Fast Fourier Transform (FFT) processor is one of the most computational components of the OFDM system. This thesis focuses on designing an efficient and variable length FFT processor for both DVB-terrestrial (DVB-T) and DVB-Handheld (DVB-H) systems.
In order to improve the performance of the FFT processor, this thesis analyzed not only the computational complexity of various FFT algorithms but also the characteristic of FFT hardware architecture. Accordingly, the novel pipeline in memory-based (PIMA) architecture which combined pipeline-based architecture with memory-based architecture is proposed. PIMA architecture owns the advantage of lower controlling complexity. Besides, the dynamic power consumption resulted from the switching activity of the SRAM is also reduced if high-radix FFT algorithm is used. Furthermore, we upgrade performance through optimizing the sub-modules of PIMA architecture in terms of using the twiddle factor generator of only 1/8 period, and adopting the simple single-port memories.
The proposed FFT processor has been designed and fabricated using TSMC 0.18μm single-poly six-metal (1P6M) CMOS process with core area of 4.49 mm2. The maximum frequency is 102 MHz, and the power dissipation is 20.5 mW when the chip is operated at 20 MHz. The energy efficiency index, i.e. the FFTs/Energy, of this design is up to 68.05, which is at least 12% higher than the state-of-the-art designs. The proposed FFT processor has been verified through the DVB model built in MATLAB simulink, and the measured signal-to-quantification-noise ratio (SQNR) and bit error rate (BER) are 43 dB and 1.1×〖10〗^(-4), respectively. These results can be proved the proposed FFT processor conforms to the requirement of DVB-T/H standard.
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Li, Miao-Shan, and 李妙善. "Low power pipelined array multiplier design using delay line controlled dynamic adders and embedded pulse triggered FFs." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/82705044381793041937.
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