Relevant bibliographies by topics / Pipeline synthesis

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Pipeline synthesis'

Author: Grafiati
Published: 7 February 2023

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Journal articles on the topic "Pipeline synthesis"

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Pienaar, Wessel. "Logistics management aspects of planning, implementing and controlling commercial petroleum pipeline operations." Corporate Ownership and Control 8, no. 1 (2010): 447–55. http://dx.doi.org/10.22495/cocv8i1c4p3.

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The purpose of the article is to identify, assess and describe the logistics aspects of the commercial operation of petroleum pipelines. A synthesis is provided of the nature of 11 logistics activities of petroleum pipeline operations. The relative modal service performance of pipeline transport, based on six measures of effectiveness, is also provided. The article identifies the segments in the petroleum-products supply chain where pipelines can play an efficient and effective role
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Wen, Kai, Jing Gong, and Yan Wu. "The Cascade Control of Natural Gas Pipeline Systems." Applied Sciences 9, no. 3 (January 30, 2019): 481. http://dx.doi.org/10.3390/app9030481.

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With the boost of natural gas consumption, an automatic gas pipeline scheduling method is required to replace the dispatchers in decision making. Since the state space model is the fundamental work of modern control theory, it is possible that the classical controller synthesis method can be used for the complicated gas pipeline controller design. In this paper, a cascade control algorithm is proposed based on the state space model that is used for the transient flow simulation of the natural gas pipelines. A linear quadratic regulator is designed following the classical optimal control theory. Finally, the transient process with different control methods shows the effectiveness of the cascade control using information of the entire pipeline. According to the hardware configuration of natural gas pipelines, automatic scheduling process is ready to deploy as one step to the intelligent natural gas pipelines.
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Meher, Pramod, and Sang Park. "Design of Cascaded CORDIC Based on Precise Analysis of Critical Path." Electronics 8, no. 4 (March 29, 2019): 382. http://dx.doi.org/10.3390/electronics8040382.

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A conventional coordinate rotation digital computer (CORDIC) has a low throughput rate due to its recursive implementation of micro-rotations. On the contrary, a fully-pipelined cascaded CORDIC provides a very high throughput rate at the cost of high complexity and large area. In this paper, possible design choices of cascaded CORDIC are explored over a wide range of operating frequencies, throughput rates, latency, and area complexity. For this purpose, we present a fine-grained critical path analysis of the cascaded CORDIC in terms of bit-level delay. Based on the propagation delay estimate, we propose an algorithm for determining the required number of pipeline stages and locations of the pipeline registers in order to meet the time constraint in a particular application. A hybrid cascaded-recursive CORDIC is also proposed to increase the throughput rate, and to reduce the latency and energy per sample (EPS). From synthesis results, we show that the proposed pipelined cascaded CORDIC with only four pipeline stages requires 31.1% less area and 29.0% less EPS compared to a fully-pipelined CORDIC. An eight stage pipelined recursive cascaded CORDIC provides 18.3% less EPS and 40.4% less area-delay product than a conventional CORDIC.
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Hwang, C. T., Y. C. Hsu, and Y. L. Lin. "PLS: a scheduler for pipeline synthesis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12, no. 9 (1993): 1279–86. http://dx.doi.org/10.1109/43.240075.

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Eminov, R. A., and E. I. Huseynli. "GENERAL CONCEPT FOR DEVELOPMENT OF UNIVERSAL LASER SCANNERS FOR CONSTRUCTION AND EXPLOITATION OF MAIN GAS PIPELINES." Kontrol'. Diagnostika, no. 254 (2019): 54–59. http://dx.doi.org/10.14489/td.2019.08.pp.054-059.

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The article is devoted on development of general concept for development of diagnostic-geodesy laser scanners useful for both the geodesy support of construction and exploitation of main gas pipelines. The carried out review of existing works on such an extension of functional capabilities of laser scanners in direction of combination of geodesy and diagnostic functions of laser at the stages of construction and exploitation of gas pipelines shown absence of any works in such direction. The possibility of technical realization of such extension of functions of laser scanner are considered. The general task on development of laser scanners operating in infrared band for construction and exploitation of gas pipelines is formulated. Optimization of functioning regime of laser scanner working in regime of detection of gas leaks in main gas pipelines is carried out. Synthesis of specialized laser scanner capable to realize functions of geodesy laser scanner during pipeline construction and functions of diagnostics that is detection of gas leaks in stage of pipeline exploitation is carried out. It is shown that technical realization of calculated optimum interrelation between main functional parameters of the system can be realized during serial measurements by organization of adaptive control of laser beam power depending on distance between measuring instrument and gas pipeline. At the same time the system should be equipped by laser distance meter included into gas leak detection system operating in adaptive regime.
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Dai, Jian-Bo, Gui-Di Zhang, Cheng-Tao Hu, and Kai-Kai Cheng. "Study on Synthesis Method of Multipoint Seismic Waves for Buried Oil and Gas Pipeline in Shaking Table Tests." Shock and Vibration 2021 (July 31, 2021): 1–8. http://dx.doi.org/10.1155/2021/4624871.

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The buried oil and gas pipeline is a linear structure with infinite length. In the shaking table test of its seismic response, it is necessary to input the spatially related multipoint seismic wave considering the propagation characteristics of ground motion. The multipoint seismic excitation shaking table tests and loading scheme of buried oil and gas pipelines are designed and formulated. The synthesis method of spatial correlation multipoint seismic wave for the buried oil and gas pipeline test is proposed in this study. The values of relevant parameters are analyzed, and corresponding program is compiled by MATLAB. The results show that the developed multipoint excitation shaking table seismic wave input scheme is reasonable. At the same time, the synthesized multipoint seismic wave based on the actual seismic record and artificial random simulation seismic wave can meet the test requirements, which suggests the testing effect is good.
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Tararychkin, I. A. "Protection of Transport Nodes and Resistibility of Pipeline Systems." World of Transport and Transportation 17, no. 2 (September 13, 2019): 218–29. http://dx.doi.org/10.30932/1992-3252-2019-17-2-218-229.

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The analysis has been carried out and the laws of occurrence of emergency threats at pipeline transport facilities associated with the sequential damage of structural elements have been established. When an emergency situation develops, blocking of a separate system node is associated with simultaneous transition to a state of inoperability of all pipelines converging into the zone of that node. Such damage to the point element of the network structure prevents product flows from passing through that point. The ability of a system to withstand a progressive blocking depends on its composition, structure, and is characterized by an indicator of persistence, the value of which is calculated using a simulation method. An example of the use of cluster schemes in solving the problem of structural synthesis and the selection of the best protection option for a pipeline transport system has been considered.
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Kim, Jong Tae, Fadi J. Kurdahi, and Noh Byung Park. "System-level Time-stationary Control Synthesis for Pipelined Data Paths." VLSI Design 9, no. 2 (January 1, 1999): 159–80. http://dx.doi.org/10.1155/1999/49179.

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We address the prblem of time-stationary control synthesis for pipelined data paths. Control synthesis system accepts scheduled control data flow graph with conditional branches which are produced by high level synthesis tools such as Sehwa [1] as input specification and generates a FSM controller. First a scheduled control/data flow graph is analyzed and the various states are identified. Overlapped states are grouped together to produce L groups where L is the pipeline latency. Next, state transitions are identified and a state table is generated. Finally, a highly optimized FSM controller is implemented by performing horizontal partitioning and the corresponding stae encoding so as to minimize the total controller area. We compared our approach to published work on FSM generation and optimization and the results indicate that our method results in large savings in total controller area.
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Badillo-Olvera, A., A. Pérez-González, O. Begovich, and J. Ruíz-León. "Burst detection and localization in water pipelines based on an extended differential evolution algorithm." Journal of Hydroinformatics 21, no. 4 (April 1, 2019): 593–606. http://dx.doi.org/10.2166/hydro.2019.123.

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Abstract This paper presents a new burst detection and location technique for pressurized pipelines based on an extension of the Differential Evolution (DE) algorithm. The proposed approach addresses the burst location problem as an optimization task, by considering the dynamic model that describes the behavior of a fluid through a pipeline and the presence of fluid losses produced by a burst. The optimization problem relies on finding suitable estimations related to the burst parameters, i.e. magnitude, pressure and position of a burst, while a defined cost function is minimized. In order to deal with this problem, three strategies are proposed to extend and adapt the DE algorithm: (i) an informed definition of the physical restrictions of the problem according to the pipeline characteristics; (ii) a training stage of the algorithm that allows to find the appropriate synthesis parameters; (iii) a multi-start structure, in order to track dynamical variations of the problem. Experiments on a pipeline prototype illustrate the results obtained by the proposed algorithm on the estimation of the burst parameters, comparing its performance with an algorithm based on the Extended Kalman Filter, which is widely used in the literature.
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Todd-Brown, Katherine E. O., Rose Z. Abramoff, Jeffrey Beem-Miller, Hava K. Blair, Stevan Earl, Kristen J. Frederick, Daniel R. Fuka, et al. "Reviews and syntheses: The promise of big diverse soil data, moving current practices towards future potential." Biogeosciences 19, no. 14 (July 28, 2022): 3505–22. http://dx.doi.org/10.5194/bg-19-3505-2022.

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Abstract. In the age of big data, soil data are more available and richer than ever, but – outside of a few large soil survey resources – they remain largely unusable for informing soil management and understanding Earth system processes beyond the original study. Data science has promised a fully reusable research pipeline where data from past studies are used to contextualize new findings and reanalyzed for new insight. Yet synthesis projects encounter challenges at all steps of the data reuse pipeline, including unavailable data, labor-intensive transcription of datasets, incomplete metadata, and a lack of communication between collaborators. Here, using insights from a diversity of soil, data, and climate scientists, we summarize current practices in soil data synthesis across all stages of database creation: availability, input, harmonization, curation, and publication. We then suggest new soil-focused semantic tools to improve existing data pipelines, such as ontologies, vocabulary lists, and community practices. Our goal is to provide the soil data community with an overview of current practices in soil data and where we need to go to fully leverage big data to solve soil problems in the next century.
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Dissertations / Theses on the topic "Pipeline synthesis"

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Oreifej, Rashad. "SYNTHESIS OF SELF-RESETTING STAGE LOGIC PIPELINES." Master's thesis, University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3572.

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As designers began to pack multi-million transistors onto a single chip, their reliance on a global clocking signal to orchestrate the operations of the chip has started to face almost insurmountable difficulties. As a result, designers started to explore clockless circuits to avoid the global clocking problem. Recently, self-resetting circuits implemented in dynamic logic families have been proposed as viable clockless alternatives. While these circuits can produce excellent performances, they display serious limitations in terms of area cost and power consumption. A middle-of-the-road alternative, which can provide a good performance and avoid the limitations seen in dynamic self-resetting circuits, would be to implement self-resetting behavior in static circuits. This alternative has been introduced recently as Self-Resetting Stage Logic and used to propose three types of clockless pipelines. Experimental studies show that these pipelines have the potential to produce high throughputs with a minimum area overhead if a suitable synthesis methodology is available. This thesis proposes a novel synthesis methodology to design and verify clockless pipelines implemented in SRSL by taking advantage of the maturity of current CAD tools. This methodology formulates the synthesis problem as a combinatorial analytical problem for which a run-time efficient exact solution is difficult to derive. Consequently, a two-phase algorithm is proposed to synthesize these pipelines from gate netlists subject to user-specified constraints. The first phase is a heuristic based on the as-soon-as-possible scheduling strategy in which each gate of the netlist is assigned to a single pipeline stage without violating the period constraint of each pipeline stage. On the other hand, the second phase consists of a heuristic, based on the Kernighan-Lin partitioning strategy, to minimize the number of nets crossing each pair of adjacent pipeline stages. The objective of this optimization is to reduce the number of latches separating pipeline stages since these latches tend to occupy large areas. Experiments conducted on a prototype of the synthesis algorithm reveal that these self-resetting stage logic pipelines can easily reach throughputs higher than 1 GHz. Furthermore, these experiments reveal that the area overhead needed to implement the self-resetting circuitry of these pipelines can be easily amortized over the area of the logic embedded in the pipeline stages. In the overall, the synthesis methods developed for SRSL produce low area overhead pipelines for wide and deep gate netlists while it tends to produce high throughput pipelines for wide and shallow gate netlists. This shows that these pipelines are mostly suitable for coarse-grain datapaths.
M.S.Cp.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Engineering
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DASASATHYAN, SRINIVASAN. "SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529.

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Nicklous, Francis Edward. "The Design, Simulation and Synthesis of Pipelined Floating-Point Radix-4 Fast Fourier Transform Data Path in VHDL." Master's thesis, Temple University Libraries, 2010. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/96963.

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Electrical Engineering
M.S.E.
The Fast Fourier Transform (FFT) converts time or spatial information into the frequency domain. The FFT is one of the most widely used digital signal processing (DSP) algorithms. DSPs are used in a number of applications from communication and controls to speech and image processing. DSPs have also found their way into toys, music synthesizers and in most digital instruments. Many applications have relied on Digital Signal Processors and Application Specific Integrated Circuits (ASIC) for most of the signal processing needs. DSPs provide an adequate means of performance and efficiency for many applications as well as robust tools to ease the development process. However, the requirements of important emerging DSP applications have begun to exceed the capabilities of DSPs. With this in mind, system developers have begun to consider alternatives such as ASICs and Field Programmable Gate Arrays (FPGA). Although ASICs can provide excellent performance and efficiency, the time, cost and risk associated with the design of ASICs is leading developers towards FPGAs. A number of significant advances in FPGA technology have improved the suitability of FPGAs for DSP applications. These advances include increased device capacity and speed, DSP-oriented architectural enhancements, better DSP-oriented tools, and increasing availability of DSP-oriented IP libraries. The thesis research focuses on the design of a single precision floating-point radix-4 FFT FPGA using VHDL for real time DSP applications. The paper will go into further detail pertaining to the FFT algorithm used, the description of the design steps taken as well as the results from both simulation and synthesis.
Temple University--Theses
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Hao, Kecheng. "Equivalence Checking for High-Assurance Behavioral Synthesis." PDXScholar, 2013. https://pdxscholar.library.pdx.edu/open_access_etds/1066.

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The rapidly increasing complexities of hardware designs are forcing design methodologies and tools to move to the Electronic System Level (ESL), a higher abstraction level with better productivity than the state-of-the-art Register Transfer Level (RTL). Behavioral synthesis, which automatically synthesizes ESL behavioral specifications to RTL implementations, plays a central role in this transition. However, since behavioral synthesis is a complex and error-prone translation process, the lack of designers' confidence in its correctness becomes a major barrier to its wide adoption. Therefore, techniques for establishing equivalence between an ESL specification and its synthesized RTL implementation are critical to bring behavioral synthesis into practice. The major research challenge to equivalence checking for behavioral synthesis is the significant semantic gap between ESL and RTL. The semantics of ESL involve untimed, sequential execution; however, the semantics of RTL involve timed, concurrent execution. We propose a sequential equivalence checking (SEC) framework for certifying a behavioral synthesis flow, which exploits information on successive intermediate design representations produced by the synthesis flow to bridge the semantic gap. In particular, the intermediate design representation after scheduling and pipelining transformations permits effective correspondence of internal operations between this design representation and the synthesized RTL implementation, enabling scalable, compositional equivalence checking. Certifications of loop and function pipelining transformations are possible by a combination of theorem proving and SEC through exploiting pipeline generation information from the synthesis flow (e.g., the iteration interval of a generated pipeline). The complexity brought by bubbles in function pipelines is creatively reduced by symbolically encoding all possible bubble insertions in one pipelined design representation. The result of this dissertation is a robust, practical, and scalable framework for certifying RTL designs synthesized from ESL specifications. We have validated the robustness, practicality, and scalability of our approach on industrial-scale ESL designs that result in tens of thousands of lines of RTL implementations.
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Sun, Hua. "Throughput constrained and area optimized dataflow synthesis for FPGAS." Diss., CLICK HERE for online access, 2008. http://contentdm.lib.byu.edu/ETD/image/etd2276.pdf.

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Morvan, Antoine. "Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées." Phd thesis, École normale supérieure de Cachan - ENS Cachan, 2013. http://tel.archives-ouvertes.fr/tel-00913692.

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Grâce aux progrès réalisés dans le domaine des semi-conducteurs, les plateformes matérielles embarquées sont capables de satisfaire les contraintes de performances d'applications de plus en plus complexes. Cette augmentation conduit à une explosion des coûts de conception, ce qui pousse les concepteurs de ces plateformes à utiliser des outils travaillant à des niveaux d'abstraction plus élevés. Aujourd'hui, les outils de synthèse de haut niveau opèrent sur des descriptions C/C++ pour en générer des accélérateurs matériels spécialisés. Ces outils offrent des gains en productivité significatifs par rapport à la génération précédente, qui opérait sur des descriptions structurelles de l'architecture en VHDL ou Verilog. Ces descriptions algorithmiques doivent être retravaillées pour que les outils puissent générer des circuits performants. Pour faciliter cette tâche, une solution consiste à mettre en œuvre une boite à outils pour des transformations source-à-source orientées synthèse de haut niveau. En particulier, cette thèse s'intéresse aux transformations de boucles, avec pour objectif d'améliorer les performances en exposant des boucles parallèles et en améliorant la localité des accès mémoire. En nous appuyant sur une représentation des boucles dans le modèle polyédrique, nous proposons une approche qui améliore l'applicabilité du pipeline de nids de boucles en vérifiant sa légalité de manière plus précise que les approches existantes. De plus, lorsque la vérification échoue, nous proposons une technique de correction qui insère statiquement des états d'attente pour assurer la légalité du pipeline. Enfin, ce pipeline est mis en œuvre en utilisant une technique de génération de code qui met les nids de boucles à plat. Ces contributions ont été implémentées dans l'infrastructure de compilation source-à-source Gecos, avant d'être appliquées à un ensemble de benchmarks représentatifs des noyaux de calculs cibles de la synthèse de haut niveau. Les résultats montrent un gain en performances significatif, avec un surcoût en surface modéré.
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Parrot, Rémi. "Réseaux de Petri temporisés pour la synthèse de circuits pipelinés." Thesis, Ecole centrale de Nantes, 2022. http://www.theses.fr/2022ECDN0048.

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Dans cette thèse, nous nous intéressons à l’optimisation des ressources consommées par un circuit implémentant une loi de commande pour la charge de véhicules électriques sur FPGA. Tout d’abord, nous proposons une nouvelle solution au problème de la synthèse de pipeline minimisant les bascules et garantissant une fréquence minimale de fonctionnement. En se basant sur cette même approche, nous sommes capable de construire un pipeline permettant le pliage (ou multiplexage temporel) du circuit, c’est-à-dire qui permet la fusion de portions du circuit identiques en séquençant leur accès. Ainsi, les ressources consommées sont réduites à la fois en nombre de bascule et en nombre d’unités logiques. Notre approche est basée sur un modèle de Réseau de Petri Temporisé avec des transitions retardables, pouvant rater leur date de tir, et une action spécifique appelée reset qui réinitialise les horloges de toutes les transitions. Ce modèle s’avère équivalent à un automate à une horloge. Une surclasse de ce modèle, les Réseaux de Petri Temporisés avec transitions retardables (sans reset), s’avère être incomparable, en terme d’expressivité en sémantique faible, avec les classes de Réseaux de Petri Temporels ou Temporisés en temps dense ou discret. Enfin, une exploration symbolique de ce modèle ainsi que des résultats de complexité théorique et pratique sont étudiés
In this thesis, we are interested in the optimization of the resources consumed by a circuit implementing a control law for the charging of electric vehicles on FPGA. First, we propose a new solution to the pipeline synthesis problem that minimizes the number of flip-flops and guarantees a minimum operating frequency. Based on this same approach, we are able to build a pipeline that allows the folding (or time multiplexing) of the circuit, i.e., that allows the merging of identical circuit portions by sequencing their access. Thus, the consumed resources are reduced both in number of flip-flops and in number of logical units. Our approach is based on a Timed Petri Net model with delayable transitions that can miss their firing date, and a specific action called reset that resets the clocks of all transitions. This model is shown to be equivalent to a one-clock automaton. An overclass of this model, the Timed Petri Nets with delayable transitions (without reset), turns out tobe incomparable, in terms of expressivity in weak semantics, with the classes of Temporal or Timed Petri nets in dense or discrete time. Finally, a symbolic exploration of this model and results on theoretical and practical complexity are studied
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Rahmouni, Maher. "Ordonnancement et optimisations pour la synthèse de haut niveau des circuits de controle." Grenoble INPG, 1997. http://www.theses.fr/1997INPG0028.

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La plupart des algorithmes d'ordonnancement existants dans le domaine de la synthese de haut niveau sont concus pour des applications dominees par les donnees telles que les applications de traitement de signal. Ces algorithmes ont pour objectif de minimiser le cout de la partie operative. Cependant, dans les circuits de commande modernes, les performances de la partie controle dominent la performance globale du circuit. Il est donc necessaire de prendre en compte les caracteristiques de ces applications et de developper un ensemble de techniques qui permettent de minimiser le cout de la partie controle. Cette these presente de nouvelles techniques d'ordonnancement pour differentes architectures de controleur ainsi qu'une etude sur l'interpretation des structures du langage vhdl par la synthese de haut niveau. Les approches developpees se concentrent sur l'optimisation de la surface du controleur et de la performance du circuit. Le principe de ces techniques est d'analyser les differents chemins d'execution de la description comportementale du circuit representee sous forme d'un graphe de flot de controle. Les algorithmes realises ont ete integres dans l'outil de synthese de haut niveau amical. Les resultats montrent leur efficacite sur des exemples reels de circuits domines par le controle.
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Gopalan, Ranganath. "Leakage power driven behavioral synthesis of pipelined asics." [Tampa, Fla.] : University of South Florida, 2005. http://purl.fcla.edu/fcla/etd/SFE0001064.

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Hinrichsen, Holger. "Ein transformativer Ansatz für die Synthese und Verifikation algorithmischer Hardwarebeschreibungen." [S.l. : s.n.], 2000. http://deposit.ddb.de/cgi-bin/dokserv?idn=962731447.

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Books on the topic "Pipeline synthesis"

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Tamás, Visegrády, and Jankovits István, eds. High level synthesis of pipelined datapaths. Chichester, [England]: Wiley, 2001.

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Ruiz-Amaya, Jesus. Device-level modeling and synthesis of high-performance pipeline ADCs. New York: Springer, 2011.

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Ruiz-Amaya, Jesús, Manuel Delgado-Restituto, and Ángel Rodríguez-Vázquez. Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8846-1.

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Fuels, United States Congress House Committee on Energy and Commerce Subcommittee on Fossil and Synthetic. Pipeline safety authorization: Hearing before the Subcommittee on Fossil and Synthetic Fuels of the Committee on Energy and Commerce, House of Representatives, Ninety-ninth Congress, first session, April 16, 1985-. Washington: U.S. G.P.O., 1985.

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United States. Congress. House. Committee on Energy and Commerce. Subcommittee on Fossil and Synthetic Fuels. Pipeline safety authorization: Hearing before the Subcommittee on Fossil and Synthetic Fuels of the Committee on Energy and Commerce, House of Representatives, Ninety-ninth Congress, first session, April 16, 1985. Washington: U.S. G.P.O., 1985.

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Fuels, United States Congress House Committee on Energy and Commerce Subcommittee on Fossil and Synthetic. Pipeline safety: Hearing before the Subcommittee on Fossil and Synthetic Fuels of the Committee on Energy and Commerce, House of Representatives, Ninety-ninth Congress, second session, on H.R. 4426 ... March 18, 1986. Washington: U.S. G.P.O., 1986.

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United States. Congress. House. Committee on Energy and Commerce. Subcommittee on Fossil and Synthetic Fuels. Pipeline safety: Hearing before the Subcommittee on Fossil and Synthetic Fuels of the Committee on Energy and Commerce, House of Representatives, Ninety-ninth Congress, second session, on H.R. 4426 ... March 18, 1986. Washington: U.S. G.P.O., 1986.

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United States. Congress. House. Committee on Energy and Commerce. Subcommittee on Fossil and Synthetic Fuels. FERC contract carriage proposal: Hearings before the Subcommittee on Fossil and Synthetic Fuels of the Committee on Energy and Commerce, House of Representatives, Ninety-ninth Congress, first session, June 27, November 13 and 14, 1985. Washington: U.S. G.P.O., 1986.

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Péter Arató, Tamás Visegrády, and István Jankovits. High Level Synthesis of Pipelined Datapaths. Wiley, 2001.

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Delgado-Restituto, Manuel, Ángel Rodríguez-Vázquez, and Jesús Ruiz-Amaya. Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs. Springer, 2014.

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Book chapters on the topic "Pipeline synthesis"

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Possignolo, Rafael T., Elnaz Ebrahimi, Haven Skinner, and Jose Renau. "Automated Pipeline Transformations with Fluid Pipelines." In Advanced Logic Synthesis, 125–50. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-67295-3_6.

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Huang, Shuai, and Houtao Deng. "Synthesis Architecture & Pipeline." In Data Analytics, 219–46. First edition. | Boca Raton : CRC Press, 2021.: Chapman and Hall/CRC, 2021. http://dx.doi.org/10.1201/9781003102656-ch10.

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Weinhardt, Markus. "Portable pipeline synthesis for FCCMs." In Lecture Notes in Computer Science, 1–13. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-61730-2_1.

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Ruiz-Amaya, Jesús, Manuel Delgado-Restituto, and Ángel Rodríguez-Vázquez. "Pipeline ADC Overview." In Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, 1–28. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8846-1_1.

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Ruiz-Amaya, Jesús, Manuel Delgado-Restituto, and Ángel Rodríguez-Vázquez. "Pipeline ADC Electrical-Level Synthesis Tool." In Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, 39–64. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8846-1_3.

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Ruiz-Amaya, Jesús, Manuel Delgado-Restituto, and Ángel Rodríguez-Vázquez. "Design Methodologies for Pipeline ADCs." In Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, 29–37. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8846-1_2.

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Ruiz-Amaya, Jesús, Manuel Delgado-Restituto, and Ángel Rodríguez-Vázquez. "Behavioural Modelling of Pipeline ADCs." In Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, 65–103. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8846-1_4.

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Childers, Bruce R., and Jack W. Davidson. "A design environment for counterflow pipeline synthesis." In Lecture Notes in Computer Science, 223–34. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0057793.

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Christiansen, Henning, Christian Theil Have, Ole Torp Lassen, and Matthieu Petit. "A Declarative Pipeline Language for Complex Data Analysis." In Logic-Based Program Synthesis and Transformation, 17–34. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38197-3_3.

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Hagn, Korbinian, and Oliver Grau. "Optimized Data Synthesis for DNN Training and Validation by Sensor Artifact Simulation." In Deep Neural Networks and Data for Automated Driving, 127–47. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-01233-4_4.

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Abstract:
AbstractSynthetic, i.e., computer-generated imagery (CGI) data is a key component for training and validating deep-learning-based perceptive functions due to its ability to simulate rare cases, avoidance of privacy issues, and generation of pixel-accurate ground truth data. Today, physical-based rendering (PBR) engines simulate already a wealth of realistic optical effects but are mainly focused on the human perception system. Whereas the perceptive functions require realistic images modeled with sensor artifacts as close as possible toward the sensor, the training data has been recorded. This chapter proposes a way to improve the data synthesis process by application of realistic sensor artifacts. To do this, one has to overcome the domain distance between real-world imagery and the synthetic imagery. Therefore, we propose a measure which captures the generalization distance of two distinct datasets which have been trained on the same model. With this measure the data synthesis pipeline can be improved to produce realistic sensor-simulated images which are closer to the real-world domain. The proposed measure is based on the Wasserstein distance (earth mover’s distance, EMD) over the performance metric mean intersection-over-union (mIoU) on a per-image basis, comparing synthetic and real datasets using deep neural networks (DNNs) for semantic segmentation. This measure is subsequently used to match the characteristic of a real-world camera for the image synthesis pipeline which considers realistic sensor noise and lens artifacts. Comparing the measure with the well-established Fréchet inception distance (FID) on real and artificial datasets demonstrates the ability to interpret the generalization distance which is inherent asymmetric and more informative than just a simple distance measure. Furthermore, we use the metric as an optimization criterion to adapt a synthetic dataset to a real dataset, decreasing the EMD distance between a synthetic and the Cityscapes dataset from 32.67 to 27.48 and increasing the mIoU of our test algorithm () from 40.36 to $$47.63\%$$ 47.63 % .
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Conference papers on the topic "Pipeline synthesis"

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Oreifej, Rashad, Abdelhalim Alsharqawi, and Abdel Ejnioui. "Pipeline synthesis of SRSL circuits." In 2005 12th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2005). IEEE, 2005. http://dx.doi.org/10.1109/icecs.2005.4633512.

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Fusiello, A., and L. Irsara. "An Uncalibrated View-Synthesis Pipeline." In 14th International Conference on Image Analysis and Processing (ICIAP 2007). IEEE, 2007. http://dx.doi.org/10.1109/iciap.2007.4362844.

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Ruiz-Amaya, Jesus, Manuel Delgado-Restituto, and Angel Rodriguez-Vazquez. "Electrical-level synthesis of pipeline ADCs." In APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2008. http://dx.doi.org/10.1109/apccas.2008.4746348.

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Trost, Andrej, and Andrej Zemva. "Pipeline circuit synthesis from Python code." In 2017 6th Mediterranean Conference on Embedded Computing (MECO). IEEE, 2017. http://dx.doi.org/10.1109/meco.2017.7977227.

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Zhang, Zhiru, and Bin Liu. "SDC-based modulo scheduling for pipeline synthesis." In 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2013. http://dx.doi.org/10.1109/iccad.2013.6691121.

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Tan, Mingxing, Bin Liu, Steve Dai, and Zhiru Zhang. "Multithreaded pipeline synthesis for data-parallel kernels." In 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2014. http://dx.doi.org/10.1109/iccad.2014.7001431.

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Vandame, Benoit, Neus Sabater, Guillaume Boisson, Didier Doyen, Valerie Allie, Frederic Babon, Remy Gendrot, Tristan Langlois, and Arno Schubert. "Pipeline for Real-Time Video View Synthesis." In 2020 IEEE International Conference on Multimedia & Expo Workshops (ICMEW). IEEE, 2020. http://dx.doi.org/10.1109/icmew46912.2020.9105988.

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Wirthlin, Michael, and Welson Sun. "DSynth: A Pipeline Synthesis Environment for FPGAs." In 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. IEEE, 2006. http://dx.doi.org/10.1109/fccm.2006.37.

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Baioco, J. S., D. C. S. Coutinho, C. H. Albrecht, B. S. L. P. de Lima, B. P. Jacob, D. M. Rocha, and C. O. Cardoso. "SYNTHESIS AND OPTIMIZATION OF SUBMARINE PIPELINE ROUTES." In 10th World Congress on Computational Mechanics. São Paulo: Editora Edgard Blücher, 2014. http://dx.doi.org/10.5151/meceng-wccm2012-19493.

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Nurvitadhi, Eriko, James C. Hoe, Shih-Lien L. Lu, and Timothy Kam. "Automatic multithreaded pipeline synthesis from transactional datapath specifications." In the 47th Design Automation Conference. New York, New York, USA: ACM Press, 2010. http://dx.doi.org/10.1145/1837274.1837356.

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