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Oreifej, Rashad. "SYNTHESIS OF SELF-RESETTING STAGE LOGIC PIPELINES." Master's thesis, University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3572.
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As designers began to pack multi-million transistors onto a single chip, their reliance on a global clocking signal to orchestrate the operations of the chip has started to face almost insurmountable difficulties. As a result, designers started to explore clockless circuits to avoid the global clocking problem. Recently, self-resetting circuits implemented in dynamic logic families have been proposed as viable clockless alternatives. While these circuits can produce excellent performances, they display serious limitations in terms of area cost and power consumption. A middle-of-the-road alternative, which can provide a good performance and avoid the limitations seen in dynamic self-resetting circuits, would be to implement self-resetting behavior in static circuits. This alternative has been introduced recently as Self-Resetting Stage Logic and used to propose three types of clockless pipelines. Experimental studies show that these pipelines have the potential to produce high throughputs with a minimum area overhead if a suitable synthesis methodology is available. This thesis proposes a novel synthesis methodology to design and verify clockless pipelines implemented in SRSL by taking advantage of the maturity of current CAD tools. This methodology formulates the synthesis problem as a combinatorial analytical problem for which a run-time efficient exact solution is difficult to derive. Consequently, a two-phase algorithm is proposed to synthesize these pipelines from gate netlists subject to user-specified constraints. The first phase is a heuristic based on the as-soon-as-possible scheduling strategy in which each gate of the netlist is assigned to a single pipeline stage without violating the period constraint of each pipeline stage. On the other hand, the second phase consists of a heuristic, based on the Kernighan-Lin partitioning strategy, to minimize the number of nets crossing each pair of adjacent pipeline stages. The objective of this optimization is to reduce the number of latches separating pipeline stages since these latches tend to occupy large areas. Experiments conducted on a prototype of the synthesis algorithm reveal that these self-resetting stage logic pipelines can easily reach throughputs higher than 1 GHz. Furthermore, these experiments reveal that the area overhead needed to implement the self-resetting circuitry of these pipelines can be easily amortized over the area of the logic embedded in the pipeline stages. In the overall, the synthesis methods developed for SRSL produce low area overhead pipelines for wide and deep gate netlists while it tends to produce high throughput pipelines for wide and shallow gate netlists. This shows that these pipelines are mostly suitable for coarse-grain datapaths.M.S.Cp.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Engineering
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DASASATHYAN, SRINIVASAN. "SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529.
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Nicklous, Francis Edward. "The Design, Simulation and Synthesis of Pipelined Floating-Point Radix-4 Fast Fourier Transform Data Path in VHDL." Master's thesis, Temple University Libraries, 2010. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/96963.
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Electrical EngineeringM.S.E.
The Fast Fourier Transform (FFT) converts time or spatial information into the frequency domain. The FFT is one of the most widely used digital signal processing (DSP) algorithms. DSPs are used in a number of applications from communication and controls to speech and image processing. DSPs have also found their way into toys, music synthesizers and in most digital instruments. Many applications have relied on Digital Signal Processors and Application Specific Integrated Circuits (ASIC) for most of the signal processing needs. DSPs provide an adequate means of performance and efficiency for many applications as well as robust tools to ease the development process. However, the requirements of important emerging DSP applications have begun to exceed the capabilities of DSPs. With this in mind, system developers have begun to consider alternatives such as ASICs and Field Programmable Gate Arrays (FPGA). Although ASICs can provide excellent performance and efficiency, the time, cost and risk associated with the design of ASICs is leading developers towards FPGAs. A number of significant advances in FPGA technology have improved the suitability of FPGAs for DSP applications. These advances include increased device capacity and speed, DSP-oriented architectural enhancements, better DSP-oriented tools, and increasing availability of DSP-oriented IP libraries. The thesis research focuses on the design of a single precision floating-point radix-4 FFT FPGA using VHDL for real time DSP applications. The paper will go into further detail pertaining to the FFT algorithm used, the description of the design steps taken as well as the results from both simulation and synthesis.
Temple University--Theses
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Hao, Kecheng. "Equivalence Checking for High-Assurance Behavioral Synthesis." PDXScholar, 2013. https://pdxscholar.library.pdx.edu/open_access_etds/1066.
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The rapidly increasing complexities of hardware designs are forcing design methodologies and tools to move to the Electronic System Level (ESL), a higher abstraction level with better productivity than the state-of-the-art Register Transfer Level (RTL). Behavioral synthesis, which automatically synthesizes ESL behavioral specifications to RTL implementations, plays a central role in this transition. However, since behavioral synthesis is a complex and error-prone translation process, the lack of designers' confidence in its correctness becomes a major barrier to its wide adoption. Therefore, techniques for establishing equivalence between an ESL specification and its synthesized RTL implementation are critical to bring behavioral synthesis into practice.
The major research challenge to equivalence checking for behavioral synthesis is the significant semantic gap between ESL and RTL. The semantics of ESL involve untimed, sequential execution; however, the semantics of RTL involve timed, concurrent execution. We propose a sequential equivalence checking (SEC) framework for certifying a behavioral synthesis flow, which exploits information on successive intermediate design representations produced by the synthesis flow to bridge the semantic gap. In particular, the intermediate design representation after scheduling and pipelining transformations permits effective correspondence of internal operations between this design representation and the synthesized RTL implementation, enabling scalable, compositional equivalence checking. Certifications of loop and function pipelining transformations are possible by a combination of theorem proving and SEC through exploiting pipeline generation information from the synthesis flow (e.g., the iteration interval of a generated pipeline). The complexity brought by bubbles in function pipelines is creatively reduced by symbolically encoding all possible bubble insertions in one pipelined design representation. The result of this dissertation is a robust, practical, and scalable framework for certifying RTL designs synthesized from ESL specifications. We have validated the robustness, practicality, and scalability of our approach on industrial-scale ESL designs that result in tens of thousands of lines of RTL implementations.
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Sun, Hua. "Throughput constrained and area optimized dataflow synthesis for FPGAS." Diss., CLICK HERE for online access, 2008. http://contentdm.lib.byu.edu/ETD/image/etd2276.pdf.
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Morvan, Antoine. "Utilisation du modèle polyédrique pour la synthèse d'architectures pipelinées." Phd thesis, École normale supérieure de Cachan - ENS Cachan, 2013. http://tel.archives-ouvertes.fr/tel-00913692.
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Grâce aux progrès réalisés dans le domaine des semi-conducteurs, les plateformes matérielles embarquées sont capables de satisfaire les contraintes de performances d'applications de plus en plus complexes. Cette augmentation conduit à une explosion des coûts de conception, ce qui pousse les concepteurs de ces plateformes à utiliser des outils travaillant à des niveaux d'abstraction plus élevés. Aujourd'hui, les outils de synthèse de haut niveau opèrent sur des descriptions C/C++ pour en générer des accélérateurs matériels spécialisés. Ces outils offrent des gains en productivité significatifs par rapport à la génération précédente, qui opérait sur des descriptions structurelles de l'architecture en VHDL ou Verilog. Ces descriptions algorithmiques doivent être retravaillées pour que les outils puissent générer des circuits performants. Pour faciliter cette tâche, une solution consiste à mettre en œuvre une boite à outils pour des transformations source-à-source orientées synthèse de haut niveau. En particulier, cette thèse s'intéresse aux transformations de boucles, avec pour objectif d'améliorer les performances en exposant des boucles parallèles et en améliorant la localité des accès mémoire. En nous appuyant sur une représentation des boucles dans le modèle polyédrique, nous proposons une approche qui améliore l'applicabilité du pipeline de nids de boucles en vérifiant sa légalité de manière plus précise que les approches existantes. De plus, lorsque la vérification échoue, nous proposons une technique de correction qui insère statiquement des états d'attente pour assurer la légalité du pipeline. Enfin, ce pipeline est mis en œuvre en utilisant une technique de génération de code qui met les nids de boucles à plat. Ces contributions ont été implémentées dans l'infrastructure de compilation source-à-source Gecos, avant d'être appliquées à un ensemble de benchmarks représentatifs des noyaux de calculs cibles de la synthèse de haut niveau. Les résultats montrent un gain en performances significatif, avec un surcoût en surface modéré.
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Parrot, Rémi. "Réseaux de Petri temporisés pour la synthèse de circuits pipelinés." Thesis, Ecole centrale de Nantes, 2022. http://www.theses.fr/2022ECDN0048.
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Dans cette thèse, nous nous intéressons à l’optimisation des ressources consommées par un circuit implémentant une loi de commande pour la charge de véhicules électriques sur FPGA. Tout d’abord, nous proposons une nouvelle solution au problème de la synthèse de pipeline minimisant les bascules et garantissant une fréquence minimale de fonctionnement. En se basant sur cette même approche, nous sommes capable de construire un pipeline permettant le pliage (ou multiplexage temporel) du circuit, c’est-à-dire qui permet la fusion de portions du circuit identiques en séquençant leur accès. Ainsi, les ressources consommées sont réduites à la fois en nombre de bascule et en nombre d’unités logiques. Notre approche est basée sur un modèle de Réseau de Petri Temporisé avec des transitions retardables, pouvant rater leur date de tir, et une action spécifique appelée reset qui réinitialise les horloges de toutes les transitions. Ce modèle s’avère équivalent à un automate à une horloge. Une surclasse de ce modèle, les Réseaux de Petri Temporisés avec transitions retardables (sans reset), s’avère être incomparable, en terme d’expressivité en sémantique faible, avec les classes de Réseaux de Petri Temporels ou Temporisés en temps dense ou discret. Enfin, une exploration symbolique de ce modèle ainsi que des résultats de complexité théorique et pratique sont étudiésIn this thesis, we are interested in the optimization of the resources consumed by a circuit implementing a control law for the charging of electric vehicles on FPGA. First, we propose a new solution to the pipeline synthesis problem that minimizes the number of flip-flops and guarantees a minimum operating frequency. Based on this same approach, we are able to build a pipeline that allows the folding (or time multiplexing) of the circuit, i.e., that allows the merging of identical circuit portions by sequencing their access. Thus, the consumed resources are reduced both in number of flip-flops and in number of logical units. Our approach is based on a Timed Petri Net model with delayable transitions that can miss their firing date, and a specific action called reset that resets the clocks of all transitions. This model is shown to be equivalent to a one-clock automaton. An overclass of this model, the Timed Petri Nets with delayable transitions (without reset), turns out tobe incomparable, in terms of expressivity in weak semantics, with the classes of Temporal or Timed Petri nets in dense or discrete time. Finally, a symbolic exploration of this model and results on theoretical and practical complexity are studied
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Rahmouni, Maher. "Ordonnancement et optimisations pour la synthèse de haut niveau des circuits de controle." Grenoble INPG, 1997. http://www.theses.fr/1997INPG0028.
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La plupart des algorithmes d'ordonnancement existants dans le domaine de la synthese de haut niveau sont concus pour des applications dominees par les donnees telles que les applications de traitement de signal. Ces algorithmes ont pour objectif de minimiser le cout de la partie operative. Cependant, dans les circuits de commande modernes, les performances de la partie controle dominent la performance globale du circuit. Il est donc necessaire de prendre en compte les caracteristiques de ces applications et de developper un ensemble de techniques qui permettent de minimiser le cout de la partie controle. Cette these presente de nouvelles techniques d'ordonnancement pour differentes architectures de controleur ainsi qu'une etude sur l'interpretation des structures du langage vhdl par la synthese de haut niveau. Les approches developpees se concentrent sur l'optimisation de la surface du controleur et de la performance du circuit. Le principe de ces techniques est d'analyser les differents chemins d'execution de la description comportementale du circuit representee sous forme d'un graphe de flot de controle. Les algorithmes realises ont ete integres dans l'outil de synthese de haut niveau amical. Les resultats montrent leur efficacite sur des exemples reels de circuits domines par le controle.
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Gopalan, Ranganath. "Leakage power driven behavioral synthesis of pipelined asics." [Tampa, Fla.] : University of South Florida, 2005. http://purl.fcla.edu/fcla/etd/SFE0001064.
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Hinrichsen, Holger. "Ein transformativer Ansatz für die Synthese und Verifikation algorithmischer Hardwarebeschreibungen." [S.l. : s.n.], 2000. http://deposit.ddb.de/cgi-bin/dokserv?idn=962731447.
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Alsharqawi, Abdelhalim. "DESIGN AND SYNTHESIS OF CLOCKLESS PIPELINES BASED ON SELF-RESETTING STAGE LOGIC." Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2833.
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For decades, digital design has been primarily dominated by clocked circuits. With larger scales of integration made possible by improved semiconductor manufacturing techniques, relying on a clock signal to orchestrate logic operations across an entire chip became increasingly difficult. Motivated by this problem, designers are currently considering circuits which can operate without a clock. However, the wide acceptance of these circuits by the digital design community requires two ingredients: (i) a unified design methodology supported by widely available CAD tools, and (ii) a granularity of design techniques suitable for synthesizing large designs. Currently, there is no unified established design methodology to support the design and verification of these circuits. Moreover, the majority of clockless design techniques is conceived at circuit level, and is subsequently so fine-grain, that their application to large designs can have unacceptable area costs. Given these considerations, this dissertation presents a new clockless technique, called self-resetting stage logic (SRSL), in which the computation of a block is reset periodically from within the block itself. SRSL is used as a building block for three coarse-grain pipelining techniques: (i) Stage-controlled self-resetting stage logic (S-SRSL) Pipelines: In these pipelines, the control of the communication between stages is performed locally between each pair of stages. This communication is performed in a uni-directional manner in order to simplify its implementation. (ii) Pipeline-controlled self-resetting stage logic (P-SRSL) Pipelines: In these pipelines, the communication between each pair of stages in the pipeline is driven by the oscillation of the last pipeline stage. Their communication scheme is identical to the one used in S-SRSL pipelines. (iii) Delay-tolerant self-resetting stage logic (D-SRSL) Pipelines: While communication in these pipelines is local in nature in a manner similar to the one used in S-SRL pipelines, this communication is nevertheless extended in both directions. The result of this bi-directional approach is an increase in the capability of the pipeline to handle stages with random delay. Based on these pipelining techniques, a new design methodology is proposed to synthesize clockless designs. The synthesis problem consists of synthesizing an SRSL pipeline from a gate netlist with a minimum area overhead given a specified data rate. A two-phase heuristic algorithm is proposed to solve this problem. The goal of the algorithm is to pipeline a given datapath by minimizing the area occupied by inter-stage latches without violating any timing constraints. Experiments with this synthesis algorithm show that while P-SRSL pipelines can reach high throughputs in shallow pipelines, D-SRSL pipelines can achieve comparable throughputs in deeper pipelines.Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Computer Engineering
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Wilson, Andrew Elbert. "Dynamic Reconfigurable Real-Time Video Processing Pipelines on SRAM-based FPGAs." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8620.
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For applications such as live video processing, there is a high demand for high performance and low latency solutions. The configurable logic in FPGAs allows for custom hardware to be tailored to a specific video application. These FPGA designs require technical expertise and lengthy implementation times by vendor tools for each unique solution. This thesis presents a dynamically configurable topology as an FPGA overlay to deploy custom hardware processing pipelines during run-time by utilizing dynamic partial reconfiguration. Within the FPGA overlay, a configurable topology with a routable switch allows video streams to be copied and mixed to create complex data paths. This work demonstrates a dynamic video processing pipeline with 11 reconfigurable regions and 16 unique processing cores, allowing for billions of custom run-time configurations.
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Pursel, Eugene Ray. "Synthetic vision : visual perception for computer generated forces using the programmable graphics pipeline /." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://library.nps.navy.mil/uhtbin/hyperion/04Sep%5FPursel.pdf.
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Thesis (M.S. in Modeling, Virtual Environments and Simulation (MOVES))--Naval Postgraduate School, Sept. 2004.Thesis Advisor(s): Christian J. Darken. Includes bibliographical references (p. 93-95). Also available online.
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Pasca, Bogdan Mihai. "Calcul flottant haute performance sur circuits reconfigurables." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2011. http://tel.archives-ouvertes.fr/tel-00654121.
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De plus en plus de constructeurs proposent des accélérateurs de calculs à base de circuits reconfigurables FPGA, cette technologie présentant bien plus de souplesse que le microprocesseur. Valoriser cette flexibilité dans le domaine de l'accélération de calcul flottant en utilisant les langages de description de circuits classiques (VHDL ou Verilog) reste toutefois très difficile, voire impossible parfois. Cette thèse a contribué au développement du logiciel FloPoCo, qui offre aux utilisateurs familiers avec VHDL un cadre C++ de description d'opérateurs arithmétiques génériques adapté au calcul reconfigurable. Ce cadre distingue explicitement la fonctionnalité combinatoire d'un opérateur, et la problématique de son pipeline pour une précision, une fréquence et un FPGA cible donnés. Afin de pouvoir utiliser FloPoCo pour concevoir des opérateurs haute performance en virgule flottante, il a fallu d'abord concevoir des blocs de bases optimisés. Nous avons d'abord développé des additionneurs pipelinés autour des lignes de propagation de retenue rapides, puis, à l'aide de techniques de pavages, nous avons conçu de gros multiplieurs, possiblement tronqués, utilisant des petits multiplieurs. L'évaluation de fonctions élémentaires en flottant implique souvent l'évaluation en virgule fixe d'une fonction. Nous présentons un opérateur générique de FloPoCo qui prend en entrée l'expression de la fonction à évaluer, avec ses précisions d'entrée et de sortie, et construit un évaluateur polynomial optimisé de cette fonction. Ce bloc de base a permis de développer des opérateurs en virgule flottante pour la racine carrée et l'exponentielle qui améliorent considérablement l'état de l'art. Nous avons aussi travaillé sur des techniques de compilation avancée pour adapter l'exécution d'un code C aux pipelines flexibles de nos opérateurs. FloPoCo a pu ainsi être utilisé pour implanter sur FPGA des applications complètes.
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Wu, Wei-Hong, and 吳威宏. "Low-Voltage Low-Power CMOS Multiplier Design Using Pipeline Latch High-Level Synthesis Approach." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/02208380310385112207.
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碩士臺灣大學
電子工程學研究所
98
The integrate-circuit technology scale down recently, more functionality can be combined into a single chip. So circuit complexity thereupon increases, performance and power consumption will be considered. The thesis describe a ways to increase speed of a circuit, and make up the high-level circuit. Chapter 1 introduce CMOS very large scale integrated circuits reason, power consumption and simulation software . Chapter 2 introduces a 16-bit Wallace tree multiplier circuit with VDD = 0.5V. Latch technology insert the multiplier become pipeline structure. Using Synopsys Primetime EDA tool analyses result, We can get the 257% increase operation frequency. Because of the final adder is bigger delay than other path of the multiplier circuit, so we can get the 95% increase operation frequency by change the VDD = 1V. Chapter 3 introduces a high-level multiplier circuit consists of 16-bit multiplier circuits, compare with high-level Wallace multiplier, performance and power consumption have not been improved, but is easily scalable to higher bit precision by duplicating sub-multiplier and adding an additional levels of reduction, allows for short design time. We have a way to increase speed by insert pipeline latch into final adder of the high-level multiplier.
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Chih-HsuanWang and 王志亘. "PIPELINED SCHEDULE SYNTHESIS FOR MULTIMEDIA SOC." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/06820709950847495741.
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碩士國立臺灣大學
資訊工程學研究所
95
Multimedia SoCs have property of throughput constraints. The throughput of multimedia application is the rate at which it processes input data, and this is usually the prime constraint on most multimedia applications. In order to meet the throughput constraints of these system with low cost, it is necessary to construct more efficient implementation with pipelined design. Idea of pipelined design is to divide applications into several concurrently executing stages, thus increasing its data rate. In this thesis, we presented a solution to pipelined schedule synthesis for multimedia SoCs such that pipeline buffer is minimized under throughput constraints. We proposed a three-step exploration methodology to obtain pipelined schedule with minimal pipeline buffer which meets the given throughput constraints. Performance evaluation results prove the proposed three-step exploration methodology could reduce the run-time overhead and derive a near-optimal solution.
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Chih-HsuanWang. "PIPELINED SCHEDULE SYNTHESIS FOR MULTIMEDIA SOC." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1408200721483300.
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Chiu, Yi-Sheng, and 邱奕升. "Pipelined Schedule Synthesis for Periodic Conditional Data Flows." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/27031054807562253611.
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碩士國立臺灣大學
資訊工程學研究所
97
Heterogeneous multi-core platforms has become the trend for the high performance requirement of multimedia pplications. The pipeline techniques are widely used in the multi-core platforms to lead performance elevation, but the data dependencies of multimedia applications often make pipelined design unsatisfied. In this thesis, we target on multimedia streaming applications described as conditional data flows on heterogeneous multi-core platforms, and we design a ”Tile Piecing Algorithm” for pipelined schedule synthesis within the targeted applications and platforms. The approach gives an efficient way to construct a pipelined schedule. The performance evaluation result prove the proposed ”Tile Piecing Algorithm” could reduce the runtime overhead and derive a well-designed pipelined schedule.
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Huang, Xian-June, and 黃咸鈞. "Bipartition and Synthesis in Low Power Pipelined Circuits." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/48703485533536032107.
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碩士國立臺灣大學
電機工程學系
85
The bipartition architecture of finite-state machines can effectively reduce power consumption in CMOS digital circuits using a smaller FSM extracted from original. By treating each different output pattern as a state, we extend this concept to pipelined circuits. It is possible that the output of a pipelined circuit transit mainly among some few states. If some few states dominate the state transition most of the time, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states with high activity is small and the other that contains the remainder with low activity is big. An additional combination logic block is introduced to control which of the two partitioned blocks to work. Power reduction is based on the observation that most time the small block is at work and the big one is at idle. In order to maximize the efficiency of additional control block, we present an algorithm that can improve the performance of our bipartition architecture. Experiments with MCNC benchmarks show high percentage of power saving by using our new architecture for low power pipelined circuit design.
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Huang, Xian-Jun, and 黃咸鈞. "Bipartition and Synthesis in Low Power Pipelined Circuits." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/70628650054992598192.
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LUO, SHAO-PING, and 駱紹平. "Automated synthesis of asynchronous pipelines from algorithmic description." Thesis, 1991. http://ndltd.ncl.edu.tw/handle/20024371263591746976.
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Shyu, Ya-Ting, and 許雅婷. "An Automated Synthesis Tool for Pipelined Analog-to-Digital Converters." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/76888787154816953369.
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碩士國立成功大學
電機工程學系碩博士班
96
Using a system-on-chip to realize a complex system has become the main trend for today’s IC design. To realize a complete system on a single chip, there are more and more analog and mixed-signal circuits integrated in the chip. With the increasing complexities of SoC designs and the shortening average life-periods of electronic products, it is getting harder to complete a SoC design within a very tight design schedule. Therefore, developing design automation tools for mixed-signal circuits to speedup the design process is more and more important. Analog-to-digital converter is one of the most commonly used components in a mixed-signal SoC. Among all architectures of high-speed analog-to-digital converters, the pipelined analog-to-digital converter is widely used in the applications of mobile communication, display, and imaging systems because it exhibits properties of high-speed, high-accuracy and low power consumption. However, its design complexity is higher then other architectures of analog-to-digital converters. In this thesis, we develop an automated synthesis tool for pipelined ADCs by consulting the circuit-design experience. It can be used to design a pipelined ADC with acceptable performances in a short time. Experimental results show that it can complete the design of the whole pipelined ADC circuit in one day on the operating system with two 1.2GHz UltraSPARC-III+ processor and 2GB memory.
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Chen, Shyh-jong, and 陳世宗. "Partition and Synthesis in Low Power FSMs and Pipelined Circuits." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/33900657068863868367.
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博士國立臺灣大學
電機工程學系研究所
86
This thesis proposes some techniques that applying new multi-partition architecture to implement low power FSMs and bipartition architecture for low power pipelined circuits. If the transition behavior of one FSM clusters around some few adjoining states, then one FSM can be split into several small FSMs: almost one or two dominate the transition behavior but implemented in samll area and the others are big with low activity. All the small FSMs work in turn to emulate the transition behavior of the original FSM. Because each small FSM consists of fewer state than the original FSM, each one consumes less power. At any moment, only one small machine and the concerned control overhead dissipate power. Therefore, to get a low power machine, the total of the all the small machine and overhead power consumptions must be less than that of the original machine. Treating each different output pattern of a combinational logic block as a state, bipartition concept can be used in pipelined circuits. If some few states dominate the state transition in most of the time, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states with high activity is small and the other that contains the remainder with low activity is big. An additional combination logic block is introduced to control which of the two partitioned blocks to work. Power reduction is based on the observation that most time the small block is at work and the big one is at idle. In order to maximize the efficiency of additional control block, we present an algorithm that can improve the performance of our bipartition architecture. Experiments with MCNC benchmarks show high percentage of power saving by using our new architecture for low power FSM and pipelined circuit design. Because delay elements must be added in front of each patitioned block of pipelined circuits, it will increase much overhead. So our thesis does not discuss with multi-partition on low power pipelined circuit.
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Ruan, Shanq-Jang, and 阮聖彰. "Synthesis of Low Power Pipelined Logic Circuits Using Bipartition and Encoding Techniques." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/47969583754170565902.
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博士國立臺灣大學
電機工程學研究所
91
In the last decade, power dissipation has become a critical design metric for an increasingly large number of VLSI circuits. This is largely due to in the use of portable electronic appliances which calls for complex integrated systems that can be powered by lightweight batteries with long periods between recharges. Additionally, the reliability of high performance computation in modern processor is always defeated by increasing heat, which is due to the power consumption. Of particular interest in such systems is pipelining design fashion. In this dissertation, we are concerned with optimizing logic level pipelined circuits for low power. We study the power distribution of a pipeline stage and propose several architectures to achieve the lower power consumption. We employ bipartition and encoding techniques for reducing power in a pipeline stage. We first propose two bipartition architectures: bipartition based on output extraction and bipartition based on Shannon expansion. The former bipartitions the circuit in terms of output clustering characteristic, the latter bipartitions the circuit by Shannon expansion with minimum entropy consideration. In order to further reduce power, we apply encoding techniques to both architectures and propose two novel architectures: bipartition single-encoding architecture and biparition dual-encoding architecture. These two architectures reduce the switch activity of not only combinational logic block but pipelined register. To validate the results, we employ an accurate transistor-level power estimator to estimate power dissipation. The transistor-level power estimator provides accurate power results for analyzing the effect of bipartition and encoding techniques.
25
Guzmán-Vega, Francisco J. "Applications in computational structural biology: the generation of a protein modelling pipeline and the structural analysis of patient-derived mutations." Thesis, 2019. http://hdl.handle.net/10754/652872.
Full textAbstract:
Besides helping us advance the understanding of the physicochemical principles governing the three-dimensional folding of proteins and their mechanisms of action, the ability to build, evaluate, and optimize reliable 3D protein models has provided valuable tools for the development of different applications in the fields of biotechnology, medicine, and synthetic biology. The development of automated algorithms has made many of the current methodologies for protein modelling and visualization available to researchers from all backgrounds, without the need to be familiarized with the inner workings of their statistical and biophysical principles. However, there is still a lack in some areas where the learning curves are too steep for the methods to be widely used by the average non-programmer molecular biologist, or the implementation of the methods lacks key features to improve the interpretability and impact of their results.
Throughout this work, I will focus on two different applications in the field of structural biology where computational methods provide useful tools to aid in synthetic biology or medical research. The first application is the implementation of a pipeline to build models of protein complexes by joining structured domains with disordered linkers, in individual or multiple chains, and with the possibility of building symmetric structures. Its capabilities and performance for the generation of complex constructs are evaluated, and possible areas of improvement described. The second application, but not less important, involves the structural analysis of patient-derived protein mutants using protein modelling techniques and visualization tools, to elucidate the potential molecular basis for the patient’s phenotype. The methodology for these analyses is described, along with the results and observations from 22 such cases in 13 different proteins. Finally, the need for a dedicated pipeline for the structure-based prediction of the effect of different types of mutations on the stability and function of proteins, complementary to available sequence-based approaches, is highlighted.