Relevant bibliographies by topics / PLL Phase locked loops

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'PLL Phase locked loops'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "PLL Phase locked loops"

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Niezrecki, C., and H. H. Cudney. "Structural Control Using Analog Phase-Locked Loops." Journal of Vibration and Acoustics 119, no. 1 (January 1, 1997): 104–9. http://dx.doi.org/10.1115/1.2889677.

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A study of the application of the phase-locked loop (PLL) to modal control of mechanical structures is performed. An analog PLL circuit is used to control the vibration of a cantilevered beam with piezoelectric sensors and actuators. By using the PLL controller, strain rate feedback is provided within a narrow and distinct frequency range about the fourth mode of the beam. The controller ignores all other modes and does not affect the phase outside of the frequency range. The PLL controller provides a simple, inexpensive, and effective method to control an individual structural mode or set of modes without causing spillover.
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Lei, Feiran, and Marvin H. White. "Reference Injected Phase-Locked Loops (PLL-RIs)." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 7 (July 2017): 1651–60. http://dx.doi.org/10.1109/tcsi.2017.2668298.

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Zhai, Bingcong. "Understanding of the Coherent Demodulation with Phase-Locked Loop." MATEC Web of Conferences 176 (2018): 01028. http://dx.doi.org/10.1051/matecconf/201817601028.

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The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way. Therefore, more and more attentions have been paid to the research and application of all digital phase-locked loops. This paper serves as an introduction about the basic background of PLL, the basic characteristics and structure of PLL, and the basic principles of modulation and demodulation. It provides a concise application about the basic principle and main design process of modulation and demodulation of FSK signal, which are realized by using phase-locked loop chip NE564.
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Tsyrulnikova, L. A., B. P. Sudeev, and A. R. Safin. "Wave Analogs of Media Based on Phase Locked Loops." Journal of the Russian Universities. Radioelectronics 23, no. 3 (July 21, 2020): 32–40. http://dx.doi.org/10.32603/1993-8985-2020-23-3-32-40.

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Introduction. At present, phase locked loops (PLLs) are widely used: from optimal signal detection and frequency synthesis to automatic control of phase distribution in phased scanned arrays. One of the simplest structures is a multi-stage (chain) PLL, which may contain a specially selected multi-connected control circuit. Such cascaded PLLs have wide application in solving a number of tasks of the theory of optimal estimates, multi-position phase telegraphy, in synchronizing of many tunable generators while preserving specified phase relations between their oscillations, etc. PLLs are actively used in radio physics both in analog and digital versions. One of the promising directions for collective PLLs development is the study of ensembles of neuromorphic networks based on PLL. Aim. To obtain wave analogues characterizing the collective PLL not as a discrete network, but as a continuous (distributed) media. Materials and methods. An unidirectional model (without mutual control circuits) of the cascade structure of the PLL. Results. Wave analogues of cascade-coupled phase synchronization systems that do not contain mutual control circuits were found. A solution of equations of wave analogues was found. A proof of validity of the obtained approximate solution in comparison with the exact one was presented. Conclusion. It was shown that by selecting a filter in a control circuit of each single-circuit circuit with different transmission coefficients, it is possible to obtain various types of continuous media or wave analogues of chain structures based on phase synchronization systems.
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Ahissar, Ehud. "Temporal-Code to Rate-Code Conversion by Neuronal Phase-Locked Loops." Neural Computation 10, no. 3 (April 1, 1998): 597–650. http://dx.doi.org/10.1162/089976698300017683.

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Peripheral sensory activity follows the temporal structure of input signals. Central sensory processing uses also rate coding, and motor outputs appear to be primarily encoded by rate. I propose here a simple, efficient structure, converting temporal coding to rate coding by neuronal phase-locked loops (PLL). The simplest form of a PLL includes a phase detector (that is, a neuronal-plausible version of an ideal coincidence detector) and a controllable local oscillator that are connected in a negative feedback loop. The phase detector compares the firing times of the local oscillator and the input and provides an output whose firing rate is monotonically related to the time difference. The output rate is fed back to the local oscillator and forces it to phase-lock to the input. Every temporal interval at the input is associated with a specific pair of output rate and time difference values; the higher the output rate, the further the local oscillator is driven from its intrinsic frequency. Sequences of input intervals, which by definition encode input information, are thus represented by sequences of firing rates at the PLL's output. The most plausible implementation of PLL circuits is by thalamocortical loops in which populations of thalamic “relay” neurons function as phase detectors that compare the timings of cortical oscillators and sensory signals. The output in this case is encoded by the thalamic population rate. This article presents and analyzes the algorithmic and the implementation levels of the proposed PLL model and describes the implementation of the PLL model to the primate tactile system.
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Shepherd, Paul, Ashfaqur Rahman, Shamim Ahmed, A. Matt Francis, Jim Holmes, and H. Alan Mantooth. "500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000076–83. http://dx.doi.org/10.4071/hitec-tp15.

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Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.
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Rashed, Mohamed, Christian Klumpner, and Greg Asher. "Dynamic phasor analysis and design of phase-locked loops for single phase grid connected converters." COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 34, no. 4 (July 6, 2015): 1122–43. http://dx.doi.org/10.1108/compel-04-2014-0090.

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Purpose – The purpose of the paper is to introduce the dynamic phasor modelling (DPM) approach for stability investigation and control design of single-phase phase-locked loops (PLLs). The aim is to identify the system instabilities not predicted using the existent analysis and design methods based on the simplified average model approach. Design/methodology/approach – This paper starts by investigating the performance of three commonly used PLL schemes: the inverse park-PLL, the second-order generalised integrators (SOGI)-frequency-locked loop and the enhanced-PLL, designed using the simplified average model and will show that following this approach, there is a mismatch between their actual and desired transient performance. A new PLL design method is then proposed based on the DPM approach that allows the development of fourth-order DPM models. The small-signal eigenvalues analysis of the fourth-order DPM models is used to determine the control gains and the stability limits. Findings – The DPM approach is proven to be useful for single-phase PLLs stability analysis and control parameters design. It has been successfully used to design the control parameters and to predict the PLL stability limits, which have been validated via simulation and experimental tests consisting of grid voltage sag, phase jump and frequency step change. Originality/value – This paper has introduced the use of DPM approach for the purpose of single-phase PLL stability analysis and control design. The approach has enabled accurate control gains design and stability limits identification of single-phase PLLs.
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Burgos-Mellado, Claudio, Alessandro Costabeber, Mark Sumner, Roberto Cárdenas-Dobson, and Doris Sáez. "Small-Signal Modelling and Stability Assessment of Phase-Locked Loops in Weak Grids." Energies 12, no. 7 (March 30, 2019): 1227. http://dx.doi.org/10.3390/en12071227.

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This paper proposes a low-complexity small signal model for a 3-leg converter connected to a balanced three-phase, three-wire weak grid and synchronised to this grid using a PLL implemented in a synchronous rotating d-q axis. A thorough analysis of the system stability as a function of the PLL bandwidth and the short circuit ratio (SCR) of the grid is performed based on a linearised model. By using the proposed model, an improved design process is proposed for the commonly used dq-PLL that accounts for the potential stability issues which may occur in weak grids. Using the proposed approach, it is possible to optimise the PLL design to find the fastest PLL that can operate stably considering the SCR of the grid. In addition, the proposed model is very simple, resulting in a straightforward design tool that could also be used for online stability monitoring. The method is validated through simulations and experimental results from a 5kW laboratory system.
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Osmany, S. A., F. Herzel, K. Schmalz, and W. Winkler. "Phase noise and jitter modeling for fractional-N PLLs." Advances in Radio Science 5 (June 13, 2007): 313–20. http://dx.doi.org/10.5194/ars-5-313-2007.

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Abstract. We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filtered by the PLL operation. We express the rms phase error (jitter) in terms of phase noise of the reference, the VCO phase noise and the third-order loop filter parameters. In addition, we consider OFDM systems, where the PLL phase noise is reduced by digital signal processing after down-conversion of the RF signal to baseband. The rms phase error is discussed as a function of the loop parameters. Our model drastically simplifies the noise optimization of the PLL loop dynamics.
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Imran, Rajib, Monirul Islam, and Abdullah Al Kafi. "Synthesizable Digital Phase Locked Loop Implementation." Advanced Materials Research 684 (April 2013): 317–21. http://dx.doi.org/10.4028/www.scientific.net/amr.684.317.

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Phase locked loop (PLL) is a very common circuit in the most of the electrical devices. The systems where needed clock or data recovery or frequency synthesis, PLL is the most cost effective and efficient choice that from cellular phone in our hands to the computers, televisions, radios and a different controller, PLL is everywhere. Due to ever increasing growth of the digital systems especially in the wireless communication, the Digital PLL (DPLL) has been developed to overcome the disadvantages of analog techniques such as large noise, power hungry, parameter sensitivity etc. Besides DPLL provides faster lock-in time, better testability, stability and portability over different process. The most of the resources available discussed about the theoretical model of the DPLL which is not synthesizable, that’s why a model is presented here keeping in mind that must be fully digital and synthesizable. The proposed PLL structure is fully digital, has the design flexibility with reduced hardware, low power consumption and higher power efficiency.
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Dissertations / Theses on the topic "PLL Phase locked loops"

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Lei, Feiran. "Injection Locked Synchronous Oscillators (SOs) and Reference Injected Phase-Locke Loops (PLL-RIs)." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492789278258943.

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SINGH, GUNEET. "HIGH-FREQUENCY CHARGE-PUMP BASED PHASE-LOCKED LOOP DESIGN AND IT'S CHARACTERIZATION USING VERILOG-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155077793.

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Eklund, Robert. "Linearization of Voltage-Controlled Oscillators in Phase-Locked Loops." Thesis, Linköping University, Department of Science and Technology, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5366.

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This is a thesis report done as part of the Master of Science in Electronics Design Engineering given at Linköping University, Campus Norrköping. The thesis work is done at Ericsson AB in the spring of 2005. The thesis describes a method of removing variations in the tuning sensitivity of voltage-controlled crystal oscillators due to different manufacturing processes. These variations results in unwanted variations in the modulation bandwidth of the phase-locked loop the oscillator is used in. Through examination of the theory of phase-locked loops it is found that the bandwidth of the loop is dependent on the tuning sensitivity of the oscillator.

A method of correcting the oscillator-sensitivity by amplifying or attenuating the control-voltage of the oscillator is developed. The size of the correction depends on the difference in oscillator-sensitivity compared to that of an ideal oscillator. This error is measured and the correct correction constant calculated.

To facilitate the measurements and correction extra circuits are developed and inserted in the loop. The circuits are both analog and digital. The analog circuits are mounted on an extra circuit board and the digital circuits are implemented in VHDL in an external FPGA.

Tests and theoretical calculations show that the method is valid and able to correct both positive and negative variations in oscillator-sensitivity of up to a factor ±2.5 times. The bandwidth of the loop can be adjusted between 2 to 15 Hz (up to ±8 dB, relative an unmodified loop).

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Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.

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Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.
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Barale, Francesco. "Frequency dividers design for multi-GHz PLL systems." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24610.

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Kim, Sinnyoung. "Analysis and Design of Radiation-Hardened Phase-Locked Loop." 京都大学 (Kyoto University), 2014. http://hdl.handle.net/2433/188872.

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Lee, Kun Seok. "Wideband phase-locked loops with high spectral purity for wireless communications." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44882.

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The objective of this research is to demonstrate the feasibility of the implementation of wideband RF CMOS PLLs with high spectral purity using deep sub-micron technologies. To achieve wide frequency coverage, this dissertation proposed a 45-nm SOI-CMOS RF PLL with a wide frequency range to support multiple standards. The PLL has small parasitic capacitance with the help of a SOI technology, increasing the frequency tuning range of a capacitor bank. A designed and fabricated chip demonstrates the PLL supporting almost all cellular standards with a single PLL. This dissertation also proposed a third order sample-hold loop filter with two MOS switches for high spectral purity. Sample-hold operation improves in-band and out-of-band phase noise performance simultaneously in RF PLLs. By controlling the size of the MOS switches and control time, the nonideal effects of the MOS switches are minimized. The sample-hold loop filter is implemented within a 45-nm RF PLL and the performance is evaluated. Thus, this research provides a solution for wideband CMOS frequency synthesizers for multi-band, multi-mode, and multiple-standard applications in deep sub-micron technologies.
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Lin, Ming-Lang. "Analogue to information system based on PLL-based frequency synthesizers with fast locking schemes." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/4627.

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Data conversion is the crucial interface between the real world and digital processing systems. Analogue-to-digital converters and digital-to-analogue converters are two key conversion devices and used as the interface. Up to now, the conventional ADCs based on Nyquist sampling theorem are facing a critical challenge: the resolution and the sampling rate must be radically increased when some applications such as radar detection and ultra-wideband communication emerge. The offset of comparators and the setup time of sample-and-hold circuits, however, limit the resulution and clock rate of ADCs. Alternatively, in some applications such as speech, temperature sensor, etc. signals remain possibly unchanged for prolonged periods with brief bursts of significant activity. If trational ADCs are employed in such circumstances a higher bandwidth is required for transmitting the converted samples. On the other hand, sampling signals with an extremely high clock rate are also required for converting the signals with the feature of sparsity in time domain. The level-crossing sampling scheme (LCSS) is one of the data conversions suitable for converting signals with the sparsity feature and brief bursts of signigicant activity. due to the traditional LCSS with a fixed clock rate being limited in applications a novel irregular data conversion scheme called analogue-to-information system (AIS) is proposed in this thesis. The AIS is typically based upon LCSS, but an adjustable clock generator and a real time data compression scheme are applied to it. As the system-level simulations results of AIS show it can be seen that a data transmission saving rate nearly 30% is achieved for different signals. PLLs with fast pull-in and locking schemes are very important when they are applied in TDMA systems and fequency hopping wireless systems. So a novel triple path nonlinear phase frequency detector (TPNPFD) is also proposed in this thesis. Compared to otherPFDs, the pll-in and locking time in TPNPFD is much shorter. A proper transmission data format can make the recreation of the skipped samples and the reconstruction of the original signal more efficient, i.e. they can be achieved in a minimum number of the received data without increasing much more hardware complexity. So the preliminary data format used for transmitting the converted data from AIS is also given in the final chapter of this thesis for future works.
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Thomas, Renji George. "A Full Digital Phase Locked Loop." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406.

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Moes, Henderikus Jan. "A low noise PLL-based frequency synthesiser for X-band radar." Thesis, Link to the online version, 2008. http://hdl.handle.net/10019/1337.

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Books on the topic "PLL Phase locked loops"

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Encinas, J. B. Phase locked loops. London: Chapman & Hall, 1993.

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Best, Roland E. Phase-Locked Loops. New York: McGraw-Hill, 2007.

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Encinas, J. B. Phase Locked Loops. Boston, MA: Springer US, 1993.

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Brennan, Paul V. Phase-Locked Loops. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-14006-0.

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Encinas, J. B. Phase Locked Loops. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3064-0.

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Cheema, Hammad M. 60-GHz CMOS Phase-Locked Loops. Dordrecht: Springer Science+Business Media B.V., 2010.

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Cheema, Hammad M., Reza Mahmoudi, and Arthur H. M. Roermund. 60-GHz CMOS Phase-Locked Loops. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9280-9.

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Stephens, Donald R. Phase-Locked Loops for Wireless Communications. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5717-3.

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Phase-locked loops: Theory and applications. Boca Raton: CRC Press, 1997.

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Phase-locked loops: Principles and practice. Basingstoke: Macmillan Press, 1996.

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Book chapters on the topic "PLL Phase locked loops"

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Encinas, J. B. "Simplified operation of PLL circuits." In Phase Locked Loops, 1–10. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3064-0_1.

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Encinas, J. B. "Linear bipolar silicon PLL integrated circuits." In Phase Locked Loops, 102–23. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3064-0_7.

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Stephens, Donald R. "Digital PLL Responses and Acquisition." In Phase-Locked Loops for Wireless Communications, 271–303. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5717-3_10.

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Encinas, J. B. "Analysis methods for linear PLLs." In Phase Locked Loops, 11–49. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3064-0_2.

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Encinas, J. B. "PLLs using digital phase comparators." In Phase Locked Loops, 124–43. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3064-0_8.

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Ehrhardt, Dietmar. "PLL (Phase Locked Loop)." In Verstärkertechnik, 270–78. Wiesbaden: Vieweg+Teubner Verlag, 1992. http://dx.doi.org/10.1007/978-3-322-83026-5_24.

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Tran, Thanh T. "Phase-Locked Loop (PLL)." In High-Speed DSP and Analog System Design, 105–20. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6309-3_6.

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Alvarado, Unai, Guillermo Bistué, and Iñigo Adín. "Phase Locked Loop (PLL) Design." In Lecture Notes in Electrical Engineering, 179–236. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-22987-9_8.

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Zhao, Feng, and Fa Foster Dai. "A Wide-Band Low Power BiCMOS PLL." In Low-Noise Low-Power Design for Phase-Locked Loops, 25–39. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-12200-7_3.

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Margaris, Nikolaos I. "2. PLL components." In Theory of the Non-linear Analog Phase Locked Loop, 13–29. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-39990-2_2.

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Conference papers on the topic "PLL Phase locked loops"

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Lopes, Guilherme Cano, Átila Madureira Bueno, and José Manoel Balthazar. "Elastic Beam Vibration Control With Phase-Locked Loop." In ASME 2014 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2014. http://dx.doi.org/10.1115/imece2014-36647.

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The Phase-Locked Loop (PLL) is a closed-loop control system that synchronizes a local oscillator to an oscillatory incoming signal. The PLL plays important roles in communication, computation and control systems, allowing the correct flow of information by efficiently generating and distributing clock reference signals. PLLs are also applied in motor speed control and in atomic force microscopy. Nevertheless, PLLs are inherently nonlinear devices, and behaviors such as bifurcations and chaos may arise. In this paper, the vibration control of an elastic beam is performed by a PLL control structure. Additionally, different designs for the PLL-beam control system are discussed.
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Brennan, P. V. "Investigation of non-linear operation of PLL FM demodulators." In IEE Colloquium on Phase Lock Loops: Theory and Practice. IEE, 1999. http://dx.doi.org/10.1049/ic:19990565.

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Mason, J. S. B. "A 400 Mb/s clock and data recovery PLL system in a 0.5 um CMOS ASIC process." In IEE Colloquium on Phase Lock Loops: Theory and Practice. IEE, 1999. http://dx.doi.org/10.1049/ic:19990567.

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Goh, S. H., Wendy Lau, B. L. Yeoh, H. W. Ho, G. F. You, Hu Hao, Y. E. Koh, and Jeffrey Lam. "Debugging Phase-Locked Loop Failures in Integrated Circuit Products." In ISTFA 2014. ASM International, 2014. http://dx.doi.org/10.31399/asm.cp.istfa2014p0456.

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Abstract A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.
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Pallavi, Priya, and Ch V. Rama Rao. "Phase-locked Loop (PLL) Based Phase Estimation in Single Channel Speech Enhancement." In Interspeech 2018. ISCA: ISCA, 2018. http://dx.doi.org/10.21437/interspeech.2018-1950.

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del Rocio Ricardez-Trejo, Ma, Celso Gutierrez-Martinez, J. Alfredo Torres-Fortiz, and Jacobo Meza-Perez. "Modeling and simulation of phase-locked loops (PLL) microwave generators using Matlab/Simulink® basic blocks." In 2017 IEEE URUCON. IEEE, 2017. http://dx.doi.org/10.1109/urucon.2017.8171854.

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Lei, Feiran, and Marvin H. White. "A study of the low frequency noise (LFN) in reference injected Phase Locked Loops (PLL-RI)." In 2016 IEEE Dallas Circuits and Systems Conference (DCAS). IEEE, 2016. http://dx.doi.org/10.1109/dcas.2016.7791144.

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Clark, Matthew, and Z. C. Feng. "Dynamic Testing of Mechanical Properties of a Substrate Using Phase-Locked-Loop." In ASME 2005 International Mechanical Engineering Congress and Exposition. ASMEDC, 2005. http://dx.doi.org/10.1115/imece2005-81392.

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This paper explores dynamically deriving the mechanical properties of a substrate. A method is presented in which a phase locked loop (PLL) is used to find the resonance frequency of a mechanical model consisting of an oscillating probe and a material substrate. This is done by first presenting an accurate PLL which is stable for nonlinear systems. The relationship between the system frequency and the stiffness of the material substrate is derived theoretically. The stiffness of the substrate is obtained by combining the theoretical result and the converging resonance frequency from PLL.
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Shiu, Yu, and C. C. Jay Kuo. "On-Line Musical Beat Tracking with Phase-Locked-Loop (PLL) Techniique." In 2007 Digest of Technical Papers International Conference on Consumer Electronics. IEEE, 2007. http://dx.doi.org/10.1109/icce.2007.341369.

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10

Ostrem, T., W. Sulkowski, L. Norum, and C. Wang. "Grid Connected Photovoltaic (PV) Inverter with Robust Phase-Locked Loop (PLL)." In 2006 IEEE/PES Transmission & Distribution Conference and Exposition: Latin America. IEEE, 2006. http://dx.doi.org/10.1109/tdcla.2006.311434.

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Reports on the topic "PLL Phase locked loops"

1

Rosignoli, D., and J. Rose. Design and test of a phase shifter utilizing phase loop lock (PLL). Office of Scientific and Technical Information (OSTI), October 1994. http://dx.doi.org/10.2172/1118897.

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