To see the other types of publications on this topic, follow the link: PLL Phase locked loops.
Dissertations / Theses on the topic 'PLL Phase locked loops'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'PLL Phase locked loops.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Lei, Feiran. "Injection Locked Synchronous Oscillators (SOs) and Reference Injected Phase-Locke Loops (PLL-RIs)." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492789278258943.
Full text
2
SINGH, GUNEET. "HIGH-FREQUENCY CHARGE-PUMP BASED PHASE-LOCKED LOOP DESIGN AND IT'S CHARACTERIZATION USING VERILOG-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155077793.
Full text
3
Eklund, Robert. "Linearization of Voltage-Controlled Oscillators in Phase-Locked Loops." Thesis, Linköping University, Department of Science and Technology, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5366.
Full textAbstract:
This is a thesis report done as part of the Master of Science in Electronics Design Engineering given at Linköping University, Campus Norrköping. The thesis work is done at Ericsson AB in the spring of 2005. The thesis describes a method of removing variations in the tuning sensitivity of voltage-controlled crystal oscillators due to different manufacturing processes. These variations results in unwanted variations in the modulation bandwidth of the phase-locked loop the oscillator is used in. Through examination of the theory of phase-locked loops it is found that the bandwidth of the loop is dependent on the tuning sensitivity of the oscillator.
A method of correcting the oscillator-sensitivity by amplifying or attenuating the control-voltage of the oscillator is developed. The size of the correction depends on the difference in oscillator-sensitivity compared to that of an ideal oscillator. This error is measured and the correct correction constant calculated.
To facilitate the measurements and correction extra circuits are developed and inserted in the loop. The circuits are both analog and digital. The analog circuits are mounted on an extra circuit board and the digital circuits are implemented in VHDL in an external FPGA.
Tests and theoretical calculations show that the method is valid and able to correct both positive and negative variations in oscillator-sensitivity of up to a factor ±2.5 times. The bandwidth of the loop can be adjusted between 2 to 15 Hz (up to ±8 dB, relative an unmodified loop).
4
Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.
Full textAbstract:
Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications.
Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL).
This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.
5
Barale, Francesco. "Frequency dividers design for multi-GHz PLL systems." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24610.
Full text
6
Kim, Sinnyoung. "Analysis and Design of Radiation-Hardened Phase-Locked Loop." 京都大学 (Kyoto University), 2014. http://hdl.handle.net/2433/188872.
Full text
7
Lee, Kun Seok. "Wideband phase-locked loops with high spectral purity for wireless communications." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44882.
Full textAbstract:
The objective of this research is to demonstrate the feasibility of the implementation of wideband RF CMOS PLLs with high spectral purity using deep sub-micron technologies. To achieve wide frequency coverage, this dissertation proposed a 45-nm SOI-CMOS RF PLL with a wide frequency range to support multiple standards. The PLL has small parasitic capacitance with the help of a SOI technology, increasing the frequency tuning range of a capacitor bank. A designed and fabricated chip demonstrates the PLL supporting almost all cellular standards with a single PLL. This dissertation also proposed a third order sample-hold loop filter with two MOS switches for high spectral purity. Sample-hold operation improves in-band and out-of-band phase noise performance simultaneously in RF PLLs. By controlling the size of the MOS switches and control time, the nonideal effects of the MOS switches are minimized. The sample-hold loop filter is implemented within a 45-nm RF PLL and the performance is evaluated. Thus, this research provides a solution for wideband CMOS frequency synthesizers for multi-band, multi-mode, and multiple-standard applications in deep sub-micron technologies.
8
Lin, Ming-Lang. "Analogue to information system based on PLL-based frequency synthesizers with fast locking schemes." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/4627.
Full textAbstract:
Data conversion is the crucial interface between the real world and digital processing systems. Analogue-to-digital converters and digital-to-analogue converters are two key conversion devices and used as the interface. Up to now, the conventional ADCs based on Nyquist sampling theorem are facing a critical challenge: the resolution and the sampling rate must be radically increased when some applications such as radar detection and ultra-wideband communication emerge. The offset of comparators and the setup time of sample-and-hold circuits, however, limit the resulution and clock rate of ADCs. Alternatively, in some applications such as speech, temperature sensor, etc. signals remain possibly unchanged for prolonged periods with brief bursts of significant activity. If trational ADCs are employed in such circumstances a higher bandwidth is required for transmitting the converted samples. On the other hand, sampling signals with an extremely high clock rate are also required for converting the signals with the feature of sparsity in time domain. The level-crossing sampling scheme (LCSS) is one of the data conversions suitable for converting signals with the sparsity feature and brief bursts of signigicant activity. due to the traditional LCSS with a fixed clock rate being limited in applications a novel irregular data conversion scheme called analogue-to-information system (AIS) is proposed in this thesis. The AIS is typically based upon LCSS, but an adjustable clock generator and a real time data compression scheme are applied to it. As the system-level simulations results of AIS show it can be seen that a data transmission saving rate nearly 30% is achieved for different signals. PLLs with fast pull-in and locking schemes are very important when they are applied in TDMA systems and fequency hopping wireless systems. So a novel triple path nonlinear phase frequency detector (TPNPFD) is also proposed in this thesis. Compared to otherPFDs, the pll-in and locking time in TPNPFD is much shorter. A proper transmission data format can make the recreation of the skipped samples and the reconstruction of the original signal more efficient, i.e. they can be achieved in a minimum number of the received data without increasing much more hardware complexity. So the preliminary data format used for transmitting the converted data from AIS is also given in the final chapter of this thesis for future works.
9
Thomas, Renji George. "A Full Digital Phase Locked Loop." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406.
Full text
10
Moes, Henderikus Jan. "A low noise PLL-based frequency synthesiser for X-band radar." Thesis, Link to the online version, 2008. http://hdl.handle.net/10019/1337.
Full text
11
Sun, Lizhong Carleton University Dissertation Engineering Electronics. "High speed submicron CMOS oscillators and PLL clock generators." Ottawa, 1999.
Find full text
12
Shariat, Yazdi Ramin. "Mixed signal design flow, a mixed signal PLL case study." Thesis, University of Waterloo, 2001. http://hdl.handle.net/10012/916.
Full textAbstract:
Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- µ m CMOS process technology.
13
Cheng, Shanfeng. "Design of CMOS integrated phase-locked loops for multi-gigabits serial data links." Texas A&M University, 2006. http://hdl.handle.net/1969.1/4954.
Full textAbstract:
High-speed serial data links are quickly gaining in popularity and replacing the
conventional parallel data links in recent years when the data rate of communication
exceeds one gigabits per second. Compared with parallel data links, serial data links are
able to achieve higher data rate and longer transfer distance. This dissertation is focused on
the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks
used in multi-gigabits serial data link transceivers.
Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are
modeled and analyzed. The steady-state behavior of BPLLs is derived with combined
discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs
are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC-
192, the mainstream standard for optical serial data links, is presented. The CDR is based
on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked
loop based on a quad-level phase detector and a linear frequency-locked loop based on a
linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in
0.18 üm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter
generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance
exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential
divide-by-eight injection-locked frequency divider with low power dissipation is presented.
The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It
has a maximum operating frequency of 18 GHz. The ratio of locking range over center
frequency is up to 50%. The prototype chip is implemented in 0.18 üm CMOS technology
and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques
of fully differential charge pumps are discussed. Techniques are proposed to minimize the
nonidealities associated with a fully differential charge pump, including differential
mismatch, output current variation, low-speed glitches and high-speed glitches. The
performance improvement brought by the techniques is verified with simulations of
schematics designed in 0.35 üm CMOS technology.
14
Parash, Par Nima. "Automotive Radar Demonstrator : Phase-locked loop and filterdesign." Thesis, Linköping University, Department of Science and Technology, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18937.
Full textAbstract:
As technique and requirement of today’s products keeps expending, Acreo AB has been researching for automotive radar that fulfills these requirements, e.g. higher resolution, faster system and lower cost.
The purpose of this master thesis work has been to evaluate a previous design and implement changes. The work has resulted in a PCB card that will be used to compare the performance between two radar modules. The demonstrator has been developed in two versions – first based on the existing GaAs-chipset (Gallium Arsenide) and a second with the inclusion of a low cost SiGe-chipset (Silicon Germanium).
The outcome of this work proves that some requirements cannot be fulfilled and therefore a next-generation radar demonstrator has been proposed. The new radar demonstrator includes changes that can fulfill the requirements.
15
Keregudadhahalli, Rajesh Kumar. "Costas PLL Loop System for BPSK Detection." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515.
Full text
16
Pardo, Gonzalez Mauricio. "MEMS-based phase-locked-loop clock conditioner." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/43643.
Full textAbstract:
Ultra narrow-band filters and the use of two loops in a cascade configuration dominate current clock conditioners based on phase-locked-loop (PLL) schemes. Since a PLL exhibits a low-pass transfer function with respect to the reference clock, the noise performance at very close-to-carrier offset frequencies is still determined by the input signal. Although better cleaning can be achieved with extremely narrow loops, an ultra low cut-off frequency could not be selected since the stability of the configuration deteriorates as the filter bandwidth is reduced. This fact suggests that a full-spectrum clock conditioning is not possible using traditional PLL architectures, and an alternative scheme is necessary to attenuate the very-close-to-carrier phase noise (PN). In addition, ultra-narrow loop filters can compromise on-chip integration because of the large size capacitors needed when chosen as passive. Input signal attenuation with relaxed bandwidth requirements becomes the main aspect that a comprehensive clock cleaner must address to effectively regenerate a reference signal.
This dissertation describes the Band-Reject Nested-PLL (BRN-PLL) scheme, a modified PLL-based architecture that provides an effective signal cleaning procedure by introducing a notch in the input transfer function through inner and outer loops and a high-pass filter (HPF). This modified response attenuates the reference-signal PN and reduces the size of the loop-filter capacitors substantially. Ultra narrow loops are no longer required because the notch size is related to the system bandwidth. The associated transfer function for the constitutive blocks (phase detectors and local oscillators) show that the output close-to-carrier and far-from-carrier PN sections are mainly dominated by the noise from the inner-PLL phase detector (PD) and local oscillator (LO) located in the outer loop, respectively. The inner-PLL PD transfer function maintains a low-pass characteristic with a passband gain inversely proportional to the PD gain becoming the main contribution around the carrier signal. On the other hand, the PN around the transition frequency is determined mainly by the reference and the inner-PLL LO. Their noise contributions to the output will depend on the associated passband local maxima, which is located at the BRN-PLL transition frequency. Hence, in this region, the inner-PLL LO is selected so that its effect can be held below that of the outer-PLL PD.
The BRN-PLL can use a high-Q MEMS-based VCO to further improve the transition region of the output PN profile and an LC-VCO as outer-PLL LO to reduce the noise floor of the output signal. In particular, two tuning mechanisms are explored for the MEMS-VCO: series tuning using varactors and phase shifting of a resonator operating in nonlinear regime. Both schemes are implemented to generate a tunable oscillator with no PN-performance degradation.
17
Tonucci, Elena. "Implementazione di un sistema ottimizzato per la stima della frequenza di segnali mediante Phase-Locked Loops." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/23522/.
Full textAbstract:
I Phase-Locked Loops sono sistemi che forniscono una stima coerente in fase del segnale in ingresso. In ambito di tracking radiometrico di sonde deep space, essi vengono utilizzati per la stima della frequenza residua, indispensabile per attuare le funzioni di navigazione, determinazione d’orbita e guida. Sebbene le loro prestazioni siano deteriorate da disturbi di diversa natura, essi sono a tutt’oggi lo strumento più impiegato per elaborare dati provenienti da esperimenti di radio scienza, tant’è che diversi studi hanno tentato negli anni di migliorare le loro prestazioni, mediante l’utilizzo di diverse tecniche.
Questa tesi ha l’obiettivo di implementare tramite MATLAB un sistema ottimizzato basato su PLL per la stima della frequenza dei segnali in uscita da sistemi di acquisizione open-loop. Partendo dai modelli numerici sviluppati in precedenza durante il tirocinio, si vogliono introdurre alcuni miglioramenti che riducano ulteriormente la misura dell’incertezza di stima, calcolata attraverso la radice dell’errore quadratico medio. A tale scopo, è stata introdotta una funzione di battimento del segnale stimato che fornisce un nuovo riferimento a frequenza costante. Ciò permettere al PLL di rielaborare nuovamente il segnale con bande di loop ottimizzate, le quali hanno la capacità di filtrare maggiormente il rumore termico del ricevitore, principale causa di disturbo per i segnali provenienti da sonde spaziali.
In questo elaborato è analizzato in dettaglio il processo di determinazione d’orbita in modo da definire il ruolo essenziale che i PLL svolgono in tale ambito. Successivamente, è analizzato lo stato dell’arte dei suddetti sistemi e i loro limiti, i quali giustificano il crescente interesse verso un loro perfezionamento. Infine, sono presentati estensivamente i modelli matematici sviluppati durante questo studio e i loro risultati per dimostrare che il sistema di battimento implementato migliora l’accuratezza della stima della frequenza dei segnali.
18
Choi, Jaehyouk. "Fully-integrated DLL/PLL-based CMOS frequency synthesizers for wireless systems." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/42698.
Full textAbstract:
A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important.
As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to the PLL-based synthesizer are still waiting for answers. This dissertation addresses key challenges related to fully integrated PLL-based frequency synthesizers, including the problem of large area consumption of passive components, the inherent reference-spur problem, and the problem of trade-offs between integer-N PLLs and fractional-N PLLs.
In this dissertation, new techniques and architectures are presented and developed to address those challenges. First, a low-phase-noise ring oscillator and a capacitor multiplier with a high-multiplication factor efficiently minimize the silicon area of sub-components, and a compact programmable delay-locked loop (DLL)-based frequency multiplier is developed to replace the PLL-based frequency synthesizer. Second, the charge-distribution mechanism for suppressing reference spurs is theoretically analyzed, and an edge interpolation technique for implementing the mechanism is developed. Finally, the concept and the architecture of sub-integer-N PLL is proposed and implemented to remove trade-offs between conventional integer-N PLLs and fractional-N PLLs.
19
Siqueira, Paulo de Tarso Dalledone. "Memória: preservação de características individuais e de grupo em sistemas coerentes formados pelo acoplamento de osciladores." Universidade de São Paulo, 2003. http://www.teses.usp.br/teses/disponiveis/43/43134/tde-20022014-142003/.
Full textAbstract:
O presente trabalho propõe-se a oferecer respostas à questão de como a informação é preservada num sistema, focalizando-se na distinção entre os papéis desempenhados pelos constituintes elementares e pelos estruturais na preservação da memória desse sistema. Os sistema simulados circunscreveram-se a malhas, com diferentes graus de regularidade, compostas pelo acoplamento de osciladores não-lineares que apresentam comportamento coerente no estado de equilíbrio. Malhas de Sincronismo de Fase, também conhecidas por PLLs (Phase Locked Loops), foram adotadas como elementos constituintes básicos dos sistemas analisados. Para tanto, utilizou-se a plataforma de cálculo MATLAB-SIMULINK, acompanhando-se as evoluções dos diversos sistemas e de seus parâmetros dinâmicos associados, possibilitando o estabelecimento da correspondência entre os valores dos referidos parâmetros dinâmicos com parâmetros gráficos \"sensíveis\" à estrutura das malhas. Os resultados obtidos indicam a coexistência/cooperação das componentes estrutural e elementar na determinação dos valores dos parâmetros dinâmicos no estado de equilíbrio do sistema. No entanto, evidencia-se que tais componentes apresentam importâncias distintas na determinação dos diferentes parâmetros dinâmicos.This work was conceived aiming to present some answers to how the information is preserved in a system. The focus was laid on the distinction between the tasks played by the elementary components and the structure of the system. The simulated systems were composed by coupled oscillators, more precisely by PLLs (Phase Locked Loops), arranged in networks of different regularities. Simulations were performed using Matlab-Simulink software to build a correlation between the final state dynamical parameters of the system and its degree of regularity. Results show the influence of both elementary and structural components on the system attained state. However the responses of characteristics parameters of the system to changes in the regularity of the structured network may greatly differ from one parameter to another. This behavior may suggest different strategies to preserve information of the system according to the information to be kept.
20
Bolucek, Muhsin Alperen. "Design And Implementation Of Low Phase Noise Phase Locked Loop Based Local Oscillator." Master's thesis, METU, 2009. http://etd.lib.metu.edu.tr/upload/12611353/index.pdf.
Full textAbstract:
In this thesis, a low phase noise local oscillator operating at 2210 MHz is designed and implemented to be used in X-Band transmitter of a LEO satellite. Designed local oscillator is a PLL (Phase Locked Loop) based frequency synthesizer which is implemented using discrete commercial components including ultra low noise voltage controlled oscillator and high resolution, low noise fractional-N synthesizer. Operational settings of the synthesizer are done using three wire serial interface of a microcontroller. Although there are some imperfections in the implementation, phase noise of the prototype system is pretty good which is measured as -123.2 dBc/Hz at 100 kHz offset and less than -141.3 dBc/Hz at 1 MHz offset.
Made up of discrete components, the VCO used in the designed local oscillator is not integrable to frequency synthesizer which is implemented in CMOS technology. Considering technological progress, integrabilitiy of system components becomes important for designing single chip complete systems like transmitters, receivers or transceivers. Therefore considering a potential single chip transceiver production, also a CMOS voltage controlled oscillator is designed using standard TSMC 0.18um technology operating in between 2.05 GHz and 2.35 GHz . Since low phase noise is the main concern, phase noise models and phase noise reduction techniques that are derived from the models are studied. These techniques are applied to the VCO core to see the effects. Design is finalized by applying some of those techniques which are found to be noticeably effective to the core design. Finalized core operates from 2.15 GHz to 2.25 GHz and phase noise is simulated as -107.265 dBc/Hz at 100 kHz offset and -131.167 dBc/Hz at 1 MHz offset. Also oscillator has figure of merit of -185.4 at 100 kHz offset. These values show that designed core is considerably good when compared to similar designs.
21
AraÃjo, Renato Guerreiro. "PLL (Phase-Locked Loop) structures for single phase and three phase systems with a high rejection capacity to sub and interharmonic." Universidade Federal do CearÃ, 2015. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=15882.
Full textAbstract:
CoordenaÃÃo de AperfeÃoamento de Pessoal de NÃvel SuperiorIn applications related to power converters, such as inverters, rectifiers and the use of active filters, the synchronization method represent a very important element in the performance of the control strategy of this equipment. The estimated values of the synchronism angle, frequency and amplitude determined by the synchronization algorithms present, facing strongly distorted signals with the presence of sub and interharmonics, high errors. This study presents two algorithms: one applied on single-phase electrical systems and one applied on three-phase electrical systems, with high immunity to interharmonics and subharmonics. First are presented the main synchronization systems that are used in the electrical power systems. In addition, will be presented the main causes and consequences of the presence of subharmonics and interharmnics in the system, as well as the mathematical modeling of the two algorithms with high rejection to these disturbances. Will be presented the simulation and the experimental results of the proposed algorithms and the comparison between these synchronization methods with particular methods present in the literature. As a result of the study, it can be seen that the proposed structures present a higher response time, but the error of the estimated signal with respect the fundamental component of the input signal is lower when compared to structures such as EPLL and structures based on SOGI. It was observed that the proposed synchronization methods are enabled to estimate the synchronism angle, the frequency and the fundamental component of the input signal adequately and can be used in control strategies of power converters.
Em aplicaÃÃes relacionadas à EletrÃnica de PotÃncia, como inversores, retificadores e a utilizaÃÃo de filtros ativos, o mÃtodo de sincronizaÃÃo representa um elemento chave no desempenho da estratÃgia de controle destes equipamentos. Os valores do Ãngulo de sincronismo, frequÃncia e amplitude estimados com determinados algoritmos de sincronizaÃÃo apresentam, diante de sinais fortemente distorcidos com a presenÃa de sub e inter-harmÃnicos, erros elevados. Neste trabalho sÃo apresentados dois algoritmos: um aplicado a sistemas elÃtricos monofÃsicos e outro aplicado a sistemas elÃtricos trifÃsicos, com elevada imunidade a inter-harmÃnicos e sub-harmÃnicos. Primeiramente sÃo apresentados os principais sistemas de sincronizaÃÃo utilizados em sistemas elÃtricos de potÃncia. AlÃm disso, sÃo apresentadas as principais causas e consequÃncias da presenÃa de sub-harmÃnicos e inter-harmÃnicos no sistema, bem como a modelagem matemÃtica dos dois algoritmos com elevada rejeiÃÃo a estes distÃrbios. SÃo apresentados os resultados de simulaÃÃo e experimentais dos algoritmos propostos e a comparaÃÃo entre estes mÃtodos de sincronizaÃÃo com determinados mÃtodos presentes na literatura. Como resultado do estudo, pode-se observar que as estruturas de sincronizaÃÃo propostas apresentam um tempo de resposta mais elevado, porÃm o erro do sinal estimado em relaÃÃo a componente fundamental do sinal de entrada à inferior quando comparado a estruturas como o EPLL e estruturas baseadas no SOGI. Com isso, tem-se que as mesmas estÃo habilitadas para estimar o Ãngulo de sincronismo, a frequÃncia e a componente fundamental do sinal de entrada adequadamente e podem serem utilizadas eficientemente em estratÃgias de controle de conversores de potÃncia.
22
Wali, Naveen, and Balamurali Radhakrishnan. "Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744.
Full textAbstract:
An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were studied and simulated. TheVernier delay based architecture and inverter delay based architecture was designedand evaluated. There architectures provided certain short comings whilethe pseudo-differential time-to-digital converter architecture was chosen, becauseof it’s less occupation of area. Since there exists a relationship between the sizeof the delay cells and it’s time resolution, the pseudo-differential time-to-digitalconverter severed it’s purpose. The whole time-to-digital converter system was tested on a 1 V power supply,reference frequency 54-MHz which is also the reference clock Fref , and a feedbackfrequency Fckv 2.1-GHz. The power consumption was found to be around 2.78mW without dynamic clock gating. When the clock gating or bypassing is done,the power consumption is expected to be reduced considerably. The measuredtime-to-digital converter resolution is around 7 ps to 9 ps with a load variation of15 fF. The inherent delay was also found to be 5 ps. The total output noise powerwas found to be -128 dBm.
23
Asghar, Malik Summair. "A “Divide-by-Odd Number” Injection-Locked Frequency Divider." Thesis, Linköpings universitet, Institutionen för systemteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-88014.
Full textAbstract:
The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.
24
Kippenberger, Roger Miles. "On Real Time Digital Phase Locked Loop Implementation with Application to Timing Recovery." Thesis, University of Canterbury. Electrical and Computer Engineering, 2006. http://hdl.handle.net/10092/1146.
Full textAbstract:
In digital communication systems symbol timing recovery is of fundamental importance. The accuracy in estimation of symbol timing has a direct effect on received data error rates. The primary objective of this thesis is to implement a practical Digital Phase Locked Loop capable of accurate synchronisation of symbols suffering channel corruption typical of modern mobile communications. This thesis describes an all-software implementation of a Digital Phase Locked in a real-time system. A timing error detection (TED) algorithms optimally implemented into a Digital Signal Processor. A real-time transmitter and receiver system is implemented in order to measure performance when the received signal is corrupted by both Additive White Gaussian Noise and Flat Fading. The Timing Error Detection algorithm implemented is a discrete time maximum likelihood one known as FFML1, developed at Canterbury University. FFML1 along with other components of the Digital Phase Locked loop are implemented entirely in software, using Motorola 56321 assembly language.
25
Lisboa, Alexandre Coutinho. "Controle de caos em PLL de terceira ordem." Universidade de São Paulo, 2009. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-02092009-100746/.
Full textAbstract:
Inicialmente, apresentam-se características de dispositivos eletrônicos conhecidos como PLLs (phase-locked loops). PLLs são amplamente empregados para se extrair sinais de tempo em canais de comunicação e em aplicações nas quais se deseja controle automático de freqüência. O objeto principal é estudar PLLs analógicos descritos por uma equação diferencial ordinária de terceira ordem. Assim, deduzem-se condições de estabilidade assintótica e identifica-se um regime de caos conservativo, que ocorre sob certas combinações de valores de parâmetros. Três métodos de controle não-linear/caótico são então apresentados e aplicados. Os métodos são os seguintes: o Método de Pyragas via realimentação de variável de estado; o Método de Pyragas com atraso temporal na realimentação; e o Método de Sinha, o qual efetua o controle perturbando um parâmetro do sistema. Simulações numéricas são levadas a cabo a fim de ilustrar o comportamento dinâmico do sistema quando sujeito à ação desses métodos. Este trabalho termina com um estudo de uma rede formada por uma cadeia de PLLs. Condições para soluções síncronas, periódicas e caóticas (dissipativas e conservativas) são deduzidas para tal rede.Firstly, features of electronic devices known as PLLs (Phase-Locked Loops) are presented. PLLs are widely employed to extract time signals in communication channels and in applications where automatic control of frequency is desired. The main goal is to study analog PLLs described by a third-order nonlinear ordinary differential equation. Thus, conditions for asymptotic stability are derived and a regime of conservative chaos occurring under certain combinations of parameter values is identified. Then, three methods of control of nonlinear/ chaotic dynamics are presented and applied. The methods are the following: the Pyragas method via feedback of state variable; the Pyragas method with time delay in the feedback; and the Sinhas method, which performs the control by disturbing a parameter of the system. Numerical simulations are accomplished in order to illustrate the dynamical behavior of the system when subjected to the action of these methods. This work ends with a study of a single-chain PLL network. Conditions for synchronous, periodic and chaotic (dissipative and conservative) solutions are derived for such a network.
26
Shen, Jue. "Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37212.
Full textAbstract:
With the advancement of CMOS process and fabrication, it has been a trend to maximize digital design while minimize analog correspondents in mixed-signal system designs. So is the case for PLL. PLL has always been a traditional mixed-signal system limited by analog part performance. Around 2000, there emerged ADPLL of which all the blocks besides oscillator are implemented in digital circuits. There have been successful examples in application of Bluetooth, and it is moving to improve results for application of WiMax and ad-hoc frequency hopping communication link. Based on the theoretic and measurement results of existing materials, ADPLL has shown advantages such as fast time-to-market, low area, low cost and better system integration; but it also showed disadvantages in frequency resolution and phase noise, etc. Also this new topic still opens questions in many researching points important to PLL such as tracking behavior and quantization effect. In this thesis, a non-linear phase domain model for all digital phase-locked loop (ADPLL) was established and validated. Based on that, we analyzed that ADPLL phase noise prediction derived from traditional linear quantization model became inaccurate in non-linear cases because its probability density of quantization error did not meet the premise assumption of linear model. The phenomena of bandwidth expansion and in-band phase noise decreasing peculiar to integer-N ADPLL were demonstrated and explained by matlab and verilog behavior level simulation test bench. The expression of threshold quantization step was defined and derived as the method to distinguish whether an integer-N ADPLL was in non-linear cases or not, and the results conformed to those of matlab simulation. A simplified approximation model for non-linear integer-N ADPLL with noise sources was established to predict in-band phase noise, and the trends of the results conformed to those of matlab simulation. Other basic analysis serving for the conclusions above covered: ADPLL loop dynamics, traditional linear theory and its quantitative limitations and numerical analysis of random number. Finally, a present measurement setup was demonstrated and the results were analyzed for future work.
27
Araújo, Renato Guerreiro. "Estruturas de PLL (Phase-Locked Loop) monofásica e trifásica com alta rejeição a sub e inter-harmônicas." reponame:Repositório Institucional da UFC, 2015. http://www.repositorio.ufc.br/handle/riufc/15474.
Full textAbstract:
ARAÚJO, R. G. Estruturas de PLL (Phase-Locked Loop) monofásica e trifásica com alta rejeição a sub e inter-harmônicas. 137 f. 2015. Dissertação (Mestrado em Engenharia Elétrica) - Centro de Tecnologia, Universidade Federal do Ceará, Fortaleza, 2015.Submitted by Marlene Sousa (mmarlene@ufc.br) on 2016-02-15T13:33:43Z No. of bitstreams: 1 2015_dis_rgaraujo.pdf: 4472806 bytes, checksum: e5fc0c7e779855fe380073eb2f4579f6 (MD5)
Approved for entry into archive by Marlene Sousa(mmarlene@ufc.br) on 2016-03-15T19:12:54Z (GMT) No. of bitstreams: 1 2015_dis_rgaraujo.pdf: 4472806 bytes, checksum: e5fc0c7e779855fe380073eb2f4579f6 (MD5)
Made available in DSpace on 2016-03-15T19:12:54Z (GMT). No. of bitstreams: 1 2015_dis_rgaraujo.pdf: 4472806 bytes, checksum: e5fc0c7e779855fe380073eb2f4579f6 (MD5) Previous issue date: 2015-11-18
In applications related to power converters, such as inverters, rectifiers and the use of active filters, the synchronization method represent a very important element in the performance of the control strategy of this equipment. The estimated values of the synchronism angle, frequency and amplitude determined by the synchronization algorithms present, facing strongly distorted signals with the presence of sub and interharmonics, high errors. This study presents two algorithms: one applied on single-phase electrical systems and one applied on three-phase electrical systems, with high immunity to interharmonics and subharmonics. First are presented the main synchronization systems that are used in the electrical power systems. In addition, will be presented the main causes and consequences of the presence of subharmonics and interharmnics in the system, as well as the mathematical modeling of the two algorithms with high rejection to these disturbances. Will be presented the simulation and the experimental results of the proposed algorithms and the comparison between these synchronization methods with particular methods present in the literature. As a result of the study, it can be seen that the proposed structures present a higher response time, but the error of the estimated signal with respect the fundamental component of the input signal is lower when compared to structures such as EPLL and structures based on SOGI. It was observed that the proposed synchronization methods are enabled to estimate the synchronism angle, the frequency and the fundamental component of the input signal adequately and can be used in control strategies of power converters.
Em aplicações relacionadas à Eletrônica de Potência, como inversores, retificadores e a utilização de filtros ativos, o método de sincronização representa um elemento chave no desempenho da estratégia de controle destes equipamentos. Os valores do ângulo de sincronismo, frequência e amplitude estimados com determinados algoritmos de sincronização apresentam, diante de sinais fortemente distorcidos com a presença de sub e inter-harmônicos, erros elevados. Neste trabalho são apresentados dois algoritmos: um aplicado a sistemas elétricos monofásicos e outro aplicado a sistemas elétricos trifásicos, com elevada imunidade a inter-harmônicos e sub-harmônicos. Primeiramente são apresentados os principais sistemas de sincronização utilizados em sistemas elétricos de potência. Além disso, são apresentadas as principais causas e consequências da presença de sub-harmônicos e inter-harmônicos no sistema, bem como a modelagem matemática dos dois algoritmos com elevada rejeição a estes distúrbios. São apresentados os resultados de simulação e experimentais dos algoritmos propostos e a comparação entre estes métodos de sincronização com determinados métodos presentes na literatura. Como resultado do estudo, pode-se observar que as estruturas de sincronização propostas apresentam um tempo de resposta mais elevado, porém o erro do sinal estimado em relação a componente fundamental do sinal de entrada é inferior quando comparado a estruturas como o EPLL e estruturas baseadas no SOGI. Com isso, tem-se que as mesmas estão habilitadas para estimar o ângulo de sincronismo, a frequência e a componente fundamental do sinal de entrada adequadamente e podem serem utilizadas eficientemente em estratégias de controle de conversores de potência.
28
Ögren, Jim. "PLL design for inverter grid connection : Simulations for ideal and non-ideal grid conditions." Thesis, Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-156145.
Full textAbstract:
In this report a phase locked loop (PLL) system for grid voltage phase tracking has been investigated. The grid voltage phase angle contains critical information for connecting a power plant, such as a wave energy converter, to the grid. A synchronous reference frame PLL system with PI-regulator gains calculated with the symmetrical optimum method has been designed and simulations in SIMULINK have been made. For ideal grid conditions the phase angle was tracked fast and accurate. For non-ideal conditions the phase angle was tracked but with less accuracy, due to slow dynamics of the system, but still within acceptable margins. In order to test this system further it has to be implemented in a control system and tested when connected to the grid.
29
Jiang, Bo. "A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration." ScholarWorks @ UVM, 2016. http://scholarworks.uvm.edu/graddis/562.
Full textAbstract:
The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the phase lock loop (PLL) frequency synthesizer. In order to access various standards, the frequency synthesizer needs to have wide frequency tuning range, fast tuning speed, and low phase noise and frequency spur. The traditional analog charge pump frequency synthesizer circuit design is becoming diffcult due to the continuous down-scalings of transistor feature size and power supply voltage. The goal of this project was to develop an all digital phase locked loop (ADPLL) as the alternative solution technique in RF transceivers by taking advantage of digital circuitry's characteristic features of good scalability, robustness against process variation and high noise margin. The targeted frequency bands for our ADPLL design included 880MHz-960MHz, 1.92GHz-2.17GHz, 2.3GHz-2.7GHz, 3.3GHz-3.8GHz and 5.15GHz-5.85GHz that are used by wireless communication standards such as GSM, UMTS, bluetooth, WiMAX and Wi-Fi etc.
This project started with the system level model development for characterizing ADPLL phase noise, fractional spur and locking speed. Then an on-chip jitter detector and parameter adapter was designed for ADPLL to perform self-tuning and self-calibration to accomplish high frequency purity and fast frequency locking in each frequency band. A novel wide band DCO is presented for multi-band wireless application. The proposed wide band adaptive ADPLL was implemented in the IBM 0.13µm CMOS technology. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was assessed and agrees well with the theoretical analysis.
30
Moberg, Caroline. "Development of measurement algorithm in an industrial PLC : An evaluation of DSOGI-PLL for real time measurements." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-388490.
Full textAbstract:
The aim of this project was to devise an algorithm for three phase AC power grid measurements that could be utilized in an excitation system for controlling generators. This application requires fast and accurate measurements even when the voltages in the power grid are characterized by unbalanced three-phase, frequency variations and harmonic distortions. Phase locked loop algorithms are used in grid synchronization techniques and are developed to withstand disturbances in the power grid. A DSOGI-PLL was implemented on a PLC and then evaluated. The DSOGI-PLL was tested with input voltages generated by a relay testing system. The result showed that the DSOGI-PLL could measure positive sequence component RMS and grid frequency of unbalanced three-phase voltages and voltages characterized by frequency variations and harmonic distortions. However, the measurements response time and accuracy did not meet the requirements for application in excitation systems.
31
Konečný, Tomáš. "Návrh fázového závěsu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217873.
Full text
32
Berenguer, Sau Jordi. "Síntesis de frecuencias en microondas mediante sistemas PLL: aplicación a la recepción de señales emitidas por satélite hasta 30 GHz." Doctoral thesis, Universitat Politècnica de Catalunya, 1988. http://hdl.handle.net/10803/6898.
Full textAbstract:
La tesi estudia el problema de la síntesi de freqüències en les bandes de freqüències de microones i ones mil·limètriques, i la seva aplicació al disseny dels oscil·ladors locals d'un receptor coherent per a la recepció de les *radiobalises que a 12, 20 i 30 GHz emetia el satèl·lit Olympus de l'Agència Espacial Europea (ESA), amb la finalitat de caracteritzar el comportament radioelèctric de l'atmosfera a aquestes freqüències, a partir de mesures d'atenuació i transpolarització sobre aquests senyals de test, tot això dintre del marc d'un experiment de propagació (OPEX) propiciat per l'agència.La tesi s'ha centrat en l'estudi dels sistemes de síntesis de freqüències utilitzats habitualment, i especialment en els de síntesi indirecta de freqüència basats en sistemes Phase Locked Loop (PLL) a freqüències de microones ja que són la base sobre la qual s'han dissenyat i construït els prototips de multiplicadors de freqüència que s'han desenvolupat, capaços de sintetitzar senyals en bandes de mil·limètriques, que en el nostre cas s'han restringit al marge de 1 a 29 GHz.
Alguns dels multiplicadors fan ús de la detecció de fase harmònica, sistema que permet realitzar multiplicacions de freqüència d'índex imparell, evitant la utilització de divisors de freqüència en el llaç de realimentació del PLL.
La tesi s'estructura en quatre parts diferenciades. La primera, amb un caire eminentment teòric, s'ofereix a manera de revisió dels aspectes del soroll de fase i dels sistemes de síntesis de freqüències existents. La segona part aborda les qüestions derivades de la síntesi de freqüències en microones mitjançant PLL's, amb descripció dels components utilitzats, per a passar a tractar dels aspectes de disseny d'un receptor coherent, els seus requisits i aplicacions. En la tercera part es presenten els multiplicadors de freqüència realitzats, la seva descripció, esquema de blocs i resultats experimentals obtinguts. I finalment, en la quarta part s'inclouen una sèrie de realitzacions derivades de la utilització de sistemes PLL a freqüències de microones, amb sincronització per injecció del VCO al senyal de referència, en aplicacions de combinació de potència i de control electrònic de fase en sistemes phased-arrays amb elements actius.
La tesis estudia el problema de la síntesis de frecuencias en las bandas de frecuencias de microondas y ondas milimétricas, y su aplicación al diseño de los osciladores locales de un receptor coherente para la recepción de las radiobalizas que a 12, 20 y 30 GHz emitía el satélite Olympus de la Agencia Espacial Europea (ESA), con la finalidad de caracterizar el comportamiento radioeléctrico de la atmósfera a estas frecuencias, a partir de medidas de atenuación y transpolarización sobre esas señales de test, todo ello dentro del marco de un experimento de propagación (OPEX) propiciado por la agencia.
La tesis se ha centrado en el estudio de los sistemas de síntesis de frecuencias utilizados habitualmente, y en especial en los de síntesis indirecta de frecuencia basados en sistemas Phase Locked Loop (PLL) a frecuencias de microondas puesto que son la base sobre la que se sustentan los prototipos de multiplicadores de frecuencia que se han desarrollado, capaces de sintetizar señales en bandas milimétricas, que en nuestro caso se han restringido al margen de 1 a 29 GHz.
Algunos de los multiplicadores hacen uso de la detección de fase armónica, sistema que permite realizar multiplicaciones de frecuencia de índice impar, evitando el empleo de divisores de frecuencia en el lazo de realimentación del PLL.
La tesis se estructura en cuatro partes diferenciadas. La primera, con un cariz eminentemente teórico, se ofrece a modo de revisión del tema del ruido de fase y de los sistemas de síntesis de frecuencias existentes. La segunda parte aborda las cuestiones derivadas de la síntesis de frecuencias en microondas mediante PLL's, con descripción de los componentes utilizados, para pasar a tratar de los aspectos de diseño de un receptor coherente, sus requisitos y aplicaciones. En la tercera parte se presentan los multiplicadores de frecuencia realizados, su descripción, esquema de bloques y resultados experimentales obtenidos. Y por último, en la cuarta parte se incluyen una serie de realizaciones derivadas de la utilización de sistemas PLL a frecuencias de microondas, con sincronización por inyección del VCO a la señal de referencia, en aplicaciones de combinación de potencia y de control electrónico de fase en sistemas phased-arrays con elementos activos.
The thesis studies the problem of the synthesis of frequencies in the microwave and millimeter waves frequency bands, and its application to the design of the local oscillators of a coherent receiver for the reception of the radio beacons that to 12, 20 and 30 GHz emitted the satellite Olympus from the European Space Agency (ESA), with the aim of characterizing the radio behavior of the atmosphere at these frequencies, from measurements of attenuation and transpolarisation on those signals of test, all that in the framework of a propagation experiment (OPEX) favored by the agency.
The thesis has been focused on the study of the frequency synthesis systems, and especially on the indirect frequency synthesis systems based on Phase Locked Loops (PLL) at microwave frequencies, since they are the base on which the prototypes of frequency multipliers that they have been developed, capable of synthesizing signals in millimeter bands, are held that in our case they have restricted regardless of 1 to 29 GHz.
Some of the multipliers make use of the harmonic phase detection system that allows carrying out frequency multiplications of odd index, preventing the use of frequency dividers in the feedback loop of the PLL.
The thesis is structured in four differentiated parts. The first, with an eminently theoretical look, offers like revision of the subject of the phase noise and the methods of frequency synthesis. The second part tackles the questions derived from the synthesis of frequencies in microwaves through PLL's, with description of the used components, to pass to deal of the aspects of design of a coherent receiver, its requirements and applications. In the third part the frequency multipliers carried out, its description, schema of blocks and obtained experimental results are presented. And finally, in the fourth part a series of accomplishments are included phased-arrays derived of the use of systems PLL at frequencies of microwaves, with synchronization by injection of the VCO to the reference signal, in applications of power combination and of electronic phase control in systems with active elements.
33
Gomes, Pedro Henrique de Castro. "Análise e síntese de um algoritmo “Phase-Locked Loop” robusto para estimação de amplitude, fase e freqüência de sinais elétricos." Universidade Federal de Juiz de Fora (UFJF), 2007. https://repositorio.ufjf.br/jspui/handle/ufjf/3807.
Full textAbstract:
Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-03-21T18:37:34Z
No. of bitstreams: 1
pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5)Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-03-22T12:40:06Z (GMT) No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5)
Made available in DSpace on 2017-03-22T12:40:06Z (GMT). No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5) Previous issue date: 2007-08-22
CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
A crescente demanda pelos consumidores por índices de qualidade de energia cada vez mais elevados e a recente desregulamentação do setor elétrico, vem exigindo uma demanda cada vez maior pelo monitoramento da qualidade da energia elétrica pelas concessionárias de uma maneira descentralizada. Aliado a esse fato, a alta proliferação de cargas não lineares conectadas à rede elétrica, entre outros, têm tornado a estimação de parâmetros dos sinais elétricos da rede uma tarefa cada vez mais desafiadora. Assim, o desenvolvimento de algoritmos de estimação eficientes e com baixa complexidade computacional, ou passíveis de implementação em sistemas (hardwares) de baixo custo, têm-se tornando uma prerrogativa importante. Nesse escopo, essa dissertação apresenta a descrição de uma malha de PLL (Phase-Locked-Loop) robusta (ER-QPLL), capaz de estimar os parâmetros (fase, freqüência e amplitude) da componente fundamental de um sinal de entrada qualquer. O desenvolvimento da estrutura baseou-se no aprimoramento de uma malha de PLL do tipo quadratura (QPLL), que estima os parâmetros da componente fundamental de um sinal de entrada através da aquisição das suas componentes em fase e em quadratura. As modificações da malha foram a introdução de um filtro notch adaptativo em sua entrada e a implementação de toda a estrutura utilizando o operador delta (δ), relacionado à Transformada Gama (γ). A introdução do filtro notch adaptativo na entrada da malha garante uma significativa melhoria na relação SNR do sinal de entrada, sem prejudicar demasiadamente a resposta dinâmica da estrutura. A característica adaptativa do filtro garante uma performance satisfatória da malha para sinais de entrada com parâmetros variantes no tempo. A implementação da malha utilizando o operador delta (δ) assegura uma performance ideal quando a mesma é implementada em sistemas de precisão limitada de, no mínimo, 16 bits. De acordo com os resultados demonstrados nesse trabalho, a performance da malha é satisfatória mesmo ao se utilizar altas taxas de amostragem relativas à freqüência de operação da malha. Finalmente, foi proposta uma implementação da malha em um microprocessador (DSP) da família TMS320, o que comprova a viabilidade de implementação da mesma em sistemas (hardware) de ponto fixo.
The always more restrictive energy quality benchmarks, pushed on by consumers, associated with the electric sector deregulamentation has been imposing the necessity, for the concessionaries, of a better and decentralized monitoring of energy electric quality. At the same time, the increase of nonlinear loads connected to the electric network, among other facts, has been increasing the complexities associated with this electric signals parameters estimation. So, the synthesis of efficient parameters estimation algorithms, with low computational effort and with easy implementation on low-cost hardware systems has becoming a priority for the energy quality area. Based on these assumptions, this work deals with the design and synthesis of a robust Phase-Locked-Loop (PLL) structure, more specifically an Enhanced Quadrature Phase-Locked-Loop (ER-QPLL) with capacity of estimate several parameters, more specifically phase, frequency and amplitude, from any input signal. The synthesis of this ER-QPLL structure was based on the enhancement of a Quadrature Phase-Locked-Loop (QPLL) that can estimate the parameters of the fundamental component of any input signal thought the information acquired with the acquisition of its phase and quadrature components. The enhancements of this QPLL structure were, basically, the introduction of a adaptive notch filter on its input, associated with an delta operator (δ), a tool of the gamma transformer (γ), for modeling the whole structure. A significant improvement in the SNR of the input signal, without degradation of the dynamic structure output, was achieved with the introduction of the notch filter. The adaptive characteristics of this notch filter can deal, in a very good way, with the non-stationery properties of the input signals. The structure implementation based on delta operator (δ) can assure an almost ideal performance for limited precision systems of, at least, 16 bits. According to the results obtained in this work, the performance of the proposed structure can be considered very good, even when dealing with high sampling rates relative to the network frequency operation. Finally, a structure based on a microprocessor DSP from TMS320 family was proposed and implemented showing its feasibility for fixed-point hardware.
34
Tiagaraj, Sathya Narasimman. "Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262041.
Full text
35
Finelli, Stefano. "Realizzazione di un sistema di stabilizzazione per laser a stato solido, per la generazione di luce squeezed in esperimenti di interferometria." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2015. http://amslaurea.unibo.it/8296/.
Full textAbstract:
Con questo lavoro di tesi si affrontano i primi accorgimenti sperimentali necessari alla realizzazione di un esperimento di ottica quantistica. L'attività svolta consiste nell'ottimizzazione dei parametri di un PLL (Phase-Locked Loop) che mantiene due laser agganciati in frequenza, e nella misura del rumore di fase presente nell'aggancio. Questa stabilizzazione costituisce il primo passo per la generazione di luce squeezed, associata a particolari stati del campo elettromagnetico. Grazie a quest'ultima, è possibile migliorare la sensibilità raggiungibile in esperimenti di interferometria di precisione, quali ad esempio quelli per la ricerca di onde gravitazionali. L'iniezione di luce squeezed costituirà infatti parte del prossimo upgrade dell'interferometro di Virgo.
36
Gao, Siyu. "Grid synchronisation of VSC-HVDC system." Thesis, University of Manchester, 2015. https://www.research.manchester.ac.uk/portal/en/theses/grid-synchronisation-of-vschvdc-system(6de14261-b0cd-4a82-bfb9-2ccaae012c4e).html.
Full textAbstract:
This thesis investigates issues affecting grid synchronisation of VSC-HVDC systems with particular regard to, but not limited to, offshore wind power generation during the complex but potentially serious behaviours following solar storms. An averaged value model (AVM) for the contemporary modular multilevel converter (MMC) based VSC-HVDC system is developed and is used in combination with different phase-locked loop (PLL) models and the unified magnetic equivalent circuit (UMEC) transformer model to assess the impacts of geomagnetically induced current (GIC) on grid synchronisation of an offshore VSC-HVDC system. GIC is DC current flowing in the earth caused by strong geomagnetic disturbance events. GIC enters the electric utility grid via the grounded transformer neutral and can cause severe saturation to transformers. This in turn causes disruptions to grid synchronisation. The main contribution of this thesis is that effects of GIC are studied using the UMEC transformer model, which can model saturation. The assessment leads to the development of enhanced fundamental positive sequence control (EFPSC) which is capable of reducing the stress on the system during GIC events. The methods developed can also be applied to other non-symmetrical AC events occurring in VSC-HVDC such as single-phase faults. Additional contributions of the thesis are:A mathematical model of the MMC is derived and forms the foundation of the AVM. The AVM is verified against a detailed equivalent-circuit-based model and shows good accuracy. The PLL is the essential component for grid synchronisation of VSC-HVDC system. Different PLLs are studied in detail. Their performance is compared both qualitatively and quantitatively. This appears to have been done for the first time systematically in the public literature. The UMEC model is verified using hand calculation. Its saturation characteristic is matched to a predefined B-H curve and is also verified. The verifications show that this model is capable of modelling transformer saturation and thus is suitable for this study. The consolidation of the AVM, PLL, UMEC, GIC and EFPSC provides an insight into the how the MMC based VSC-HVDC system behaves under severe geomagnetic disturbances and the possible methods to mitigate the risks and impacts to the power grid.
37
Scheibe, Niko. "Entwicklung einer monolithisch integrierten 2,44 GHz Phasenregelschleife in der LFoundry 150nm-CMOS Technologie." Master's thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-61765.
Full textAbstract:
Die Spezifikationen und Toleranzbereiche heutiger Hochgeschwindigkeitsdatenübertragungstechnologien nehmen immer weiter an Komplexität, aufgrund der steigenden Informationsmenge, zu. Zur Verarbeitung von Daten in Frequenzbereichen oberhalb von einem Gigahertz sind Referenzsignale notwendig, welche ein äußerst geringes Phasenrauschen aufweisen um benachbarte Kanäle nicht zu beeinflussen. Diese Referenzsignale werden in Mischerschaltungen zur Modulation oder Demodulation zwischen radio frequency (RF)- und intermediate frequency (IF)-Signalen verwendet. Die benötigte Signalform ist eine Sinusschwingung, die nicht durch digitale Schaltungsblöcke erzeugt werden kann. Daher ist die Notwendigkeit von analogen LC-Oszillatoren gegeben. Die Erzeugung von höchst stabilen und hochfrequenten Signalen war lange Zeit teuren Silizium-Germanium-Technologien vorbehalten. Jedoch erfordert der steigende Integrationsgrad und der hart umkämpfte Markt, die Entwicklung von RF-Schaltungen in günstigen CMOS-Technologien. In Zusammenarbeit mit der Landshut Silicon Foundry soll dazu eine monolithisch integrierte Phase-Locked Loop (PLL) mit einer mittleren Ausgangsfrequenz von 2,44 GHz und einem Phasenrauschen kleiner -115 dBc/Hz bei einem Abstand von 1 MHz vom Träger entwickelt werden. Dabei wird das Hauptaugenmerk auf den Kern der PLL gelegt, welcher einen spannungsgesteuerten Oszillator, einen Phasen-/Frequenzdetektor, eine Ladungspumpe, einen Schleifenfilter und einen Frequenzteiler beinhaltet. Außerdem sollen Testszenarien vorgestellt werden, um die Eigenschaften der gefertigten PLL zu bestimmen und zu vergleichen.
38
Marmo, Carlos Nehemy. "Sincronismo em redes mestre-escravo de via-única: estrela simples, cadeia simples e mista." Universidade de São Paulo, 2003. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-18022004-233234/.
Full textAbstract:
Neste trabalho, são estudados os problemas de sincronismo de fase nas redes mestre-escravo de via única (OWMS), nas topologias Estrela Simples, Cadeia Simples e mista, através da Teoria Qualitativa de Equações Diferenciais, com ênfase no Teorema da Variedade Central. Através da Teoria das Bifurcações, analisa-se o comportamento dinâmico das malhas de sincronismo de fase (PLL) de segunda ordem que compõem cada rede, frente às variações nos seus parâmetros constitutivos. São utilizadas duas funções de excitação muito comuns na prática: o degrau e a rampa de fase, aplicadas pelo nó mestre. Em cada caso, discute-se a existência e a estabilidade do estado síncrono. A existência de pontos de equilíbrio não-hiperbólicos, não permite uma aproximação linear, e nesses casos é aplicado o Teorema da Variedade Central. Através dessa rigorosa técnica de simplificação de sistemas dinâmicos é possível fazer uma aproximação homeomórfica em torno desses pontos, preservando a orientação no espaço de fases. Desse modo, é possível determinar, localmente, suas estabilidades.This work presents stability analysis of the syncronous state for three types of one-way master-slave time distribution network topologies: single star, single chain and both of them, mixed. Using bifurcation theory, the dynamical behavior of second-order phase-locked loops employed to extract the syncronous state in each node is analyzed in function of the constitutive parameters. Two usual inputs, the step and the ramp phase pertubations, are supposed to appear in the master node and, in each case, the existence and stability of the syncronous state are studied. For parameter combinations resulting in non hyperbolic synchronous states, the linear approximation does not provide any information, even about the local behaviour of the system. In this case, the center manifold theorem permits the construction of an equivalent vector field representing the asymptotic behaviour of the original system in the neighborhood of these points. Thus, the local stability can be determined.
39
Antunes, Richard Henrique Ribeiro. "Detecção e classificação de VTCDs em sistemas de distribuição de energia elétrica usando redes neurais artificiais." Universidade do Estado do Rio de Janeiro, 2012. http://www.bdtd.uerj.br/tde_busca/arquivo.php?codArquivo=3879.
Full textAbstract:
Fundação de Amparo à Pesquisa do Estado do Rio de JaneiroO objetivo deste trabalho é conhecer e compreender melhor os imprevistos no fornecimento de energia elétrica, quando ocorrem as variações de tensão de curta duração (VTCD). O banco de dados necessário para os diagnósticos das faltas foi obtido através de simulações de um modelo de alimentador radial através do software PSCAD/EMTDC. Este trabalho utiliza um Phase-Locked Loop (PLL) com o intuito de detectar VTCDs e realizar a estimativa automática da frequência, do ângulo de fase e da amplitude das tensões e correntes da rede elétrica. Nesta pesquisa, desenvolveram-se duas redes neurais artificiais: uma para identificar e outra para localizar as VTCDs ocorridas no sistema de distribuição de energia elétrica. A técnica aqui proposta aplica-se a alimentadores trifásicos com cargas desequilibradas, que podem possuir ramais laterais trifásicos, bifásicos e monofásicos. No desenvolvimento da mesma, considera-se que há disponibilidade de medições de tensões e correntes no nó inicial do alimentador e também em alguns pontos esparsos ao longo do alimentador de distribuição. Os desempenhos das arquiteturas das redes neurais foram satisfatórios e demonstram a viabilidade das RNAs na obtenção das generalizações que habilitam o sistema para realizar a classificação de curtos-circuitos.
The objective of this work is to know and understand the unforeseen in the supply of electricity, when there are short duration voltage variations (SDVV). The required databases for the diagnosis of faults were obtained through simulations of a model of radial feeder through software PSCAD/EMTDC. This work uses a Phase-Locked Loop (PLL) in order to detect and perform the estimation SDVV automatic frequency, phase angle and amplitude of the voltage and current from the power grid. This research is developing two artificial neural networks: one to identify and another to locate the SDVV occurred in the distribution system of electricity. The technique proposed here applies to three-phase feeders with unbalanced loads, which can have side extensions triphasic, biphasic and monophasic. In developing the same, it is considered that there is availability of measurements of voltages and currents at the node of the initial feeder and also in some points scattered along the distribution feeder. The performances of the architectures of neural networks were satisfactory and demonstrate the feasibility of ANNs in obtaining the generalizations that enables the system for the classification of short circuits.
40
Imran, Saeed Sohail. "Investigation of Mechanisms for Spur Generation in Fractional-N Frequency Synthesizers." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80886.
Full textAbstract:
With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.
41
Bouloc, Jeremy. "Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4307/document.
Full textAbstract:
Un microscope à force atomique (AFM) est utilisé pour caractériser des matériaux isolant ou semi-conducteur avec une résolution pouvant atteindre l'échelle atomique. Ce microscope est constitué d'un capteur de force couplé à une électronique de contrôle pour pouvoir correctement caractériser ces matériaux. Parmi les différents modes (statique et dynamique), nous nous focalisons essentiellement sur le mode dynamique et plus particulièrement sur le fonctionnement sans contact à modulation de fréquence (FM-AFM). Dans ce mode, le capteur de force est maintenu comme un oscillateur harmonique par le système d'asservissement. Le projet ANR Pnano2008 intitulé : ”Cantilevers en carbure de silicium à piézorésistivité métallique pour AFM dynamique à très haute fréquence" a pour objectif d'augmenter significativement les performances d'un FM-AFM en développant un nouveau capteur de force très haute fréquence. Le but est d'augmenter la sensibilité du capteur et de diminuer le temps nécessaire à l'obtention d'une image de la surface du matériau. Le système de contrôle associé doit être capable de détecter des variations de fréquence de 100mHz pour une fréquence de résonance de 50MHz. Etant donné que les systèmes présents dans l'état de l'art ne permettent pas d'atteindre ces performances, l'objectif de cette thèse fut de développer un nouveau système de contrôle. Celui-ci est entièrement numérique et il est implémenté sur une carte de prototypage basée sur un FPGA. Dans ce mémoire, nous présentons le fonctionnement global du système ainsi que ses caractéristiques principales. Elles portent sur la détection de l'écart de fréquence de résonance du capteur de forceAn atomic force microscope (AFM) is used to characterize insulating materials or semiconductors with a resolution up to the atomic length scale. The microscope includes a force sensor linked to a control electronic in order to properly characterize these materials. Among the various modes (static and dynamic), we focus mainly on the dynamic mode and especially on the frequency modulation mode (FM-AFM). In this mode, the force sensor is maintained as a harmonic oscillator by the servo system. The research project ANR Pnano2008 entitled: "metal piezoresistivity silicon carbide cantilever for very high frequency dynamic AFM" aims to significantly increase the performance of a FM-AFM by developing new very high frequency force sensors. The goal is to increase the sensitivity of the sensor and to decrease the time necessary to obtain topography images of the material. The control system of this new sensor must be able to detect frequency variations as small as 100mHz for cantilevers with resonance frequencies up to 50MHz. Since the state-of-the-art systems doe not present these performances, the objective of this thesis was to develop a new control system. It is fully digital and it is implemented on a FPGA based prototyping board. In this report, we present the system overall functioning and its main features which are related to the cantilever resonant frequency detection. This detection is managed by a phase locked loop (PLL) which is the key element of the system
42
Hallal, Ayman. "Génération d'ondes millimétriques et submillimétriques sur des systèmes fibrés à porteuses optiques stabilisées." Thesis, Rennes 1, 2017. http://www.theses.fr/2017REN1S005/document.
Full textAbstract:
Je rapporte dans ce manuscrit une étude théorique et expérimentale d’une source compacte, fiable et bas coût d’ondes électromagnétiques continues et cohérentes de 30 Hz de largeur de raie, accordables de 1 GHz à 500 GHz par pas de 1 GHz. Ces ondes sont générées par un photo-mélange de deux diodes lasers DFB (Distributed Feedback) très accordables autour de 1550 nm, stabilisées avec des polarisations orthogonales sur une même cavité Fabry-Perot optique fibrée. J’ai conçue des électroniques de correction très rapides pour chaque laser permettant d’avoir une bande passante d’asservissement de 7 MHz limitée par la longueur de la boucle. Je démontre des suppressions de bruit de phase jusqu’à -60 dBc/ Hz à 1 kHz et de -90 dBc/Hz à 100 kHz d’écart d’une porteuse électrique à 92 GHz. Je mesure aussi une dérive de fréquence de ~170 kHz d’un battement à 10 GHz à long terme sur 7,5 heures de verrouillage continu. Je montre une conception optimisée d’une boucle d’asservissement intégrée de quelques dizaines de cm de longueur qui réduit le bruit de phase de 18 dB à 1 MHz d’écart à la porteuse optique et des couplages phase-amplitude réduits dans la cavité d’un facteur 50 par rapport à ceux estimés expérimentalement. L’ajout d’un troisième laser DFB stabilisé en phase sur un oscillateur local permettrait d’avoir une source continûment accordable sur 1 THz. La source d’ondes continues permettrait également de générer à partir de fibres hautement non linéaires et dispersives des impulsions pico- ou femtosecondes à un taux de répétition fixe en remplacement les lasers DFB par des lasers plus stables. Je calcule par simulation une gigue temporelle de 7,2 fs sur un temps d’intégration de 1 ms à 40 GHz de taux de répétitionI report in this manuscript a theoretical and experimental study of a compact, reliable and low cost source of 30 Hz linewidth, continuous and coherent electromagnetic waves tunable from 1 GHz to 500 GHz in steps of 1 GHz. These waves are generated by photomixing two distributed feedback (DFB) laser diodes at 1550 nm which are frequency stabilized with orthogonal polarizations on the same optical fibered Fabry-Perot cavity. I have designed very fast electronic control filters for each laser allowing a 7 MHz servo bandwidth limited by the loop length. I demonstrate phase noise suppressions down to -60 dBc/Hz at 1 kHz and -90 dBc/Hz at 100 kHz offset frequencies from a 92 GHz electrical carrier. I also measure a ~170 kHz frequency drift of the beat note at 10 GHz on the long term over a continuous 7.5 hour locking period. I show an optimized design of an integrated servo loop of few tens of cm length which reduces the phase noise by 18 dB at 1 MHz optical carrier offset frequency and the phase-amplitude couplings in the cavity by a factor of 50 compared to the experimental one. The addition of a third DFB laser phase stabilized on a local oscillator allows the possibility to have continuously tunable source over 1 THz. The continuous wave source also makes it possible to generate fixed repetition rate pico- or femtosecond pulses from highly non-linear and dispersive fibers, replacing the DFB lasers by further stable lasers. I have calculated by simulation 7.2 fs temporal jitter at 40 GHz repetition rate over a 1 ms integration time
43
Souza, José Renato Cozzolino Rodrigues de. "Um estudo sobre o desempenho de algoritmos de estimação de frequência visando unidades de medição fasorial." Niterói, 2017. https://app.uff.br/riuff/handle/1/3936.
Full textAbstract:
Submitted by Patrícia Cerveira (pcerveira1@gmail.com) on 2017-06-12T18:19:03Z
No. of bitstreams: 1
José Renato Cozzolino.pdf: 2923143 bytes, checksum: 2941736082bf50938fdb3dcfea03c36e (MD5)Approved for entry into archive by Biblioteca da Escola de Engenharia (bee@ndc.uff.br) on 2017-07-03T13:30:54Z (GMT) No. of bitstreams: 1 José Renato Cozzolino.pdf: 2923143 bytes, checksum: 2941736082bf50938fdb3dcfea03c36e (MD5)
Made available in DSpace on 2017-07-03T13:30:54Z (GMT). No. of bitstreams: 1 José Renato Cozzolino.pdf: 2923143 bytes, checksum: 2941736082bf50938fdb3dcfea03c36e (MD5)
A estimação correta de frequência é essencial para a operação de diversos equipamentos de proteção, regulação e controle, os quais são necessários para operação adequada do Sistema Interligado Nacional A tecnologia de Sistemas de Medição Fasorial Sincronizada (Synchronized Phasor Measurement Systems - SPMS), baseia-se em uma rede de Unidades de Medição Fasorial (Phase Measurement Unit - PMU). Duas grandezas importantes medidas pela PMUs são a frequência e a taxa de variação da frequência. Este trabalho apresenta o resultado de estudo comparativo de algoritmos de estimação de frequência no âmbito de medição fasorial sincronizada. Foram avaliados os modelos propostos originalmente pela Norma IEEE C37.118, por seu documento de alteração ( IEEE Std. C37.118.1a-2014 Amendment), alem de três diferentes tipos de algoritmos baseados em PLLs (Phasor Locked Loop). As avaliações foram executadas com base nos testes descritos na Norma IEEE C37.118 e seus respectivos requisitos de conformidade. Verificou-se que as modificações apresentadas pelo documento Amendment foram necessárias para que o modelo de PMU proposto atendesse os requisto para todos os testes. Em relação aos modelos de PLL, verificou-se que uma versão do algoritmo (chamada aqui de PLL de Classe III) foi bem superior às demais e também melhor que o algoritmo sugerido pelo Amendment no que se refere ao teste de derivada da frequência e de modulação de fase.
An accurate frequency estimation is essential for the operation of Electric Power System regarding protection and control. Synchronized Phasor Measurement Systems - SPMS are based on a network composed by Phasor Measurement Units (Phase Measurement Unit - PMU). Two important parameters measured by the PMUs are the frequency and the frequency rate of change. This paper presents the results of a comparative study of frequency estimation algorithms within synchronized phasor measurement context. The reference model proposed in by IEEE C37.118 standard was compared with three different algorithms based on PLLs (Phasor Locked Loop). The evaluations were performed based on the compliance requirements described in IEEE C37.118. It was also found that the PLLs models have superior performance than model reference for P PMU suggested by Standard. Regarding the reference model for PMU M, there is a need to implement anti-aliasing filters for the standard inter-harmonics tests. After that, it was observed that the dynamic performances of PLLs studied at work are compatible with the algorithms suggested by the standard for the PMU M.
44
Kunyosi, Marcos Kleber Soares. "Método para determinação dos pesos sinápticos em uma rede de PLLs reconhecedora de imagens." Universidade Presbiteriana Mackenzie, 2006. http://tede.mackenzie.br/jspui/handle/tede/1492.
Full textAbstract:
Made available in DSpace on 2016-03-15T19:38:09Z (GMT). No. of bitstreams: 1
Marcos Kleber Soares Kunyosi.pdf: 2418852 bytes, checksum: ab6795f8d39445430da1eca23e865c56 (MD5)
Previous issue date: 2006-09-11Instituto Presbiteriano Mackenzie
Recognition of patterns can be performed by using neural networks built with oscillators, like phase-locked loops (PLLs). These networks are modeled with differential equation systems and can be studied by using Dynamical System Theory, which is used in this work in order to investigate the dynamical behavior related to a synaptic configuration of a neural network. As a result of such an investigation, two methods (Brute Force and Algebric) that help to build neural networks formed by PLLs are presented. These methods aim to relate the synaptic configuration of the network to the corresponding basin of attraction of fixed points, which represent the stored patterns on the network. Also general properties of synaptic configuration are presented in order to generate other useful configurations. Then a model of an image recognition machine able to store in its memory a monochromatic image and able to determine if other image is similar to the memorized one is proposed.
Reconhecimento de padrões pode ser feito usando redes neurais construídas com osciladores, como malhas de sincronismo de fase (PLLs). Essas redes são modeladas por sistemas de equações diferenciais e podem ser estudas pela Teoria de Sistemas Dinâmicos, que é usada neste trabalho para investigar o comportamento dinâmico associado a uma configuração sináptica de uma rede neural. Como resultado dessa investigação, são apresentados dois métodos (Força Bruta e Algébrico) que auxiliam na construção de redes neurais formadas por PLLs. Esses métodos têm como objetivo relacionar a configuração sináptica da rede às respectivas bacias de atração de pontos atratores, os quais representam os padrões memorizados na rede. Também são apresentadas propriedades gerais da configuração sináptica que podem ser usadas para compor outras configurações de interesse. Por fim, é proposto um modelo de máquina reconhecedora de imagem capaz de armazenar em sua memória uma figura monocromática e determinar se uma imagem qualquer apresentada a ela é semelhante à memorizada.
45
Olivarez, Nathan. "Mitigating the Effects of Ionospheric Scintillation on GPS Carrier Recovery." Digital WPI, 2013. https://digitalcommons.wpi.edu/etd-theses/245.
Full textAbstract:
Ionospheric scintillation is a phenomenon caused by varying concentrations of charged particles in the upper atmosphere that induces deep fades and rapid phase rotations in satellite signals, including GPS. During periods of scintillation, carrier tracking loops often lose lock on the signal because the rapid phase rotations generate cycle slips in the PLL. One solution to mitigating this problem is by employing decision-directed carrier recovery algorithms that achieve data wipe-off using differential bit detection techniques. Other techniques involve PLLs with variable bandwidth and variable integration times. Since nearly 60% of the GPS signal repeats between frames, this thesis explores PLLs utilizing variable integration times and decision-directed algorithms that exploit the repeating data as a training sequence to aid in phase error estimation. Experiments conducted using a GPS signal generator, software radio, and MATLAB scintillation testbed compare the bit error rate of each of the receiver models. Training-based methods utilizing variable integration times show significant reductions in the likelihood of total loss of lock.
46
Gdeisat, Munther Ahmad. "Fringe pattern demodulation using digital phase locked loops." Thesis, Liverpool John Moores University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.521754.
Full text
47
Souder, William Dai Foster. "A low power 10 GHz phase locked loop for radar applications implemented in 0.13 um SiGe technology." Auburn, Ala, 2009. http://hdl.handle.net/10415/1631.
Full text
48
Ratcliff, Marcus Dai Foster. "Phase locked loop analysis and design." Auburn, Ala, 2008. http://hdl.handle.net/10415/1452.
Full text
49
Veillette, Benoît R. "On-chip characterization of charge-pump phase-locked loops." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0017/NQ44617.pdf.
Full text
50
Stockmaster, Michael. "Tracking of multiple sinusoids using coupled phase-locked loops." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1412945248.
Full text