Journal articles: 'PLL Phase locked loops'

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Niezrecki, C., and H. H. Cudney. "Structural Control Using Analog Phase-Locked Loops." Journal of Vibration and Acoustics 119, no. 1 (January 1, 1997): 104–9. http://dx.doi.org/10.1115/1.2889677.

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A study of the application of the phase-locked loop (PLL) to modal control of mechanical structures is performed. An analog PLL circuit is used to control the vibration of a cantilevered beam with piezoelectric sensors and actuators. By using the PLL controller, strain rate feedback is provided within a narrow and distinct frequency range about the fourth mode of the beam. The controller ignores all other modes and does not affect the phase outside of the frequency range. The PLL controller provides a simple, inexpensive, and effective method to control an individual structural mode or set of modes without causing spillover.

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Lei, Feiran, and Marvin H. White. "Reference Injected Phase-Locked Loops (PLL-RIs)." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 7 (July 2017): 1651–60. http://dx.doi.org/10.1109/tcsi.2017.2668298.

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Zhai, Bingcong. "Understanding of the Coherent Demodulation with Phase-Locked Loop." MATEC Web of Conferences 176 (2018): 01028. http://dx.doi.org/10.1051/matecconf/201817601028.

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The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way. Therefore, more and more attentions have been paid to the research and application of all digital phase-locked loops. This paper serves as an introduction about the basic background of PLL, the basic characteristics and structure of PLL, and the basic principles of modulation and demodulation. It provides a concise application about the basic principle and main design process of modulation and demodulation of FSK signal, which are realized by using phase-locked loop chip NE564.

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Tsyrulnikova, L. A., B. P. Sudeev, and A. R. Safin. "Wave Analogs of Media Based on Phase Locked Loops." Journal of the Russian Universities. Radioelectronics 23, no. 3 (July 21, 2020): 32–40. http://dx.doi.org/10.32603/1993-8985-2020-23-3-32-40.

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Introduction. At present, phase locked loops (PLLs) are widely used: from optimal signal detection and frequency synthesis to automatic control of phase distribution in phased scanned arrays. One of the simplest structures is a multi-stage (chain) PLL, which may contain a specially selected multi-connected control circuit. Such cascaded PLLs have wide application in solving a number of tasks of the theory of optimal estimates, multi-position phase telegraphy, in synchronizing of many tunable generators while preserving specified phase relations between their oscillations, etc. PLLs are actively used in radio physics both in analog and digital versions. One of the promising directions for collective PLLs development is the study of ensembles of neuromorphic networks based on PLL. Aim. To obtain wave analogues characterizing the collective PLL not as a discrete network, but as a continuous (distributed) media. Materials and methods. An unidirectional model (without mutual control circuits) of the cascade structure of the PLL. Results. Wave analogues of cascade-coupled phase synchronization systems that do not contain mutual control circuits were found. A solution of equations of wave analogues was found. A proof of validity of the obtained approximate solution in comparison with the exact one was presented. Conclusion. It was shown that by selecting a filter in a control circuit of each single-circuit circuit with different transmission coefficients, it is possible to obtain various types of continuous media or wave analogues of chain structures based on phase synchronization systems.

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Ahissar, Ehud. "Temporal-Code to Rate-Code Conversion by Neuronal Phase-Locked Loops." Neural Computation 10, no. 3 (April 1, 1998): 597–650. http://dx.doi.org/10.1162/089976698300017683.

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Peripheral sensory activity follows the temporal structure of input signals. Central sensory processing uses also rate coding, and motor outputs appear to be primarily encoded by rate. I propose here a simple, efficient structure, converting temporal coding to rate coding by neuronal phase-locked loops (PLL). The simplest form of a PLL includes a phase detector (that is, a neuronal-plausible version of an ideal coincidence detector) and a controllable local oscillator that are connected in a negative feedback loop. The phase detector compares the firing times of the local oscillator and the input and provides an output whose firing rate is monotonically related to the time difference. The output rate is fed back to the local oscillator and forces it to phase-lock to the input. Every temporal interval at the input is associated with a specific pair of output rate and time difference values; the higher the output rate, the further the local oscillator is driven from its intrinsic frequency. Sequences of input intervals, which by definition encode input information, are thus represented by sequences of firing rates at the PLL's output. The most plausible implementation of PLL circuits is by thalamocortical loops in which populations of thalamic “relay” neurons function as phase detectors that compare the timings of cortical oscillators and sensory signals. The output in this case is encoded by the thalamic population rate. This article presents and analyzes the algorithmic and the implementation levels of the proposed PLL model and describes the implementation of the PLL model to the primate tactile system.

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Shepherd, Paul, Ashfaqur Rahman, Shamim Ahmed, A. Matt Francis, Jim Holmes, and H. Alan Mantooth. "500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000076–83. http://dx.doi.org/10.4071/hitec-tp15.

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Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.

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Rashed, Mohamed, Christian Klumpner, and Greg Asher. "Dynamic phasor analysis and design of phase-locked loops for single phase grid connected converters." COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 34, no. 4 (July 6, 2015): 1122–43. http://dx.doi.org/10.1108/compel-04-2014-0090.

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Purpose – The purpose of the paper is to introduce the dynamic phasor modelling (DPM) approach for stability investigation and control design of single-phase phase-locked loops (PLLs). The aim is to identify the system instabilities not predicted using the existent analysis and design methods based on the simplified average model approach. Design/methodology/approach – This paper starts by investigating the performance of three commonly used PLL schemes: the inverse park-PLL, the second-order generalised integrators (SOGI)-frequency-locked loop and the enhanced-PLL, designed using the simplified average model and will show that following this approach, there is a mismatch between their actual and desired transient performance. A new PLL design method is then proposed based on the DPM approach that allows the development of fourth-order DPM models. The small-signal eigenvalues analysis of the fourth-order DPM models is used to determine the control gains and the stability limits. Findings – The DPM approach is proven to be useful for single-phase PLLs stability analysis and control parameters design. It has been successfully used to design the control parameters and to predict the PLL stability limits, which have been validated via simulation and experimental tests consisting of grid voltage sag, phase jump and frequency step change. Originality/value – This paper has introduced the use of DPM approach for the purpose of single-phase PLL stability analysis and control design. The approach has enabled accurate control gains design and stability limits identification of single-phase PLLs.

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Burgos-Mellado, Claudio, Alessandro Costabeber, Mark Sumner, Roberto Cárdenas-Dobson, and Doris Sáez. "Small-Signal Modelling and Stability Assessment of Phase-Locked Loops in Weak Grids." Energies 12, no. 7 (March 30, 2019): 1227. http://dx.doi.org/10.3390/en12071227.

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This paper proposes a low-complexity small signal model for a 3-leg converter connected to a balanced three-phase, three-wire weak grid and synchronised to this grid using a PLL implemented in a synchronous rotating d-q axis. A thorough analysis of the system stability as a function of the PLL bandwidth and the short circuit ratio (SCR) of the grid is performed based on a linearised model. By using the proposed model, an improved design process is proposed for the commonly used dq-PLL that accounts for the potential stability issues which may occur in weak grids. Using the proposed approach, it is possible to optimise the PLL design to find the fastest PLL that can operate stably considering the SCR of the grid. In addition, the proposed model is very simple, resulting in a straightforward design tool that could also be used for online stability monitoring. The method is validated through simulations and experimental results from a 5kW laboratory system.

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Osmany, S. A., F. Herzel, K. Schmalz, and W. Winkler. "Phase noise and jitter modeling for fractional-N PLLs." Advances in Radio Science 5 (June 13, 2007): 313–20. http://dx.doi.org/10.5194/ars-5-313-2007.

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Abstract. We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filtered by the PLL operation. We express the rms phase error (jitter) in terms of phase noise of the reference, the VCO phase noise and the third-order loop filter parameters. In addition, we consider OFDM systems, where the PLL phase noise is reduced by digital signal processing after down-conversion of the RF signal to baseband. The rms phase error is discussed as a function of the loop parameters. Our model drastically simplifies the noise optimization of the PLL loop dynamics.

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Imran, Rajib, Monirul Islam, and Abdullah Al Kafi. "Synthesizable Digital Phase Locked Loop Implementation." Advanced Materials Research 684 (April 2013): 317–21. http://dx.doi.org/10.4028/www.scientific.net/amr.684.317.

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Phase locked loop (PLL) is a very common circuit in the most of the electrical devices. The systems where needed clock or data recovery or frequency synthesis, PLL is the most cost effective and efficient choice that from cellular phone in our hands to the computers, televisions, radios and a different controller, PLL is everywhere. Due to ever increasing growth of the digital systems especially in the wireless communication, the Digital PLL (DPLL) has been developed to overcome the disadvantages of analog techniques such as large noise, power hungry, parameter sensitivity etc. Besides DPLL provides faster lock-in time, better testability, stability and portability over different process. The most of the resources available discussed about the theoretical model of the DPLL which is not synthesizable, that’s why a model is presented here keeping in mind that must be fully digital and synthesizable. The proposed PLL structure is fully digital, has the design flexibility with reduced hardware, low power consumption and higher power efficiency.

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Musch, T. "Broadband suppression of phase-noise with cascaded phase-locked-loops for the generation of frequency ramps." Advances in Radio Science 1 (May 5, 2003): 37–41. http://dx.doi.org/10.5194/ars-1-37-2003.

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Abstract. The generation of analogue frequency ramps with non-fractional phase-locked-loops (PLL) is a cost effective way of linearising varactor controlled oscillators (VCO). In case that the VCO shows a high phase-noise level, a single non-fractional PLL is not able to suppress the phase-noise of the VCO sufficiently. The reason for this is the limited loopbandwidth of the PLL. In the field of precise measurements a high phase-noise level is mostly not tolerable. Examples of VCO-types with an extremely high phase noise level are integrated millimetre wave oscillators based on GaAs-HEMT technology. Both, a low quality factor of the resonator and a high flicker-noise corner frequency of the transistors are the main reason for the poor phase-noise behaviour. On the other hand this oscillator type allows a cost effective implementation of a millimetre-wave VCO. Therefore, a cascaded two-loop structure is presented that is able to linearise a VCO and additionally to reduce its phase-noise significantly.

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Piqueira, José Roberto C. "Master-Slave Topologies with Phase-Locked Loops." Wireless Communications and Mobile Computing 2020 (February 21, 2020): 1–12. http://dx.doi.org/10.1155/2020/2727805.

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Since phase-locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, being the essential element to recover frequency and phase information. As the technology developed, PLL appeared in several applications, such as, dense communication networks, smart grids, electronic instrumentation, computational clusters, and integrated circuits. In all of these practical cases, isolated or networked PLLs are responsible for recovering the correct time basis and synchronizing the processes. According to the application needs, different clock distribution strategies were developed, with the master-slave being the simplest and most used choice. Considering that the master clock is obtained from a stable periodic oscillator, two topologies are studied: one-way, not considering clock feedback; and two-way master-slave, with the slave nodes providing clock feedback to the master. Here, these two cases are studied by using simulation strategies, presenting results about the clock signal recovery process in the presence of disturbances, indicating that master-slave clock distribution networks can be useful for networks with few nodes and a stable master oscillator with the one-way topology presenting better results than the two-way arrangement.

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R, Prithiviraj, and Selvakumar J. "Non-Linear Mathematical Modelling for Phase Locked Loop." International Journal of Engineering & Technology 7, no. 4.10 (October 2, 2018): 81. http://dx.doi.org/10.14419/ijet.v7i4.10.20710.

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Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.

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Wiegand, C., C. Hedayat, and U. Hilleringmann. "Non-linear behaviour of charge-pump phase-locked loops." Advances in Radio Science 8 (October 1, 2010): 161–66. http://dx.doi.org/10.5194/ars-8-161-2010.

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Abstract. The analysis of the mixed analogue and digital structure of charge-pump phase-locked loops (CP-PLL) is a challenge in modelling and simulation. In most cases the system is designed and characterized using its continuous linear model or its discrete linear model neglecting its non-linear switching behaviour. I.e., the time-varying model is approximated by a time-invariant representation using its average dynamics. Depending on what kind of phase detector is used, the scopes of validity of these approximations are different. Here, a preeminent characterization and simulation technique based on the systems event-driven feature is presented, merging the logical and analogue inherent characteristics of the system. In particular, the high-grade non-linear locking process and the dead-zone are analyzed.

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Ince, Mehmet, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, Leroy Winemberg, and Sule Ozev. "Fault-based Built-in Self-test and Evaluation of Phase Locked Loops." ACM Transactions on Design Automation of Electronic Systems 26, no. 3 (February 2021): 1–18. http://dx.doi.org/10.1145/3427911.

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With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

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Roncagliolo, Pedro A., Javier G. García, and Carlos H. Muravchik. "Optimized Carrier Tracking Loop Design for Real-Time High-Dynamics GNSS Receivers." International Journal of Navigation and Observation 2012 (June 3, 2012): 1–18. http://dx.doi.org/10.1155/2012/651039.

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Carrier phase estimation in real-time Global Navigation Satellite System (GNSS) receivers is usually performed by tracking loops due to their very low computational complexity. We show that a careful design of these loops allows them to operate properly in high-dynamics environments, that is, accelerations up to 40 g or more. Their phase and frequency discriminators and loop filter are derived considering the digital nature of the loop inputs. Based on these ideas, we propose a new loop structure named Unambiguous Frequency-Aided Phase-Locked Loop (UFA-PLL). In terms of tracking capacity and noise resistance UFA-PLL has the same advantages of frequently used coupled-loop schemes, but it is simpler to design and to implement. Moreover, it can keep phase lock in situations where other loops cannot. The loop design is completed selecting the correlation time and loop bandwidth that minimize the pull-out probability, without relying on typical rules of thumb. Optimal and efficient ways to smooth the phase estimates are also presented. Hence, high-quality phase measurements—usually exploited in offline and quasistatic applications—become practical for real-time and high-dynamics receivers. Experiments with fixed-point implementations of the proposed loops and actual radio signals are also shown.

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Radwan, Eyad, Khalil Salih, Emad Awada, and Mutasim Nour. "Modified phase locked loop for grid connected single phase inverter." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (October 1, 2019): 3934. http://dx.doi.org/10.11591/ijece.v9i5.pp3934-3943.

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Connecting a single-phase or three-phase inverter to the grid in distributed generation applications requires synchronization with the grid. Synchronization of an inverter-connected distributed generation units in its basic form necessitates accurate information about the frequency and phase angle of the utility grid. Phase Locked Loop (PLL) circuit is usually used for the purpose of synchronization. However, deviation in the grid frequency from nominal value will cause errors in the PLL estimated outputs, and that’s a major drawback. Moreover, if the grid is heavily distorted with low order harmonics the estimation of the grid phase angle deteriorates resulting in higher oscillations (errors) appearing in the synchronization voltage signals. This paper proposes a modified time delay PLL (MTDPLL) technique that continuously updates a variable time delay unit to keep track of the variation in the grid frequency. The MTDPLL is implemented along a Multi-Harmonic Decoupling Cell (MHDC) to overcome the effects of distortion caused by gird lower order harmonics. The performance of the proposed MTDPLL is verified by simulation and compared in terms of performance and accuracy with recent PLL techniques.

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Zhao, Lei, Lei Shi, and Congying Zhu. "New Nonlinear Second-Order Phase-Locked Loop with Adaptive Bandwidth Regulation." Electronics 7, no. 12 (November 23, 2018): 346. http://dx.doi.org/10.3390/electronics7120346.

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Synchronization of large acquisition bandwidth brings great challenges to the traditional second-order phase-locked loop (PLL). To address the contradiction between acquisition bandwidth and noise suppression capability of the traditional PLL, a new second-order PLL coupled with a nonlinear element is proposed. The proposed nonlinear second-order PLL regulates the loop noise bandwidth adaptively by the nonlinear module. When a large input–output phase error occurs, this PLL reduces the frequency offset quickly by taking advantage of the large bandwidth. When the phase error is reduced by the loop control, the proposed PLL suppresses noises by using the small bandwidth to increase the tracking accuracy. Simulation results demonstrate that the tracking speed of the proposed PLL is increased considerably, and its acquisition bandwidth is increased to 18.8 kHz compared with that of the traditional second-order PLL (4 kHz).

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Wang, Chua-Chin, Yu-Tsun Chien, and Ying-Pei Chen. "A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop." VLSI Design 11, no. 2 (January 1, 2000): 107–13. http://dx.doi.org/10.1155/2000/52658.

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In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL) limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The paper presents a targeted 5.0V 500 MHz PLL which is implemented by a 0.6 um 1P3M digital CMOS technology. The features of the proposed design include a load-optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, thus, is reduced to 72.693 ps at 600 MHz at the presence of supply noise, while the sensitivity is limited to 286.6 ps/V. This high-noise immunity design allows that the PLL can be integrated with digital circuits.

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DE ALMEIDA, MARCONI O., EDUARDO T. F. SANTOS, and JOSÉ M. ARAÚJO. "IMPROVED PERFORMANCE PHASE DETECTOR FOR MULTIPLICATIVE SECOND-ORDER PLL SYSTEMS USING DEFORMED ALGEBRA." Journal of Circuits, Systems and Computers 23, no. 01 (January 2014): 1450008. http://dx.doi.org/10.1142/s021812661450008x.

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Phase-locked loops (PLL) is a phase and/or frequency tracking system, widely used in communication and control systems. The sinusoidal multiplicative type PLL still remains a recurrent model, due the fact that its derivation is originated from the maximum likelihood approach. In this note, it is showed as a generalized product, called q-product, which can be used to implement the phase detector and improve some important parameters of the PLL system, as the block linearity and pull-in characteristics. Numerical examples are presented in order to illustrate the proposal.

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PATEL, GOVIND S., and S. SHARMA. "PREDICTING THE JITTER OF PLL–DLL BASED FREQUENCY SYNTHESIZERS." International Journal of Wavelets, Multiresolution and Information Processing 12, no. 02 (March 2014): 1450016. http://dx.doi.org/10.1142/s0219691314500167.

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Phase Lock Loop (PLL) and Delay Locked Loops (DLLs) are major analog circuits used for many different communication applications such as frequency synthesizer, radio, computer, clock generation and recovery, global positioning system etc. This paper developed a methodical approach to calculate jitter of the PLL and DLL. The methodological nature of our approach would manifest itself in the development of a clear step-by-step procedure for the design of the constituent components of the same. Finally, jitter of DLL has been reduced by proposed technique.

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Pinheiro, Ricardo Bressan, and José Roberto C. Piqueira. "Designing All-Pole Filters for High-Frequency Phase-Locked Loops." Mathematical Problems in Engineering 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/682318.

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Since the phase-locked loop (PLL) circuit was proposed in the 1930s, it is being used for a lot of situations when precise frequency and phase references are required. Among these applications, synchronous telecommunication networks experienced a strong development in order to support the explosive information traffic that the modern society demands. Consequently, bandwidth became a decisive parameter, implying higher and higher frequencies for the clock signals exchanged between the nodes of the networks and detected by PLLs. The necessity to improve clock precision that follows the bandwidth increase provoked the improvement of the filter component of the PLLs, avoiding instability and high-frequency components in the reference signals. Here, a technique of designing this kind of filter is presented, considering second-order filters, implying third-order PLLs. Simulations show that following this technique produces very fast tracking processes, enabling precise operation even for very high frequencies.

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Li, Peng, Tian Tian, Bin Wu, and Tianchun Ye. "A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications." Electronics 10, no. 17 (August 27, 2021): 2077. http://dx.doi.org/10.3390/electronics10172077.

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This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

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Cai, Zhi Kuang, Kai Huang, Jun Yang, and Long Xing Shi. "Built-In Self-Test Scheme for All-Digital Phase-Locked Loops." Advanced Materials Research 546-547 (July 2012): 922–27. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.922.

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This paper presents a low-cost Built-In Self-Test (BIST) scheme, which is based on the principle of parity check code. The proposed circuit is consisted of a XOR network, a frequency decrease module, a BIST controller and a fault detector module. Different from the previous methods of PLL BIST, digital signals from the divide-by-N are grouped as transmission codes, and parity check codes are produced synchronously by the BIST controller. Then the results of parity checking are imported to the fault detector and final test results are generated. Purely digital design flow is adopted and hybrid faults models are used to evaluate the efficiency of the circuit. Experimental results indicates that the proposed method can provide the highest test coverage and lower area overhead, which are 98.3% and 4.2%, respectively.

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CHAU, YAWGENG A., and CHEN-FENG CHEN. "ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS." Journal of Circuits, Systems and Computers 20, no. 06 (October 2011): 1037–49. http://dx.doi.org/10.1142/s0218126611007748.

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The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. An example is given to illustrate the design procedure and simulation results are presented to validate the adaptive characteristics with respect to the phase noise and varying bands of input frequency.

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Luo, Zhibin, Jicheng Ding, and Lin Zhao. "Adaptive Gain Control Method of a Phase-Locked Loop for GNSS Carrier Signal Tracking." International Journal of Antennas and Propagation 2018 (2018): 1–14. http://dx.doi.org/10.1155/2018/6841285.

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The global navigation satellite system (GNSS) has been widely used in both military and civil fields. This study focuses on enhancing the carrier tracking ability of the phase-locked loop (PLL) in GNSS receivers for high-dynamic application. The PLL is a very popular and practical approach for tracking the GNSS carrier signal which propagates in the form of electromagnetic wave. However, a PLL with constant coefficient would be suboptimal. Adaptive loop noise bandwidth techniques proposed by previous researches can improve PLL tracking behavior to some extent. This paper presents a novel PLL with an adaptive loop gain control filter (AGCF-PLL) that can provide an alternative. The mathematical model based on second- and third-order PLL was derived. The error characteristics of the AGCF-PLL were also derived and analyzed under different signal conditions, which mainly refers to the different combinations of carrier phase dynamic and signal strength. Based on error characteristic curves, the optimal loop gain control method has been achieved to minimize tracking error. Finally, the completely adaptive loop gain control algorithm was designed. Comparable test results and analysis using the new method, conventional PLL, FLL-assisted PLL, and FAB-LL demonstrate that the AGCF-PLL has stronger adaptability to high target movement dynamic.

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Harb, Bassam, Mohammad Qudah, Ibrahim Ghareeb, and Ahmad Harb. "Chaos and bifurcation in time delayed third order phase-locked loop." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (April 1, 2021): 1431. http://dx.doi.org/10.11591/ijece.v11i2.pp1431-1438.

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In this paper, the modern nonlinear theory is applied to a third order phase locked loop (PLL) with a feedback time delay. Due to this delay, different behaviors that are not accounted for in a conventional PLL model are identified, namely, oscillatory instability, periodic doubling and chaos. Firstly, a Pade approximation is used to model the time delay where it is utilized in deriving the state space representation of the PLL under investigation. The PLL under consideration is simulated with and without time delay. It is shown that for certain loop gain (control parameter) and time delay values, the system changes its stability and becomes chaotic. Simulations show that the PLL with time delay becomes chaotic for control parameter value less than the one without time delay, i.e, the stable region becomes narrower. Moreover, the chaotic region becomes wider as time delay increases.

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Abbas, Waseem, Zubair Mehmood, and Munkyo Seo. "A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS." Electronics 9, no. 9 (September 13, 2020): 1502. http://dx.doi.org/10.3390/electronics9091502.

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A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.

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Prinzie, Jeffrey, Jorgen Christiansen, Paulo Moreira, Michiel Steyaert, and Paul Leroux. "Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology." EPJ Web of Conferences 170 (2018): 01021. http://dx.doi.org/10.1051/epjconf/201817001021.

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This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and high-energy physics application. An experimental circuit has been fabricated and irradiated with Xrays up to 600 Mrad. Heavy ions with an LET between 3.2 and 69.2 MeV.cm2/mg were used to verify the SEU cross section of the devices. A Two-photon Absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. The presented circuit employs TMR in the digital logic and an asynchronous phase-frequency detector (PFD) is presented. The PLL has a ringand LC-oscillator to be compared experimentally. The circuit has been fabricated in a 65 nm CMOS technology.

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Vukadinović, Dinko, Tien Duy Nguyen, Cat Ho Nguyen, Nhu Lan Vu, Mateo Bašić, and Ivan Grgić. "Hedge-Algebra-Based Phase-Locked Loop for Distorted Utility Conditions." Journal of Control Science and Engineering 2019 (March 3, 2019): 1–17. http://dx.doi.org/10.1155/2019/3590527.

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This paper presents the first application of the hedge-algebra theory in the field of grid synchronization. For this purpose, an optimized hedge-algebra controller (HAC) is developed and incorporated within the three-phase phase-locked loop (PLL) with moving average filters (MAFs) inside its feedback loop. Optimized fuzziness parameters and linguistic rule base of the HAC are obtained by a genetic algorithm using the integral of absolute error as the performance index during optimization. Calculated optimal parameter values of the HAC depend on the most frequently occurring disturbance in the electric grid. Two different PLL structures are proposed, depending on the types of disturbances occurring in the electric grid. The first structure is the conventional synchronous reference frame PLL with the nonadaptive MAF (i.e., MAF without order adjustment), but with the PI/PID controller in the phase loop replaced by the developed HAC. Such PLL structure is suitable for all analyzed disturbance types, expect for step-changes in the grid frequency. The second PLL structure introduces the adaptive MAF (i.e., MAF with order adjustment) and a new feedback signal in the output stage of the controller to achieve zero steady-state error in the case of step-changes in the grid frequency. The disturbance rejection capability of the two developed PLLs with the HAC (HAC-PLLs) is tested separately and compared experimentally with the PID- and fuzzy-controller-based PLLs.

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Setiawan, Iwan, Mochammad Facta, Ardyono Priyadi, and Mauridhi Hery Purnomo. "Estimator Parameter Tegangan Jaringan Tiga Fasa Berbasis D-SOGI PLL." Majalah Ilmiah Teknologi Elektro 16, no. 2 (August 31, 2017): 84. http://dx.doi.org/10.24843/mite.2017.v16i02p15.

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Phase locked loop (PLL) adalah sebuah sistem umpan balik yang memegang peran penting dalam sistem-sistem konverter terkoneksi jaringan listrik. Fungsi utama PLL adalah mendapatkan beragam informasi parameter jaringan yaitu seperti phase dan magnitude tegangan. Informasi-informasi tersebut selanjutnya digunakan sebagai dasar proses sinkronisasi peralatan dengan jaringan listrik. Tujuan utama paper ini adalah memodelkan sekaligus membandingkan unjuk kerja salah satu jenis PLL yang dikenal dengan nama Dual Second Order Generalized Integrator Phase-Locked Loop dengan SRF-PLL yaitu sebuah PLL yang relatif standar. Berdasarkan hasil simulasi, unjuk kerja D-SOGI PLL dalam keadaan tunaknya lebih unggul dibandingkan SRF-PLL terutama untuk kondisi jaringan listrik tiga phase tidak seimbang.

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Fereidountabar, Amirhossein, Gian Carlo Cardarilli, and Marco Re. "High Dynamic Optimized Carrier Loop Improvement for Tracking Doppler Rates." Journal of Electrical and Computer Engineering 2015 (2015): 1–6. http://dx.doi.org/10.1155/2015/679505.

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Mathematical analysis and optimization of a carrier tracking loop are presented. Due to fast changing of the carrier frequency in some satellite systems, such as Low Earth Orbit (LEO) or Global Positioning System (GPS), or some planes like Unmanned Aerial Vehicles (UAVs), high dynamic tracking loops play a very important role. In this paper an optimized tracking loop consisting of a third-order Phase Locked Loop (PLL) assisted by a second-order Frequency Locked Loop (FLL) for UAVs is proposed and discussed. Based on this structure an optimal loop has been designed. The main advantages of this approach are the reduction of the computation complexity and smaller phase error. The paper shows the simulation results, comparing them with a previous work.

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WOO, YOUNGSHIN, YOUNG MIN JANG, and MAN YOUNG SUNG. "A NOVEL METHOD FOR HIGH-PERFORMANCE PHASE-LOCKED LOOP." Journal of Circuits, Systems and Computers 13, no. 01 (February 2004): 53–63. http://dx.doi.org/10.1142/s0218126604001271.

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In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5 μm CMOS technology with 5 V supply voltage.

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Adesina, Naheem Olakunle, and Ashok Srivastava. "Memristor-Based Loop Filter Design for Phase Locked Loop." Journal of Low Power Electronics and Applications 9, no. 3 (July 29, 2019): 24. http://dx.doi.org/10.3390/jlpea9030024.

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The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.

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Hamood, Mostafa A., Ognjen Marjanovic, and Joaquin Carrasco. "Adaptive Impedance-Conditioned Phase-Locked Loop for the VSC Converter Connected to Weak Grid." Energies 14, no. 19 (September 23, 2021): 6040. http://dx.doi.org/10.3390/en14196040.

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In this paper, an adaptive version of the impedance-conditioned phase-locked loop (IC-PLL), namely the adaptive IC-PLL (AIC-PLL), is proposed. The IC-PLL has recently been proposed to address the issue of synchronisation with a weak AC grid by supplementing the conventional synchronous reference frame phase-locked loop (SRF-PLL) with an additional virtual impedance term. The resulting IC-PLL aims to synchronise the converter to a remote and stronger point in the grid, hence increasing the upper bound on the achievable power transfer achieved by the VSC converter connected to the weak grid. However, the issue of the variable grid strength imposes another challenge in the operation of the IC-PLL. This is because the IC-PLL requires impedance estimation methods to estimate the value of the virtual impedance part. In AIC-PLL, the virtual impedance part is estimated by appending another dynamic loop in the exciting IC-PLL. In this method, an additional closed loop is involved so that the values of the virtual inductance and resistance are internally estimated and adapted. Hence, the VSC converter becomes effectively viable for the case of the grid strength variable, where the estimation of the grid impedance becomes unnecessary. The results show that the converter that relies on AIC-PLL has the ability to transfer power that is approximately equal to the theoretical maximum power while maintaining satisfactory dynamic performance.

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Harb, Bassam A., Ahmad Al-Ajlouni, and Ali Eyadeh. "A Collocation-Based Algorithm for Analyzing Bifurcations in Phase Locked Loops with Tanlock and Sawtooth Phase Detectors." Mathematical Problems in Engineering 2018 (July 4, 2018): 1–7. http://dx.doi.org/10.1155/2018/8532546.

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Analysis of bifurcation of second-order analog phase locked loop (PLL) with tanlock and sawtooth phase detectors is investigated. Both qualitative and quantitative analyses are carried out. Qualitatively, the basin boundaries of the attractors were constructed by plotting the stable and the unstable manifolds of the system. The basin boundaries show that the PLL under consideration for certain loop parameters has a separatrix cycle which terminates the limit cycle (out-of-lock state) and the loop pulls-in. This behavior is known in literature as homoclinic bifurcation and the value of the bifurcation parameter where this process occurs is called the pull-in range. Quantitatively, we propose a collocation-based algorithm to compute the separatrix cycle and the pull-in range. The separatrix cycle is approximated by a finite set of harmonics N with unknown amplitudes and by utilizing the fact that this limit cycle bifurcates from a separatrix cycle, a system of nonlinear algebraic equations is derived. For given values of filter parameters and gain, the algorithm numerically solves for the unknown amplitude of the harmonics and the value of the pull-in range simultaneously by evaluating the system at the collocation points. Results demonstrate that phase locked loop with sawtooth phase detector characteristics has the wider pull-in range followed by tanlock and sinusoidal, respectively.

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Lee, Tzung-Je, and Chua-Chin Wang. "A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators." VLSI Design 2008 (September 24, 2008): 1–8. http://dx.doi.org/10.1155/2008/512946.

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A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper. Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively. By using separate regulators, the area and the power consumption of the regulator can be reduced. Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise. The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process. The peak-to-peak jitter (P2P jitter) of the proposed PLL is measured to be 81.8 ps at 80 MHz when a 250 mVrms supply noise is added. By contrast, the P2P jitter is measured to be 118.2 ps without the two regulators when the same supply noise is coupled.

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Fan, Sheng Wen, Chun Yu Zheng, Zheng Xi Li, and Chun Xue Wen. "A Study of Phase-Locked Technology of Wind Power Generation Three-Phase Grid-Connected Inverter." Advanced Materials Research 383-390 (November 2011): 3449–55. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.3449.

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This paper presents two phase-locked methods of wind power generation three-phase grid-connected inverter. First establishes the mathematical model of the inverter, on this basis analyzes why the power voltage phase must be known. And then studies the direct calculation method in α-β coordinates, and analyzes the shortcomings of this approach for three-phase imbalance; then focusing on the phase locked loop (PLL) approach in d-q coordinate system. To solve dynamic response problem of the PLL, a new signal delay cancellation method is put forward. With this improved method, the PLL can have a better performance. Experimental results show that the theoretical analysis is real.

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Liu, L., and C. Liu. "Deliberations about three-phase PLL technologies applied to a grid control of the renewable power system." Bulletin of the Polish Academy of Sciences Technical Sciences 63, no. 1 (March 1, 2015): 261–67. http://dx.doi.org/10.1515/bpasts-2015-0030.

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Abstract An efficient phase locked loop (PLL) method is very important to improve the grid-connected efficiency and the locked speed of frequency, phase, and voltage. However, most of literatures only introduce one PLL or one modified PLL method. There are many grid faults due to the grid connection to the renewable power generating system. A comparison and analysis is very important to select the most effective PLL technology for the grid-connected control of the renewable power system. Three PLL technologies are compared at different grid faults, such as single phase voltage drop, two phase voltage drop, frequency deviation, and voltage distortion. Simulation results indicated that different PLL methods have different locked performances at different grid faults.

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Jaeschke, T., C. Bredendiek, M. Vogt, and N. Pohl. "Fractional-N PLL based FMCW sweep generator for an 80 GHz radar system with 24.5 GHz bandwidth." Advances in Radio Science 10 (September 18, 2012): 7–11. http://dx.doi.org/10.5194/ars-10-7-2012.

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Abstract. A phase-locked loop (PLL) based frequency synthesizer capable of generating highly linear broadband frequency sweeps as signal source of a high resolution 80 GHz FMCW radar system is presented. The system achieves a wide output range of 24.5 GHz starting from 68 GHz up to 92.5 GHz. High frequencies allow the use of small antennas for small antenna beam angles. The wide bandwidth results in a radar system with a very high range resolution of below 1.5 cm. Furthermore, the presented synthesizer provides a very low phase noise performance of −80 dBc/Hz at 80 GHz carrier frequency and 10 kHz offset, which enables high precision distance measurements with low range errors. This is achieved by using two nested phase-looked loops with high order loop filters. The use of a fractional PLL divider and a high phase frequency discriminator (PFD) frequency assures an excellent ramp linearity.

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Liu, Yang, and Yan Bo Zhu. "A FLL-PLL Cooperative GNSS Weak Signal Tracking Framework." Applied Mechanics and Materials 551 (May 2014): 470–77. http://dx.doi.org/10.4028/www.scientific.net/amm.551.470.

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Navigation signals should be steadily tracked to allow the extraction of navigation information, and support the calculation of navigation solution. Generally, extraction of navigation information is realized by GNSS tracking loops, which need to implement two critical operations: 1) tracking parameters should be precisely estimated in order to reliably decode the navigation message. 2) Successive tracking method of navigation information. This paper proposes a novel tracking framework using dynamic FLL assisting PLL strategy and a loop state detection monitor. The new framework extends traditional phase and delay locked loop (PLL/DLL) tracking framework, and contributions mainly lie in two parts. A dynamic framework for parameters adjustment is proposed to avoid tracking failure due to the change of environment, which is complemented in a FLL-PLL cooperative framework. Experimental results demonstrate the advantages of our algorithm compared with standard PLL/DLL framework. It is shown that the algorithm proposed is more suitable for tracking under signal attenuation situation, while maintaining high performance at the same time.

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42

Ghaderi, Noushin, Hamid Reza Erfani-jazi, and Mehdi Mohseni-Mirabadi. "A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods." Journal of Electrical and Computer Engineering 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/8202581.

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A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a0.18 μmCMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly.

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Moroń, J., M. Firlej, and M. Idzik. "Development of low power Phase-Locked Loop (PLL) and PLL-based serial transceiver." Journal of Instrumentation 7, no. 01 (January 26, 2012): C01099. http://dx.doi.org/10.1088/1748-0221/7/01/c01099.

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Charlamov, J., and R. Navickas. "Phase Locked Loop Integrated System." Solid State Phenomena 164 (June 2010): 221–26. http://dx.doi.org/10.4028/www.scientific.net/ssp.164.221.

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CMOS-MEMS integration is an indispensable technique for self-calibration of electromechanical performance to make MEMS devices independent on environmental drift or fabrication errors. The goal of single-chip integration (the “holy grail” for the semiconductor timing industry) would be to include the resonator, the oscillator, the PLL and a temperature compensation circuit (TCC) on a single silicon substrate. The current structure of silicon MEMS-based devices utilizes a stacked-die arrangement, housed in a multi-chip package [1]. MEMS-based timing circuits often use PLLs, which can succumb to phase jitter and noise at higher timing frequencies. The architecture of a charge pump phase locked loop (CPPLL) is proposed in this work. It is discussed how its functional blocks influence the overall system performance. We have performed voltage-controlled oscillator (VCO) phase noise analysis and have determined the relationship between CPPLL and VCO phase noises and have discussed the requirements and results of the accomplished design.

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CHANG, ROBERT C., LUNG-CHIH KUO, and HOU-MING CHEN. "A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP." Journal of Circuits, Systems and Computers 14, no. 05 (October 2005): 997–1006. http://dx.doi.org/10.1142/s0218126605002738.

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A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

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Jwo, Dah-Jing. "Investigation of Phase-Locked Loop Statistics via Numerical Implementation of the Fokker–Planck Equation." Applied Sciences 10, no. 7 (April 10, 2020): 2625. http://dx.doi.org/10.3390/app10072625.

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The goal of this paper is to explore the effect of various parameters on the information geometric structure of the phase-locked loop (PLL) statistics, both transient and stationary. Comprehensive treatment on the behavior of PLL statistics will be given. The behavior of the phase-error statistics of the first-order PLL, in the presence of additive white Gaussian noise (WGN) is investigated through solving the differential equations known as the Fokker–Planck (FP) equation using the implicit Crank–Nicolson finite-difference method. The PLL is one of the most commonly used circuits in electrical engineering. A full knowledge of probability density functions (PDFs) of the phase-error statistics becomes essential in understanding the PLLs. Several illustrative examples are presented to provide profound insights on understanding the PLL statistics both qualitatively and quantitatively. Results covered include the transient and stationary statistics for the nonmodulo-2π probability density function, modulo-2π probability density function, and cycle slipping density function, of the phase error. Various numerical settings of PLL parameters are involved, including the detuning factor and signal-to-noise ratio (SNR). The results presented in this paper elucidate the link between various parameters and the information geometry of the phase-error statistics and form a basis for future investigation on PLL designs.

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Yu, Byeong-Jae, and Hyun-Mook Cho. "A Design of PLL for 6 Gbps Transmitter in Display Interface Application." Journal of IKEEE 17, no. 1 (March 30, 2013): 16–21. http://dx.doi.org/10.7471/ikeee.2013.17.1.016.

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Musengimana, Antoine, Haoyu Li, Xuemei Zheng, and Yanxue Yu. "Small-Signal Model and Stability Control for Grid-Connected PV Inverter to a Weak Grid." Energies 14, no. 13 (June 29, 2021): 3907. http://dx.doi.org/10.3390/en14133907.

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This paper presents a small signal stability analysis to assess the stability issues facing PV (photovoltaic) inverters connected to a weak grid. It is revealed that the cause of the transient instabilities, either high-frequency or low-frequency oscillations, is dominated by the outer control loops and the grid strength. However, most challenging oscillations are low-frequency oscillations induced by coupling interaction between the outer loop controller and PLL (Phase-Locked Loop) when the inverter is connected to a weak grid. Therefore, the paper proposes a low-frequency damping methodology in order to enhance the high system integration, while maintaining the stability of the system. The control method uses a DC link voltage error to modulate the reference reactive current. The proposed control reduces the low-frequency coupling between the DVC (DC link voltage controller), AVC (AC voltage controller) and PLL (Phase-locked loop). According to this study’s results, the performance capability of the grid-connected PV inverter is improved and flexibility in the outer loop controller design is enhanced. The control strategy proposed in this paper is tested using the PLECS simulation software (Plexim GmbH, Zurich Switzerland) and the results are compared with the conventional method.

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Long, Yingwen, and Yuhong Sun. "A New PLL Simulation Validation for Three-phase Grid under Heavy Distorted Conditions." International Journal of Online Engineering (iJOE) 11, no. 7 (August 31, 2015): 37. http://dx.doi.org/10.3991/ijoe.v11i7.4765.

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The precision of phase-locked loop (PLL) has a direct effect on the output performance for three-phase grid-connected inverter or three-phase active PFC. In this paper, a new three-phase digital closed-loop phase-locked algorithm is proposed on the basis of synchronous reference frame transformation. Synchronous simulation of the PLL techniques is a good choice even if the polluted three-phase grid such as the harmonics, phase jump and unbalance. Finally, MATLAB digital simulation results prove that the proposed PLL can fast and accurately track the positive sequence fundamental components of three-phase grid voltage.

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Du, Heng, Qiuye Sun, Qifu Cheng, Dazhong Ma, and Xu Wang. "An Adaptive Frequency Phase-Locked Loop Based on a Third Order Generalized Integrator." Energies 12, no. 2 (January 19, 2019): 309. http://dx.doi.org/10.3390/en12020309.

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In this paper, the basic principle and characteristics of a phase-locked loop (PLL) in a single phase grid-connected system are analyzed, and this paper introduces one type virtual orthogonal voltage vector method based on a third order generalized integrator (TOGI) to construct an alpha and beta static coordinate system. The TOGI structure can eliminate the DC offset in a voltage signal or zero offset in the sampling process, and ensure the amplitude of the virtual orthogonal signal is consistent. At the same time, the adaptive frequency estimation unit is introduced, which can effectively deal with the power grid voltage frequency changes and ensure the accuracy of PLL. MATLAB (R2012a, MathWorks, Natick, MA, USA) is used to simulate the variation of power grid voltage frequency, DC component injection, harmonics injection and other parameters, and the performance of PLL is adequately verified. In addition, a 5kW single-phase energy router experimental platform is built to verify the proposed PLL. The experimental results show that the PLL can well track the frequency change of the grid voltage and eliminate the DC offset, so as to achieve accurate phase tracking.

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Journal articles on the topic 'PLL Phase locked loops'

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