Relevant bibliographies by topics / Polymer Charge Trapping Memory / Dissertations / Theses
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Dissertations / Theses on the topic 'Polymer Charge Trapping Memory'

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Published: 6 September 2023

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1

Tao, Qingbo, and 陶庆波. "A study on the dielectrics of charge-trapping flash memory devices." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/196488.

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Discrete charge-trapping flash memory is being developed for the next-generation commercial flash-memory applications due to its advantages over the traditional floating-gate counterpart. Currently, Si3N4 is widely used as charge-trapping layer (CTL). However, Si3N4 has low dielectric constant and small conduction-band offset with respect to the SiO2 tunneling layer, imposing limitation on further applications. Therefore, this research emphasized on investigating new dielectrics with appropriate fabrication methods to replace Si3N4 as CTL for achieving improved memory performance. Firstly,
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2

Huang, Xiaodong, and 黄晓东. "A study on high-k dielectrics for discrete charge-trapping flash memory applications." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hub.hku.hk/bib/B5043438X.

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Discrete charge-trapping flash memories are more promising than their floating-gate counterparts due to their physically discrete-trapping and coupling-free nature. Si3N4 is conventional material as charge-trapping layer (CTL) for charge storage. The shortcomings of Si3N4 are its low dielectric constant and small barrier height at its interface with SiO2 tunneling layer. Therefore, this research aims to investigate new materials as CTL for improving the performance of the memory devices. The charge-trapping characteristics of La2O3 with and without nitrogen incorporation were investigated. C
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Jakobsson, Fredrik Lars Emil. "Charge transport modulation in organic electronic diodes." Doctoral thesis, Linköpings universitet, Institutionen för teknik och naturvetenskap, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-14719.

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Since the discovery of conducting polymers three decades ago the field of organic electronics has evolved rapidly. Organic light emitting diodes have already reached the consumer market, while organic solar cells and transistors are rapidly maturing. One of the great benefits with this class of materials is that they can be processed from solution. This enables several very cheap production methods, such as printing and spin coating, and opens up the possibility to use unconventional substrates, such as flexible plastic foils and paper. Another great benefit is the possibility of tailoring the
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4

Simon, Daniel. "Multistability, Ionic Doping, and Charge Dynamics in Electrosynthesized Polypyrrole, Polymer-Nanoparticle Blend Nonvolatile Memory, and Fixed p-i-n Junction Polymer Light-Emitting Electrochemical Cells." Doctoral thesis, University of California, Santa Cruz, USA, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-94587.

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A variety of factors make semiconducting polymers a fascinating alternative for both device development and new areas of fundamental research. Among these are solution processability, low cost, flexibility, and the strong dependence of conduction on the presence of charge compensating ions. With the lack of a complete fundamental understanding of the materials, and the growing demand for novel solutions to semiconductor device design, research in the field can take many, often multifaceted, routes. Due to ion-mediated conduction and versatility of fabrication, conducting polymers can provide a
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Griffo, Michael S. "Charge dynamics in polymer-nanoparticle blends for nonvolatile memory : Surface enhanced fluorescence of a semiconducting polymer; surface plasmon assisted luminescent solar concentrator waveguides /." Diss., Digital Dissertations Database. Restricted to UC campuses, 2009. http://uclibs.org/PID/11984.

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6

Simon, Daniel Theodore. "Multistability, ionic doping, and charge dynamics in electrosynthesized polypyrrole, polymer-nanoparticle blend nonvolatile memory, and fixed P-I-N junction polymer light-emitting electrochemical cells /." Diss., Digital Dissertations Database. Restricted to UC campuses, 2007. http://uclibs.org/PID/11984.

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7

Prime, Dominic Charles. "Switching mechanisms, electrical characterisation and fabrication of nanoparticle based non-volatile polymer memory devices." Thesis, De Montfort University, 2010. http://hdl.handle.net/2086/3314.

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Polymer and organic electronic memory devices offer the potential for cheap, simple memories that could compete across the whole spectrum of digital memories, from low cost, low performance applications, up to universal memories capable of replacing all current market leading technologies, such as hard disc drives, random access memories and Flash memories. Polymer memory devices (PMDs) are simple, two terminal metal-insulator-metal (MIM) bistable devices that can exist in two distinct conductivity states, with each state being induced by applying different voltages across the device terminals
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Gebel, Thoralf. "Nanocluster-rich SiO2 layers produced by ion beam synthesis: electrical and optoelectronic properties." Forschungszentrum Dresden, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:d120-qucosa-29449.

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The aim of this work was to find a correlation between the electrical, optical and microstructural properties of thin SiO2 layers containing group IV nanostructures produced by ion beam synthesis. The investigations were focused on two main topics: The electrical properties of Ge- and Si-rich oxide layers were studied in order to check their suitability for non-volatile memory applications. Secondly, photo- and electroluminescence (PL and EL) results of Ge-, Si/C- and Sn-rich SiO2 layers were compared to electrical properties to get a better understanding of the luminescence mechanism.
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Gebel, Thoralf. "Nanocluster-rich SiO2 layers produced by ion beam synthesis: electrical and optoelectronic properties." Forschungszentrum Rossendorf, 2002. https://hzdr.qucosa.de/id/qucosa%3A21773.

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The aim of this work was to find a correlation between the electrical, optical and microstructural properties of thin SiO2 layers containing group IV nanostructures produced by ion beam synthesis. The investigations were focused on two main topics: The electrical properties of Ge- and Si-rich oxide layers were studied in order to check their suitability for non-volatile memory applications. Secondly, photo- and electroluminescence (PL and EL) results of Ge-, Si/C- and Sn-rich SiO2 layers were compared to electrical properties to get a better understanding of the luminescence mechanism.
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10

Goh, Roland Ghim Siong. "Carbon nanotubes for organic electronics." Thesis, Queensland University of Technology, 2008. https://eprints.qut.edu.au/20849/1/Roland_Goh_Thesis.pdf.

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This thesis investigated the use of carbon nanotubes as active components in solution processible organic semiconductor devices. We investigated the use of functionalized carbon nanotubes in carbon nanotubes network transistors (CNNFET) and in photoactive composites with conjugated polymers. For CNNFETs, the objective was to obtain detailed understanding of the dependence of transistor characteristics on nanotubes bundle sizes, device geometry and processing. Single walled carbon nanotubes were functionalized by grafting octadecylamine chains onto the tubes, which rendered them dispersible in
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Goh, Roland Ghim Siong. "Carbon nanotubes for organic electronics." Queensland University of Technology, 2008. http://eprints.qut.edu.au/20849/.

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This thesis investigated the use of carbon nanotubes as active components in solution processible organic semiconductor devices. We investigated the use of functionalized carbon nanotubes in carbon nanotubes network transistors (CNNFET) and in photoactive composites with conjugated polymers. For CNNFETs, the objective was to obtain detailed understanding of the dependence of transistor characteristics on nanotubes bundle sizes, device geometry and processing. Single walled carbon nanotubes were functionalized by grafting octadecylamine chains onto the tubes, which rendered them dispersible in
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12

Yu-HaoChen and 陳昱豪. "Studies of organic non-volatile memory device with polymeric charge trapping layer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/05335209916994038869.

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碩士<br>國立成功大學<br>光電科學與工程研究所<br>98<br>We investigated organic non-volatile memory devices that are operated at low-voltage and are based on organic thin-film transistors (OTFTs) with pentacene as an active layer. Hafnium dioxide (HfO2) was used as the main gate dielectric to reduce operation voltage. Four kinds of polymer materials were used as the charge trapping layer, which was created via a spin-coating process on the HfO2 layer. The four kinds of polymer materials that were employed included poly(vinyl alcohol) (PVA), cross-linked poly(4-vinylphenol) (C-PVP), polystyrene (PS), and polymethy
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13

Liang, Ji-Ting, and 梁紀庭. "Schottky Barrier Multibit Charge-Trapping Flash Memory." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/26348063641353357830.

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14

Tsai, Tzu-Ting, and 蔡姿婷. "Effects of Stacked High-K Charge trapping layers on Charge Trapping-type Flash Memory Device." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/00933864216135054107.

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15

Liu, Te-Chiang, and 劉得強. "Operation Characteristic of Charge-Trapping-type Flash Memory Device with Charge-trapping layer of stacked dielectrics." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/48553041687300820363.

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16

游承諺. "Device Physics of Polymer Solar Cell: Charge Trapping Mechanism." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/14580335766815797192.

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17

En, Tseng Hao, and 曾浩恩. "Device Physics of Electroluminescent Polymer: Charge Transport and Trapping Mechanism." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/ceuqc9.

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博士<br>國立清華大學<br>化學工程學系<br>93<br>Poly(phenylene vinylene) (PPV), polyfluorene (PF) and their derivatives are the most popular electroluminescent polymers due to their semi-conductive and good fluorescent properties. However, the charge transport, trapping, detrapping and recombination mechanisms have not been well known so far. Issues such as the assignment of trap polarity (hole or electron), the exact effect of the trap states on the charge mobility, and the relationships between detrapping carriers and radiative recombination… etc, are rarely discussed in documents. This is because that both
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18

呂承勳. "Enhanced Operation Characteristics of Charge Trapping Flash Memory Devices with Nitrogen Incorporation and Bandgap Engineering in Charge Trapping Layer." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/16456296207794730051.

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19

Wang, Yu. "Uniform and localized charge-trapping in SONOS nonvolatile memory devices /." Diss., 2005. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3167086.

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20

Lin, Yuan-Sheng, and 林元生. "Nonvolatile Memory with Germanium-Based Material as Charge Trapping Layer." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/38360743062656892208.

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21

Po-HsienKe and 柯伯賢. "Nitrided TiO2 as Charge Trapping Layer for Nonvolatile Memory Devices." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/73puet.

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碩士<br>國立成功大學<br>材料科學及工程學系<br>102<br>Abstract Flash memories using poly-silicon as charge storage layers are the mainstream of conventional nonvolatile memories (NVM). However, flash memories face the difficulty in continued dimension down-scaling because of sidnificant charge losses through the floating gate. Therefore, MONOS nonvolatile memory devices have been developed to resolve the issue. Owing to their reliable charge storage capability, nitrided charge trapping layers promise to use thinner tunnelling oxide without losing the nonvolatility, and consequently to lower operating voltage an
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22

Huang, Ching Hua, and 黃清樺. "The High-k Charge Trapping Layer in Flash Memory Application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/18415680719091711437.

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碩士<br>長庚大學<br>電子工程學系<br>99<br>In this thesis, the Ti-doped high-k ZrO2 material has larger dielectric constant and better characteristics. The RTA annealing process can repair the oxide defect and obtain a stronger bonding to improve the device characteristics. On the other hand, ZrO2 material was used as charge storage layer in flash memory. In our result, the ZrO2 material has better characteristics after annealing treatment at 800℃. The ZrO2 as charge storage layer has a memory window of 1.87 V, higher P/E speed, better data retention and superior endurance characteristics. In addition, we
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23

Fu, Wei-Huan, and 傅暐洹. "Charge-Trapping Characteristics of Non-volatile Memory Using HfON Trapping Layer and HfO2/SiO2 Barriers." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/05290221402959471894.

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碩士<br>國立交通大學<br>光電系統研究所<br>101<br>With the developments of consumer and portable electronic devices, such as cellular phones, cameras memory cards, the nonvolatile memory (NVM) market grows rapidly recently. The NVM devices with high density, fast program/erase speed, good endurance and data retention have been attracted much attention. Have beenHowever, with flash memory entering 20nm technology node, the conventional poly-silicon floating gate (FG) flash memory faces serious challenges from stress-induced leakage current (SILC) -induced charge loss and cell-to-cell coupling. When the thickne
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Hsu, Shu-Ning, and 許書寧. "AlTiO and AlTiON as charge trapping layer for nonvolatile memory applications." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/pqyg97.

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碩士<br>國立交通大學<br>電子研究所<br>105<br>Three-dimensional (3D) architecture has been the main trend of NAND flash memory in industry. Due to no necessity for isolating between each layer insulated charge trapping (CT) layer is used rather than traditional floating gate. Although, commercial 3D NAND was based on SONOS memory, the SONOS like memory or NC memory should be potential for the next generation 3D NAND. Since the 3D structure has a high aspect ratio, the deposition of charge trapping layer is necessary to have high conformity. An appropriate technique is atomic layer deposition (ALD). Thus, in
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Ku, I.-Chun, and 古依純. "Analysis and Modeling of Lateral Migration for Charge Trapping Flash Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/33720965491595422840.

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碩士<br>國立清華大學<br>電子工程研究所<br>98<br>Recently, Flash technology is gradually migrated from floating-gate cells to charge-trapping devices due to lowing operating voltage and two-bit storage. However, it also a great challenge for that the local distributions of trap charges will be lateral migrated after thermal various or endurance operation. Since the gate length of the cell devices are continued to scale down, it is crucial to realize the impacts of lateral migration on device characteristics for the programmed and the erased SONOS cells, specially the variations of threshold voltage. In this
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Chen, Tin An, and 陳亭安. "Fabrication and Analysis of Nanowire Schottky Barrier Charge Trapping Flash Memory." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/94549668160688690512.

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碩士<br>國立清華大學<br>電子工程研究所<br>103<br>This thesis experimentally explores the process fabrication and measurement characterization of Schottky barrier nanowire charge trapping memories. Two different types of hard-mask lithography were examined to fabricate the gate-all-around nanowire structure. In cell characterization, this work studies the cell reading, programming, and erasing at room and higher temperatures. Reliability characterization in cycling endurance and data retention are also investigated. The results show that the high-temperature Schottky barrier nanowire charge trapping cells pre
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Eichenlaub, Nathan. "Design, characterization and modeling of charge trapping nonvolatile semiconductor memory devices." 2009. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:1463967.

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Chang, Ting-Yu, and 張廷瑜. "The Investigation of Charge-Trapping Flash Nonvolatile Memory by Using Ge Diffusion into Si3N4 Trapping Layer." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/73374988888532153086.

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碩士<br>國立交通大學<br>電子研究所<br>100<br>The rapid advancement of technology with a wide range of consumer electronics is popularity. In recent years, the requirements for memory are increasing and a variety of memory will be invented. Non-volatile flash memory are popular because of its high density, good data retention and program/erase (P/E), while widely used in various fields of electronic products, such as flash drives, mobile phones / camera memory card, many kinds of electronic product code stored ... and so on, faced with such a huge application, so the characteristics of flash memory for upgr
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Cheng, Chia-Hsin, and 鄭家欣. "Process Study of Trapping and Blocking Layers on Gate-All-Around Junctionless Charge Trapping Flash Memory Devices." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/79s7v3.

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碩士<br>國立清華大學<br>工程與系統科學系<br>105<br>In recent years, flash memory device can be continuously scaled down by continuous advance in process technology. However, the scale down of planar flash memory device can not be continued due to its limitation of shrinkage. How to increase the density of memory devices and enhance operating characteristics are important issues. Some approaches have been reported to solve these issues, such as high-k material, junctionless (JL) channel, poly-Si channel, nanowire (NW) structure, gate all around (GAA) structure and 3D stack devices. In this thesis, operation ch
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Yang, Hao, and 楊. 皓. "Double Stacked Charge Trapping Layer on Poly-Si Nanosheet Channels Nonvolatile Memory." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/7958x4.

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31

Hsu, Che-Jui, and 許哲睿. "Memory Characteristics of Advanced Metal-Oxide-Semiconductor Structured Nonvolatile Memory with HfLaTiON as Charge Trapping Layer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/sfnn42.

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碩士<br>國立虎尾科技大學<br>機械與機電工程研究所<br>98<br>Abstract In this thesis, the development of electrical and reliability properties measurement system for nonvolatile memory devices was achieved by the visual basic (VB) software. The electrical and reliability properties include hysteresis, programming time, erasing time, endurance and retention. To avoid the personal errors, automatically measurement systems integrated with HP4284A, HP5270B, HP5250, and HP81110A instruments were developed. Memory characteristics of advanced metal-oxide-semiconductor structured nonvolatile memory with HfLaTiON as charge
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Shiu, Feng-Wen, and 許逢文. "Effects of Stacked High-k Blocking Layer on Charge-Trapping Flash Memory Devices." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/09742273730644922957.

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碩士<br>國立清華大學<br>工程與系統科學系<br>98<br>When floaging gate device can't satisfy smaller device, SONOS-Type is the one of candidate to replace it. SONOS-Type device tunneling layer thickness is about 30A ,it is a problem for retention. How to improve our device performance is very important. In our experiment, using various high-k dielectrics as stacked SONOS-Type blocking layer. Different materials has different performances , matching stacked structure by nitrogen treatment with distinct doses(2mins , 4mins, 8mins) , bandgap-engineering, k-value as a excellent blocking oxide layer. For tunneling ox
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Tsai, Cheng-Yu, and 蔡政育. "The study of charge trap flash memory device with band engineered trapping layer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/47291991120299568898.

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碩士<br>國立清華大學<br>工程與系統科學系<br>98<br>1.Improvement of P/E speed for NAN structure trapping layer higher charge tunneling efficiency lower Ig 2.Trapped charge detrap easier for HfO2 compared with Si3N4,but that’s a trade-off : erasing speed ? retention 3.Improvement of endurance characteristics for NAN structure compared with single Si3N4 trapping layer barrier oxide(Al2O3) reduces the trap generation during cycling 4.Simultaneous improvement in P/E speed and retention for Si3N4/Al2O3/HfO2 structure
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Chen, Yen-Ting, and 陳彥廷. "Atomic Layer Deposition of HfON Thin Film for Charge Trapping Flash Memory Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/96822231653032390505.

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Lin, Wen-Shin, and 林文新. "Study on Fluorine Applied to Nonvolatile Memory Using HfO2 as Charge Trapping Layer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/36695585983895262265.

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碩士<br>國立交通大學<br>電子研究所<br>98<br>In order to save the cost, increase the throughput and decrease operation voltage, many kinds of the devices are continually scaling. Undoubtedly, the nonvolatile memory (NVM) device is one of the scaling devices. Moreover, Current requirements of nonvolatile memory are the high density cells, low-power consumption, high-speed operation and good reliability for the scaling down devices. There are many studies that discuss how to improve the reliability including retention and endurance. In this study, silicon oxide (SiO2) is grown for tunnel oxide layer. The trap
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Liu, Chi-Ling, and 劉奇靈. "Improvement of Charge Trapping/ Detrapping Efficiency by Ion Bombardment for NAND Flash Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/90775190474831345951.

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碩士<br>逢甲大學<br>產業研發碩士班<br>98<br>According to ITRS roadmap, flash memory have some challenge about shrinkage of device size. However, flash memory must maintain the device reliability and improve the device characteristic. These are the main topics for the future research. We used ion bombardment method as lightly damage on effective tunneling layer to improve the charge trapping/detrapping efficiency. The surface roughness was increased after ion bombardment and the local electrical field mechanism enhance the charge trapping/detrapping efficiency. Otherwise, ion bombardment method brought abou
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Ye, Zong-Hao, and 葉宗浩. "Applications of Band Engineering and Nitrogen Profiles in Charge-Trapping Flash Memory Devices." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/69517986608575673412.

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博士<br>國立清華大學<br>工程與系統科學系<br>104<br>As the demands for personal cameras, laptops, and smart-phones increase, development of nonvolatile memory (NVM) is rapidly expanding. NVM devices with faster programming/erasing (P/E), excellent retention and endurance characteristics are required. To achieve this goal, many methods have been applied to Charge-trapping (CT) flash memory devices. This dissertation firstly reviews the literature on CT-flash memory. According to the literature, P/E speeds can be improved by applying high-k materials to the charge-trapping layer of CT-flash memory devices. Howev
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Lee, Hsiang-Chen, and 李祥丞. "Effects of the scaled charge trapping layer on SONOS type non-volatile memory." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/93668147445726615028.

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碩士<br>國立清華大學<br>電子工程研究所<br>97<br>Recently, Flash technology is gradually migrated from floating-gate cells to charge-trapping devices due to lower operating voltage and two bits storage. However, it is also a great challenge to scale the conventional charge-trapping Flash cells for the need of high voltage operations in channel-hot-electron (CHE) programming and band-to-band-hot-hole (BBHH) erasing. This thesis experimentally examines the scaling effects of the nitride charge-trapping layers on Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type Flash memory. The reduction of nitride charge trapp
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Lin, Hsin-Yi, and 林欣逸. "Study of Fin-shaped Nanowires Tunneling-Field-Effect-Transistor Charge Trapping Nonvolatile Memory." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/21574027888647336316.

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碩士<br>國立清華大學<br>工程與系統科學系<br>101<br>The Pi-gate polycrystalline silicon (poly-Si) nanowires tunneling field effect transistor (TFET) charge trapping(CT) nonvolatile memory (NVM) with all programming mechanisms and shows a large memory window and good reliability is demonstrated for the first time. Pi-gate nanowires structure performs faster program/erase speed. Otherwise, the SONOS-type structure can improve excellent reliability. Furthermore, due to the poly-Si channel technology, it is possible to develop in 3D high-density stacked NVM. In FN tunneling programming, operation of conducti
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Chen, Guan-Syun, and 陳冠勳. "Memory Characteristics of Metal-Oxide-Semiconductor Structured Nonvolatile Memory Capacitors with Terbium Oxides as Charge Trapping Layers." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/z7b669.

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碩士<br>國立虎尾科技大學<br>光電與材料科技研究所<br>101<br>Memory characteristics of metal-oxide-semiconductor (MOS) structured nonvolatile memory capacitors with terbium oxides (Tb4O7) as charge trapping layers were demonstrated in this work. First, the memory characteristic of MOS structured nonvolatile memory capacitors with various tunneling oxide were demonstrated. Then, the SiO2/Tb4O7/SiO2 stacked films in MOS structured nonvolatile memory capacitors with various gas ambient treated Tb4O7 as charge trapping layers were proposed. Various gas ambient treatments include oxygen and nitrogen. Furthermore, the M
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Cheng, Chia-Hsiang, and 鄭嘉祥. "Memory Characteristics of Metal-Oxide-Semiconductor Structured Nonvolatile Memory Capacitors with Dysprosium Oxides as Charge Trapping Layers." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/68qkpk.

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碩士<br>國立虎尾科技大學<br>光電與材料科技研究所<br>101<br>Characteristics of metal-oxide-semiconductor (MOS) structured nonvolatile memory (NVM) devices with various dysprosium oxide (Dy2O3) dielectrics as charge trapping nodes have been presented in this study. The memory characteristics include hysteresis, programming/erasing time, endurance, and retention. First, various tunneling oxides were formed by tuning various rapid thermal annealing (RTA) temperatures. Then, the effects of post-deposition annealing (PDA) on Dy2O3 charge trapping layer of MOS structured NVM were investigated. Furthermore, characterist
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Lai, Sheng-Chih, and 賴昇志. "A Study of Future Non-volatile Memory Technologies - Charge Trapping NAND Flash Memory and Low Temperature Processed FeRAM." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/84983799650715087564.

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博士<br>國立清華大學<br>材料科學工程學系<br>96<br>Non-volatile semiconductor memories have attracted much attention due to the fast growing demand of portable electronic devices. In this thesis, the erase mechanism and the performance of the state of the art SONOS-type flash memories are critically examined, and a low temperature extended-pulse laser annealing for COI FeRAM is also studied. In the study of innovative SONOS-type flash memories, a de-trapping model for the erase mechanism of MANOS device is proposed and demonstrated. In addition, the erase and retention characteristics for MONOS, MANOS and BE-S
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Keng, Wen-Chun, and 耿文駿. "Application of SiGe Buried Channel on Electrical Characteristics of Charge-trapping Flash Memory Devices." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/40030450730645372796.

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Chang, Wei-Jen, and 張維仁. "Application of SiGe Buried Channel on Electrical Characteristics of Charge-trapping Flash Memory Devices." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/18831586821699289989.

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碩士<br>國立清華大學<br>工程與系統科學系<br>98<br>Abstract Charge-trapping (CT) flash is regarded as one of the most promising nonvolatile memory devices. Some approaches were proposed to further enhance the operation properties of CT flash devices by stacked high-k charge-trapping layer , stacked tunneling oxides with thicker physic thickness , metal gate with high work function, and SiGe buried channel(small band gap) . SiGe and Ge buried channel with different annealing temperature and various thicknesses of Si-cap layer on operation characteristics of charge-trapping (CT) flash devices were studied in thi
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Sun, Cherng-En, and 孫晟恩. "Electrical Characteristics for Flash Memory with pn-Junction Diode as the Charge-Trapping Layer." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/99464254432375680727.

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Liu, Yen-Ting, and 劉晏廷. "Study on the Novel High Speed Charge Trapping Memory Devices with Poly-Si TFTs." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/56237471861596607387.

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碩士<br>國立交通大學<br>電子研究所<br>98<br>In recent years, many researchers have drawn attention to improve the program/erase efficiency of charge trapping memory devices owing to the program/erase efficiency of conventional charge trapping memory devices is lower than that of floating gate memory devices. However, most methods of improving the program/erase efficiency resulted in poor reliability issues. In this thesis, our investigation has been classified into two topics. At first, for Poly-Si TFT SONOS memory devices, we have proposed a FinFET structure, an omega gate structure, and a GAA structu
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Fong-Chi, Shih, and 石豐綺. "Study on LTPS-TFT Flash Memory using High-k Material as Charge Trapping Layer." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/07856442760214408383.

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碩士<br>國立交通大學<br>電子工程系所<br>96<br>In this thesis, electrical characteristic and Reliability of low temperature poly- silicon thin film transistor nonvolatile flash memory have studied, including programming/erasing speed, retention, endurance, retention after cycling and programming disturbances. First, three kinds of high-k materials, SiNx, Al2O3 and Hf-silicate, respectively, were applied for charge trapping layer of n-channel TFT memories. The fabricated memory devices show great retention and disturbance characteristics, attributed to the thick tunneling oxide. Among these three materials, A
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Lu, Yu-Chin, and 盧育勤. "Improved Operation Characteristics of Charge Trap Flash Memory Devices by Engineering Stacked Trapping Layer." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/ahj6f9.

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Cheng, Cheng-Hsien, and 程政憲. "Application of SiGe on P-Channel SONOS-type Nonvolatile Memory and Study of Charge Distribution in Charge Trapping Layer." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/06591321728723849033.

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Lin, Hsiao-Len, and 林孝倫. "Effects of Metal Gate and High-k Blocking Layer on Charge-Trapping Flash Memory Devices." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/85788773007853849370.

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