Relevant bibliographies by topics / Power Aware Test

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Power Aware Test'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Power Aware Test"

1

Potluri, Seetal, Nitin Chandrachoodan, and V. Kamakoti. "Interconnect Aware Test Power Reduction." Journal of Low Power Electronics 8, no. 4 (August 1, 2012): 516–25. http://dx.doi.org/10.1166/jolpe.2012.1212.

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Singh, Padmaraj, Vijaykrishnan Narayanan, and David L. Landis. "Targeted random test generation for power-aware multicore designs." ACM Transactions on Design Automation of Electronic Systems 17, no. 3 (June 2012): 1–19. http://dx.doi.org/10.1145/2209291.2209298.

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Li, Jia, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, and Qiang Xu. "Capture-power-aware test data compression using selective encoding." Integration 44, no. 3 (June 2011): 205–16. http://dx.doi.org/10.1016/j.vlsi.2011.01.005.

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HAN, Cheng-Yu, Yu-Ching LI, Hao-Tien KAN, and James Chien-Mo LI. "Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E99.A, no. 12 (2016): 2320–27. http://dx.doi.org/10.1587/transfun.e99.a.2320.

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Arslan, Baris, and Alex Orailoglu. "Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 1 (January 2016): 141–54. http://dx.doi.org/10.1109/tcad.2015.2448689.

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Elshoukry, Mohammed, Mohammad Tehranipoor, and C. P. Ravikumar. "A critical-path-aware partial gating approach for test power reduction." ACM Transactions on Design Automation of Electronic Systems 12, no. 2 (April 2007): 17. http://dx.doi.org/10.1145/1230800.1230809.

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Habiby, Payam, Sebastian Huhn, and Rolf Drechsler. "Power-aware test scheduling framework for IEEE 1687 multi-power domain networks using formal techniques." Microelectronics Reliability 134 (July 2022): 114551. http://dx.doi.org/10.1016/j.microrel.2022.114551.

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Czysz, Dariusz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemysław Szczerbicki, and Jerzy Tyszer. "Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 8 (August 2011): 1225–38. http://dx.doi.org/10.1109/tcad.2011.2126574.

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Ma, Junxia, and Mohammad Tehranipoor. "Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 12 (December 2011): 1923–34. http://dx.doi.org/10.1109/tcad.2011.2163159.

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Haghbayan, Mohammad-Hashem, Amir-Mohammad Rahmani, Antonio Miele, Mohammad Fattah, Juha Plosila, Pasi Liljeberg, and Hannu Tenhunen. "A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures." IEEE Transactions on Computers 65, no. 3 (March 1, 2016): 730–43. http://dx.doi.org/10.1109/tc.2015.2481411.

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Dissertations / Theses on the topic "Power Aware Test"

1

Wu, Fangmei. "Study and Reduction of Power Consumption during Test of Digital Circuits." Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20072/document.

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Cette thèse concerne l'étude et la réduction de la consommation de puissance durant le test par scan des circuits digitaux. Afin de détecter les défauts de délai de transition, les deux principales structures sont utilisés dans la pratique: Launch-Off-Shift (LOS) et launch-Off-Capture (LOC). L'ensemble des travaux réalises montre que le test LOS est plus efficace que le test LOC en terme de couverture de fautes de transition et la longueur de test. Toutefois, le test LOS nécessite une puissance plus élevée lors du launch-to-capture (LTC) du cycle, notamment en terme de consommation de puissance de pic. Ainsi, nous proposons une nouvelle approche de génération de vecteurs de test LOS basée sur la consommation. La technique proposée est capable de réduire et d'évaluer la puissance de pic de test se rapprochant le plus possible de la puissance fonctionnelle. Les avantages qui en résultent permettent de résoudre le problème lié à la perte de rendement et de s'abstenir du test se produisant lorsque la puissance de test est trop faible par rapport à la puissance fonctionnelle
This thesis relates to study and reduction of power consumption during at-speed scan delay testing for digital circuits. To detect transition delay faults, two main testing schemes are used in practice: Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). In this work, we prove that LOS testing is more efficient than LOC testing in terms of transition fault coverage (TFC) and test length. However, LOS presents higher power during the launch-to-capture (LTC) cycle, especially in terms of peak power. For this purpose, we propose a novel power-aware test pattern generation technique for LOS testing. The proposed approach is able to reduce and map the test peak power as close as possible to the functional power. The important feature of this framework is that, in additional to solving the yield loss problem, it also avoids test escape that may occur when test power is too much reduced compared to functional power
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2

Tudu, Jaynarayan Thakurdas. "Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation." Thesis, 2016. http://etd.iisc.ac.in/handle/2005/3003.

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Test power, data volume, and test time have been long-standing problems for sequential scan based testing of system-on-chip (SoC) design. The modern SoCs fabricated at lower technology nodes are complex in nature, the transistor count is as large as billions of gate for some of the microprocessors. The design complexity is further projected to increase in the coming years in accordance with Moore's law. The larger gate count and integration of multiple functionalities are the causes for higher test power dissipation, test time and data volume. The dynamic power dissipation during scan testing, i.e. during scan shift, launch and response capture, are major concerns for reliable as well as cost effective testing. Excessive average power dissipation leads to a thermal problem which causes burn-out of the chip during testing. Peak power on other hand causes test failure due to power induced additional delay. The test failure has direct impact on yield. The test power problem in modern 3D stacked based IC is even a more serious issue. Estimating the worst case functional power dissipation is yet another great challenge. The worst case functional power estimation is necessary because it gives an upper bound on the functional power dissipation which can further be used to determine the safe power zone for the test. Several solutions in the past have been proposed to address these issues. In this thesis we have three major contributions: 1) Sequential scan chain reordering, and 2) JScan-an alternative Joint-scan DFT architecture to address primarily the test power issues along with test time and data volume, and 3) an integer linear programming methodology to address the power estimation problem. In order to reduce test power during shift, we have proposed a graph theoretic formulation for scan chain reordering and for optimum scan shift operation. For each formulation a set of algorithms is proposed. The experimental results on ISCAS-89 benchmark circuit show a reduction of around 25% and 15% in peak power and scan shift time respectively. In order to have a holistic DFT architecture which could solve test power, test time, and data volume problems, a new DFT architecture called Joint-scan (JScan) have been developed. In JScan we have integrated the serial and random access scan architectures in a systematic way by which the JScan could harness the respective advantages from each of the architectures. The serial scan architecture from test power, test time, and data volume problems. However, the serial scan is simple in terms of its functionality and is cost effective in terms of DFT circuitry. Whereas, the random ac-cess scan architecture is opposite to this; it is power efficient and it takes lesser time and data volume compared to serial scan. However, the random access scan occupies larger DFT area and introduces routing congestion. Therefore, we have proposed a methodology to realize the JScan architecture as an efficient alternative for standard serial and random access scan. Further, the JScan architecture is optimized and it resulted into a 2-Mode 2M-Jscan Joint-scan architecture. The proposed architectures are experimentally verified on larger benchmark circuits and compared with existing state of the art DFT architectures. The results show a reduction of 50% to 80% in test power and 30% to 50% in test time and data volume. The proposed architectures are also evaluated for routing area minimization and we obtained a saving of around 7% to 15% of chip area. Estimating the worst case functional power being a challenging problem, we have proposed a binary integer linear programming (BILP) based methodology. Two different formulations have been proposed considering the different delay models namely zero-delay and unit-delay. The proposed methodology generates a pair or input vectors which could toggle the circuit to dissipate worst power. The BILP problems are solved using CPLEX solver for ISCAS-85 combinational benchmark circuits. For some of the circuits, the proposed methodology provided the worst possible power dissipation i.e. 80 to 100% toggling in nets.
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3

Tudu, Jaynarayan Thakurdas. "Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation." Thesis, 2016. http://hdl.handle.net/2005/3003.

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Test power, data volume, and test time have been long-standing problems for sequential scan based testing of system-on-chip (SoC) design. The modern SoCs fabricated at lower technology nodes are complex in nature, the transistor count is as large as billions of gate for some of the microprocessors. The design complexity is further projected to increase in the coming years in accordance with Moore's law. The larger gate count and integration of multiple functionalities are the causes for higher test power dissipation, test time and data volume. The dynamic power dissipation during scan testing, i.e. during scan shift, launch and response capture, are major concerns for reliable as well as cost effective testing. Excessive average power dissipation leads to a thermal problem which causes burn-out of the chip during testing. Peak power on other hand causes test failure due to power induced additional delay. The test failure has direct impact on yield. The test power problem in modern 3D stacked based IC is even a more serious issue. Estimating the worst case functional power dissipation is yet another great challenge. The worst case functional power estimation is necessary because it gives an upper bound on the functional power dissipation which can further be used to determine the safe power zone for the test. Several solutions in the past have been proposed to address these issues. In this thesis we have three major contributions: 1) Sequential scan chain reordering, and 2) JScan-an alternative Joint-scan DFT architecture to address primarily the test power issues along with test time and data volume, and 3) an integer linear programming methodology to address the power estimation problem. In order to reduce test power during shift, we have proposed a graph theoretic formulation for scan chain reordering and for optimum scan shift operation. For each formulation a set of algorithms is proposed. The experimental results on ISCAS-89 benchmark circuit show a reduction of around 25% and 15% in peak power and scan shift time respectively. In order to have a holistic DFT architecture which could solve test power, test time, and data volume problems, a new DFT architecture called Joint-scan (JScan) have been developed. In JScan we have integrated the serial and random access scan architectures in a systematic way by which the JScan could harness the respective advantages from each of the architectures. The serial scan architecture from test power, test time, and data volume problems. However, the serial scan is simple in terms of its functionality and is cost effective in terms of DFT circuitry. Whereas, the random ac-cess scan architecture is opposite to this; it is power efficient and it takes lesser time and data volume compared to serial scan. However, the random access scan occupies larger DFT area and introduces routing congestion. Therefore, we have proposed a methodology to realize the JScan architecture as an efficient alternative for standard serial and random access scan. Further, the JScan architecture is optimized and it resulted into a 2-Mode 2M-Jscan Joint-scan architecture. The proposed architectures are experimentally verified on larger benchmark circuits and compared with existing state of the art DFT architectures. The results show a reduction of 50% to 80% in test power and 30% to 50% in test time and data volume. The proposed architectures are also evaluated for routing area minimization and we obtained a saving of around 7% to 15% of chip area. Estimating the worst case functional power being a challenging problem, we have proposed a binary integer linear programming (BILP) based methodology. Two different formulations have been proposed considering the different delay models namely zero-delay and unit-delay. The proposed methodology generates a pair or input vectors which could toggle the circuit to dissipate worst power. The BILP problems are solved using CPLEX solver for ISCAS-85 combinational benchmark circuits. For some of the circuits, the proposed methodology provided the worst possible power dissipation i.e. 80 to 100% toggling in nets.
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4

Han, Cheng-Yu, and 韓承佑. "Power-Supply-Noise-Aware Test Pattern Analysis and Regeneration for Yield Improvement." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/30216520221546924613.

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碩士
國立臺灣大學
電子工程學研究所
103
This thesis propose a power-supply-noise-aware test pattern analysis and regeneration framework. The proposed framework analysis timing with reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on linear analytical functions, instead of solving nonlinear functions. Moreover, the function is technology dependent, so there is no need to perform spice characterization for each cells. The experimental results show, for small circuits, the error is less than 5% compared with HSPICE. For large circuits, we achieved 272 times speed up compared with NANOSIM. We perform timing analysis on a 638K gate benchmark circuit to identify 88 timing-violation test patterns (out of 31K test patterns) that are difficult to detect by traditional techniques. After test pattern regeneration, we removed all risky patterns, without fault coverage loss and with only little test inflation. The proposed technique generates shorter test sets and higher fault coverage than commercial power-aware ATPG.
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Ho, Mei-Ling, and 何美玲. "Power-Aware Test Data Compression by Pattern Run-Length with Variable Pattern Length." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/5e27hz.

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碩士
元智大學
資訊工程學系
107
With the advance of VLSI process technology, the increasing chip density and circuit size have made the circuit testing more complex. Moreover, the structure of the SOC (System on Chip) which incorporated more modules in a single chip needs more test data volume to make sure the correctness of the circuit. That may also exceed the memory capacity or even longer testing time. Many new techniques have been proposed to reduce test data volume so as to save memory cost and improve the transmission efficiency between tester-ATE (Auto Test Equipment) and SOC. So one solution to this problem is to use compression techniques to reduce the volume of test data. The proposed thesis use Power-Aware test data compression by pattern run-length based compression method. Such as pattern length and number of pattern runs is encoded to denote the compression status. Improvements are experimentally demonstrated on larger ISCAS'89 benchmarks circuit using MINTEST. The experimental result shows that the average compression ratio of the proposed approach outperforms than other previous approaches. Keywords: WTC，WTC limit，Power-Aware
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Books on the topic "Power Aware Test"

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Girard, Patrick, Nicola Nicolici, and Xiaoqing Wen, eds. Power-Aware Testing and Test Strategies for Low Power Devices. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-0928-2.

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Wen, Xiaoqing, Nicola Nicolici, and Girard Patrick. Power-aware testing and test strategies for low power devices. New York: Springer, 2010.

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Wen, Xiaoqing, Nicola Nicolici, and Patrick Girard. Power-Aware Testing and Test Strategies for Low Power Devices. Springer, 2014.

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Wen, Xiaoqing, Nicola Nicolici, and Patrick Girard. Power-Aware Testing and Test Strategies for Low Power Devices. Springer London, Limited, 2010.

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Dobson, James E. Critical Digital Humanities. University of Illinois Press, 2019. http://dx.doi.org/10.5622/illinois/9780252042270.001.0001.

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This book seeks to develop an answer to the major question arising from the adoption of sophisticated data-science approaches within humanities research: are existing humanities methods compatible with computational thinking? Data-based and algorithmically powered methods present both new opportunities and new complications for humanists. This book takes as its founding assumption that the exploration and investigation of texts and data with sophisticated computational tools can serve the interpretative goals of humanists. At the same time, it assumes that these approaches cannot and will not obsolete other existing interpretive frameworks. Research involving computational methods, the book argues, should be subject to humanistic modes that deal with questions of power and infrastructure directed toward the field’s assumptions and practices. Arguing for a methodologically and ideologically self-aware critical digital humanities, the author contextualizes the digital humanities within the larger neo-liberalizing shifts of the contemporary university in order to resituate the field within a theoretically informed tradition of humanistic inquiry. Bringing the resources of critical theory to bear on computational methods enables humanists to construct an array of compelling and possible humanistic interpretations from multiple dimensions—from the ideological biases informing many commonly used algorithms to the complications of a historicist text mining, from examining the range of feature selection for sentiment analysis to the fantasies of human subjectless analysis activated by machine learning and artificial intelligence.
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Book chapters on the topic "Power Aware Test"

1

Wunderlich, Hans-Joachim, and Christian G. Zoellin. "Power-Aware Design-for-Test." In Power-Aware Testing and Test Strategies for Low Power Devices, 117–46. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_4.

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Larsson, Erik, and C. P. Ravikumar. "Power-Aware System-Level Test Planning." In Power-Aware Testing and Test Strategies for Low Power Devices, 175–211. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_6.

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Kundu, Sandip, and Alodeep Sanyal. "Power Issues During Test." In Power-Aware Testing and Test Strategies for Low Power Devices, 31–63. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_2.

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Goel, Sandeep Kumar, and Krishnendu Chakrabarty. "Power-Aware Test Data Compression and BIST." In Power-Aware Testing and Test Strategies for Low Power Devices, 147–73. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_5.

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Kassab, Mark, and Mohammad Tehranipoor. "Test of Power Management Structures." In Power-Aware Testing and Test Strategies for Low Power Devices, 295–322. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_10.

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Wen, Xiaoqing, and Seongmoon Wang. "Low-Power Test Pattern Generation." In Power-Aware Testing and Test Strategies for Low Power Devices, 65–115. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_3.

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Khursheed, Saqib, and Bashir M. Al-Hashimi. "Test Strategies for Multivoltage Designs." In Power-Aware Testing and Test Strategies for Low Power Devices, 243–71. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_8.

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Keller, Brion, and Krishna Chakravadhanula. "Test Strategies for Gated Clock Designs." In Power-Aware Testing and Test Strategies for Low Power Devices, 273–93. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_9.

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Hirech, Mokhtar. "EDA Solution for Power-Aware Design-for-Test." In Power-Aware Testing and Test Strategies for Low Power Devices, 323–53. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_11.

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Roy, Kaushik, and Swarup Bhunia. "Low-Power Design Techniques and Test Implications." In Power-Aware Testing and Test Strategies for Low Power Devices, 213–42. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0928-2_7.

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Conference papers on the topic "Power Aware Test"

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Manchukonda, Likith Kumar, Karthikeyan Natarajan, and Manish Arora. "Power Aware Test." In 2022 IEEE European Test Symposium (ETS). IEEE, 2022. http://dx.doi.org/10.1109/ets54262.2022.9810367.

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Lin, Xijiang, Elham Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, and Jerzy Tyszer. "Power Aware Embedded Test." In 2011 IEEE 20th Asian Test Symposium (ATS). IEEE, 2011. http://dx.doi.org/10.1109/ats.2011.49.

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Gowthami, M. R., N. Ravi Kiran, G. Harish, and Siva Yellampalli. "Test power aware STUMP BIST." In 2015 International Conference on Smart Technologies and Management  for Computing, Communication, Controls, Energy and Materials (ICSTM). IEEE, 2015. http://dx.doi.org/10.1109/icstm.2015.7225456.

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Srivaths Ravi. "Power-aware test: Challenges and solutions." In 2007 IEEE International Test Conference. IEEE, 2007. http://dx.doi.org/10.1109/test.2007.4437660.

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Xiao, Yang, Kevin Irick, Vijay Narayanan, Dongwha Shin, and Naehyuck Chang. "Saliency Aware Display Power Management." In Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2013. http://dx.doi.org/10.7873/date.2013.250.

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Bin Li, Lei Fang, and Michael S. Hsiao. "Efficient power droop aware delay fault testing." In 2007 IEEE International Test Conference. IEEE, 2007. http://dx.doi.org/10.1109/test.2007.4437597.

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Wen, Xiaoqing. "Power-aware testing: The next stage." In 2012 17th IEEE European Test Symposium. IEEE, 2012. http://dx.doi.org/10.1109/ets.2012.6233000.

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Yeh, Hua-Hsin, Shih-Hsu Huang, and Yow-Tyng Nieh. "Leakage-power-aware clock period minimization." In Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2014. http://dx.doi.org/10.7873/date.2014.272.

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Yeh, Hua-Hsin, Shih-Hsu Huang, and Yow-Tyng Nieh. "Leakage-power-aware clock period minimization." In Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2014. http://dx.doi.org/10.7873/date2014.272.

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Mukherjee, N. "Power-Aware DFT - Do we really need it?" In 2008 IEEE International Test Conference. IEEE, 2008. http://dx.doi.org/10.1109/test.2008.4700658.

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