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Relevant bibliographies by topics / Power Chip on Chip

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Academic literature on the topic 'Power Chip on Chip'

Author: Grafiati

Published: 11 January 2025

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Journal articles on the topic "Power Chip on Chip"

1

Tan, N., and S. Eriksson. "Low-power chip-to-chip communication circuits." Electronics Letters 30, no. 21 (1994): 1732–33. http://dx.doi.org/10.1049/el:19941178.

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Yerman, AlexanderJ. "4538170 Power chip package." Microelectronics Reliability 26, no. 3 (1986): 594. http://dx.doi.org/10.1016/0026-2714(86)90686-4.

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Vali, S. Sadiq, K. B. Madhu Mohan, S. Sreenivasulu, S. S. Zahoor Ahmed, and T. Muneer. "Low Power Encoding Technique for Network on Chip." International Journal of Research Publication and Reviews 4, no. 4 (2023): 4950–53. http://dx.doi.org/10.55248/gengpi.234.4.38292.

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FOK, C. W., and D. L. PULFREY. "FULL-CHIP POWER-SUPPLY NOISE: THE EFFECT OF ON-CHIP POWER-RAIL INDUCTANCE." International Journal of High Speed Electronics and Systems 12, no. 02 (2002): 573–82. http://dx.doi.org/10.1142/s0129156402001472.

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The importance of on-chip power-rail inductance in generating delta-I power-supply noise is examined in this paper using systematic circuit simulation of the complete integrated-circuit power net. This source of noise is compared to the resistive IR drop in the net, and to the delta-I noise due to both high-inductance- and low-inductance-bonding packages. Results are presented for a typical on-chip power net in 0.18 μm CMOS technology, and it is demonstrated that the inductance of this on-chip power net is the dominant contributor to the full-chip power-supply noise. The simultaneous switching events which produce the triggering current transients for the delta-I noise are taken to arise from core-logic switching; the mitigating, de-coupling role of the capacitance of non-switching gates within the core-logic block is considered.

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Eireiner, M., S. Henzler, X. Zhang, J. Berthold, and D. Schmitt-Landsiedel. "Impact of on-chip inductance on power supply integrity." Advances in Radio Science 6 (May 26, 2008): 227–32. http://dx.doi.org/10.5194/ars-6-227-2008.

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Abstract. Based on product related scenarios, the impact of on-chip inductance on power supply integrity is analyzed. The impact of varying current profiles is shown to be minimal. In a regular power grid with regular bump connections, the impact of on-chip inductance on the cycle average of the supply voltage can be neglected, even for a worst case estimation of on-chip inductance. Whereas, the maximum transient power supply drop can be significantly underestimated by neglecting on-chip inductance. The impact of on-chip inductance in a System-on-Chip (SoC) environment also can be neglected if the on-chip inductance is conservativly estimated.

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Li, Jun Hui, Lei Han, Ji An Duan, and Jue Zhong. "Features of Machine Variables in Thermosonic Flip Chip." Key Engineering Materials 339 (May 2007): 257–62. http://dx.doi.org/10.4028/www.scientific.net/kem.339.257.

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An assembly bed on thermosonic flip chip bonding was set up, two different structures of tool tips were designed, and a series of experiments on flip chip and bonding machine variables were carried out. Lift-off characteristics of thermosonic flip chip were investigated by using Scanning Electron Microscope (JSM-6360LV), and vibration features of tool tips driven by high frequency were tested by using PSV-400-M2 Laser Doppler Vibrometer. Results show that, for chip-press model, slippage and rotation phenomena between tool tip and chip have been solved by using tool with greater area tip pattern during flip-chip bonding process, and welding failures appeared in chip-collet model have been controlled. Greater area pattern on tool tip is better than small area pattern. The power of ‘n’ bumps on flip chip bonding is far smaller than that of n×(the power of single wire bonding). The power is directly proportion to vibration displacement driven by the power, high-power decrease positioning precision of flip chip bonding or result in slippage and rotation phenomena. The proper machine variables ranges for thermosonic flip chip had been obtained.

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Yin, Feng Ling, Bing Quan Huo, Hai Bo Wang, and Long Cheng. "A Design for Power Supply Monitoring." Advanced Materials Research 912-914 (April 2014): 1061–64. http://dx.doi.org/10.4028/www.scientific.net/amr.912-914.1061.

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Monitoring servers' power is very important, and a design is present for solving existed issues. Building a wireless network with Zigbee technology, there are major modules:End Device with chip CC2530, Zigbee Router with chip CC2530 and CC2591, Zigbee coordinator with chip CC2530 and CC2430.

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Laha, Soumyasanta, Savas Kaya, David W. Matolak, William Rayess, Dominic DiTomaso, and Avinash Kodi. "A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, no. 2 (2015): 186–98. http://dx.doi.org/10.1109/tcad.2014.2379640.

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Pathak, Divya, Houman Homayoun, and Ioannis Savidis. "Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 9 (2017): 2538–51. http://dx.doi.org/10.1109/tvlsi.2017.2699644.

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Kose, Selçuk, and Eby G. Friedman. "Distributed On-Chip Power Delivery." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2, no. 4 (2012): 704–13. http://dx.doi.org/10.1109/jetcas.2012.2226378.

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Dissertations / Theses on the topic "Power Chip on Chip"

1

Belfiore, Guido, Laszlo Szilagyi, Ronny Henker, and Frank Ellinger. "Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect." SPIE, 2015. https://tud.qucosa.de/id/qucosa%3A34801.

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This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm². The driver can achieve an error-free (<BER < 10^12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 2^7-1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

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Ochana, Andrew. "Power cycling of flip chip assemblies." Thesis, Loughborough University, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.418328.

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Mischenko, Alexandre. "On-chip cooling and power generation." Thesis, University of Cambridge, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.612857.

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Peter, Eldhose. "Power efficient on-chip optical interconnects." Thesis, IIT Delhi, 2016. http://localhost:8080/iit/handle/2074/7224.

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Wu, Wei-Chung. "On-chip charge pumps." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13451.

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Hamwi, Khawla. "Low Power Design Methodology and Photonics Networks on Chip for Multiprocessor System on Chip." Thesis, Brest, 2013. http://www.theses.fr/2013BRES0029.

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Les systèmes multiprocesseurs sur puce (MPSoC)s sont fortement émergent comme principaux composants dans les systèmes embarqués à hautes performances. La principale complexité dans la conception et l’implémentation des MPSoC est la communication entre les cœurs. Les réseaux sur puce (NoC) sont considérés comme la solution pour cet effet. ITRS prédit que des centaines de cœurs seront utilisées dans la génération future de système sur puce (SoC), ce qui va donc augmenter les coûts de l’évolutivité, de bande passante et de l’implémentation des réseaux sur puce (NoC)s. Ces problèmes sont présents dans diverses tendances technologiques dans le domaine des semiconducteurs et de la photonique. Cette thèse préconise l'utilisation de la synthèse NoC comme l'approche la plus appropriée pour exploiter ces tendances technologiques et rattraper les exigences des applications. A partir de plusieurs méthodologies de conception basées sur la technologie FPGA et des techniques d'estimation basse énergie (HLS) pour plusieurs IPs, nous proposons une implémentation ASIC basée sur la technologie 3D Tezzaron. Multi-FPGA technologie est utilisée pour valider la conception MPSoC avec 64 processeurs Butterfly NoC. La synthèse NoC est basée sur le regroupement de maîtres et d’esclaves générant des architectures asymétriques avec un soutien approprié pour les demandes très haut débit par optique NoC (ONoC), tandis que les demandes de bande passante inférieure sont traitées par électronique NoC. Une programmation linéaire est proposée comme une solution pour la synthèse NoC<br>Multiprocessor systems on chip (MPSoC)s are strongly emerging as main components in high performance embedded systems. Several challenges can be determined in MPSoC design like the challenge which comes from interconnect infrastructure. Network-on-Chip (NOC) with multiple constraints to be satisfied is a promising solution for these challenges. ITRS predicts that hundreds of cores will be used in future generation system on chip (SoC) and thus raises the issue of scalability, bandwidth and implementation costs for NoCs. These issues are raised within the various technological trends in semiconductors and photonics. This PhD thesis advocates the use of NoC synthesis as the most appropriate approach to exploit these technological trends catch up with the applications requirements. Starting with several design methodologies based on FPGA technology and low power estimation techniques (HLS) for several IPs, we propose an ASIC implementation based on 3D Tezzaron technology. Multi-FPGA technology is used to validate MPSoC design with up to 64 processors with Butterfly NoC. NoC synthesis is based on a clustering of masters and slaves generating asymmetric architectures with appropriate support for very high bandwidth requests through Optical NoC (ONoC) while lower bandwidth requests are processed by electronic NoC. A linear programming is proposed as a solution to the NoC synthesis

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Hamwi, Khawla. "Low Power Design Methodology and Photonics Networks on Chip for Multiprocessor System on Chip." Electronic Thesis or Diss., Brest, 2013. http://www.theses.fr/2013BRES0029.

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Les systèmes multiprocesseurs sur puce (MPSoC)s sont fortement émergent comme principaux composants dans les systèmes embarqués à hautes performances. La principale complexité dans la conception et l’implémentation des MPSoC est la communication entre les cœurs. Les réseaux sur puce (NoC) sont considérés comme la solution pour cet effet. ITRS prédit que des centaines de cœurs seront utilisées dans la génération future de système sur puce (SoC), ce qui va donc augmenter les coûts de l’évolutivité, de bande passante et de l’implémentation des réseaux sur puce (NoC)s. Ces problèmes sont présents dans diverses tendances technologiques dans le domaine des semiconducteurs et de la photonique. Cette thèse préconise l'utilisation de la synthèse NoC comme l'approche la plus appropriée pour exploiter ces tendances technologiques et rattraper les exigences des applications. A partir de plusieurs méthodologies de conception basées sur la technologie FPGA et des techniques d'estimation basse énergie (HLS) pour plusieurs IPs, nous proposons une implémentation ASIC basée sur la technologie 3D Tezzaron. Multi-FPGA technologie est utilisée pour valider la conception MPSoC avec 64 processeurs Butterfly NoC. La synthèse NoC est basée sur le regroupement de maîtres et d’esclaves générant des architectures asymétriques avec un soutien approprié pour les demandes très haut débit par optique NoC (ONoC), tandis que les demandes de bande passante inférieure sont traitées par électronique NoC. Une programmation linéaire est proposée comme une solution pour la synthèse NoC<br>Multiprocessor systems on chip (MPSoC)s are strongly emerging as main components in high performance embedded systems. Several challenges can be determined in MPSoC design like the challenge which comes from interconnect infrastructure. Network-on-Chip (NOC) with multiple constraints to be satisfied is a promising solution for these challenges. ITRS predicts that hundreds of cores will be used in future generation system on chip (SoC) and thus raises the issue of scalability, bandwidth and implementation costs for NoCs. These issues are raised within the various technological trends in semiconductors and photonics. This PhD thesis advocates the use of NoC synthesis as the most appropriate approach to exploit these technological trends catch up with the applications requirements. Starting with several design methodologies based on FPGA technology and low power estimation techniques (HLS) for several IPs, we propose an ASIC implementation based on 3D Tezzaron technology. Multi-FPGA technology is used to validate MPSoC design with up to 64 processors with Butterfly NoC. NoC synthesis is based on a clustering of masters and slaves generating asymmetric architectures with appropriate support for very high bandwidth requests through Optical NoC (ONoC) while lower bandwidth requests are processed by electronic NoC. A linear programming is proposed as a solution to the NoC synthesis

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Lai, Yin Hing. "High power flip-chip light emitting diode /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20LAI.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.<br>Includes bibliographical references (leaves 60-68). Also available in electronic version. Access restricted to campus users.

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Singhal, Rohit. "Data integrity for on-chip interconnects." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5929.

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With shrinking feature size and growing integration density in the Deep Sub- Micron (DSM) technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. Especially, in system-onchip (SoC) designs, where parallel interconnects run over large distances, they pose difficult research and design problems. This work presents an approach for evaluating the data carrying capacity of such wires. The method treats the delay and reliability in interconnects from an information theoretic perspective. The results point to an optimal frequency of operation for a given bus dimension for maximum data transfer rate. Moreover, this optimal frequency is higher than that achieved by present day designs which accommodate the worst case delays. This work also proposes several novel ways to approach this optimal data transfer rate in practical designs.From the analysis of signal propagation delay in long wires, it is seen that the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication theory, these "good" signals arriving early can be used to predict/correct the "few" signals that arrive late. In addition to this correction based on prediction, the approaches use coding techniques to eliminate high delay cases to generate a higher transmission rate. The work also extends communication theoretic approaches to other areas of VLSI design. Parity groups are generated based on low output delay correlation to add redundancy in combinatorial circuits. This redundancy is used to increase the frequency of operation and/or reduce the energy consumption while improving the overall reliability of the circuit.

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Oberle, Michael. "Low power systems-on-chip for biomedical applications /." [S.l.] : [s.n.], 2002. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=14509.

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Books on the topic "Power Chip on Chip"

1

Allard, Bruno, ed. Power Systems-On-Chip. John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.

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Silvano, Cristina, Marcello Lajolo, and Gianluca Palermo, eds. Low Power Networks-on-Chip. Springer US, 2011. http://dx.doi.org/10.1007/978-1-4419-6911-8.

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Silvano, Cristina. Low Power Networks-on-Chip. Springer Science+Business Media, LLC, 2011.

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Vaisband, Inna P., Renatas Jakushokas, Mikhail Popovich, Andrey V. Mezhiba, Selçuk Köse, and Eby G. Friedman. On-Chip Power Delivery and Management. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29395-0.

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Hu, John, and Mohammed Ismail. CMOS High Efficiency On-chip Power Management. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9526-1.

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Hu, John. CMOS High Efficiency On-chip Power Management. Springer Science+Business Media, LLC, 2011.

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Tanzawa, Toru. On-chip High-Voltage Generator Design. Springer New York, 2013.

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Tanzawa, Toru. On-chip high-voltage generator design. Springer, 2013.

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Jakushokas, Renatas, Mikhail Popovich, Andrey V. Mezhiba, Selçuk Köse, and Eby G. Friedman. Power Distribution Networks with On-Chip Decoupling Capacitors. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-7871-4.

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Popovich, Mikhhail, Andrey V. Mezhiba, and Eby G. Friedman. Power Distribution Networks with On-Chip Decoupling Capacitors. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-71601-5.

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Book chapters on the topic "Power Chip on Chip"

1

Veendrick, Harry. "Chip Performance and Power." In Bits on Chips. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-76096-4_11.

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Itoh, Kiyoo. "Low-Power Memory Circuits." In VLSI Memory Chip Design. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/978-3-662-04478-0_7.

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Schuermans, Stefan, and Rainer Leupers. "Network on Chip Experiments." In Power Estimation on Electronic System Level using Linear Power Models. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-01875-7_5.

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Alou, Pedro, José A. Cobos, Jesus A. Oliver, et al. "Control Strategies and CAD Approach." In Power Systems-On-Chip. John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch1.

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Kulkarni, Santosh, and Cian O'Mathuna. "Magnetic Components for Increased Power Density." In Power Systems-On-Chip. John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch2.

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Voiron, Frédéric. "Dielectric Components for Increased Power Density." In Power Systems-On-Chip. John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch3.

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Labbe, Benoît, and Bruno Allard. "On-board Power Management DC/DC Inductive Converter." In Power Systems-On-Chip. John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch4.

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Pillonnet, Gael, Thomas Souvignet, and Bruno Allard. "On-Chip Power Management DC/DC Switched-Capacitor Converter." In Power Systems-On-Chip. John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch5.

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Martin, Christian, Florian Neveu, and Bruno Allard. "High-Switching Frequency Inductive DC/DC Converters." In Power Systems-On-Chip. John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch6.

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Prodic, Aleksandar, Sheikh Mohammad Ahsanuzzaman, Behzad Mahdavikhah, and Timothy McRae. "Hybrid and Multi-level Converter Topologies for On-Chip Implementation of Reduced Voltage-Swing Converters." In Power Systems-On-Chip. John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch7.

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Conference papers on the topic "Power Chip on Chip"

1

Wang, Zihao, Dexian Yan, Wenze Yuan, et al. "Study on CPW Microwave Power Sensor Chip." In 2024 International Conference on Microwave and Millimeter Wave Technology (ICMMT). IEEE, 2024. http://dx.doi.org/10.1109/icmmt61774.2024.10672367.

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Wang, Peng, F. Patrick McCluskey, and Avram Bar-Cohen. "Isothermalization of an IGBT Power Electronic Chip." In ASME 2010 International Mechanical Engineering Congress and Exposition. ASMEDC, 2010. http://dx.doi.org/10.1115/imece2010-41019.

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Rapid increases in the power ratings and continued miniaturization of power electronic semiconductor devices have pushed chip heat fluxes well beyond the range of conventional thermal management techniques. The heat flux of power electronic chips for hybrid electric vehicles is now at the level of 100 to 150W/cm2 and is projected to increase to 500 W/cm2 in next generation vehicles. Such heat fluxes lead to higher and less uniform IGBT chip temperature, significantly degrading the device performance and system reliability. Maintaining the maximum temperature below a specified limit, while isothermalizing the surface of the chip, have become critical issues for thermal management of power electronics. In this work, a hybrid cooling system design, which combines microchannel liquid cooling and thermoelectric solid-state cooling, is proposed for thermal management of a 10mm × 10mm IGBT chip. The microchannel heat sink is used for global cooling of the chip while the embedded thermo-electric cooler is employed for isothermalization of the chip. A detailed package level 3D thermal model is developed to explore the potential application of this concept, with an attention focused on isothermalization and temperature reduction of IGBT chip associated with variations in thermoelectric cooler sizes, thermoelectric materials, cooling system designs, and trench structures in the DBC substrate. It is found that a thin-film superlattice TEC can deliver a superior cooling performance by eliminating more than 90% of the temperature non-uniformity on 100∼200 W/cm2 IGBT chips.

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Novotny, M., J. Jankovsky, and I. Szendiuch. "Chip Power Interconnection." In 2007 30th International Spring Seminar on Electronics Technology. IEEE, 2007. http://dx.doi.org/10.1109/isse.2007.4432844.

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Carley, Larry Richard. "Chip-to-chip RF Communications and Power Delivery via On-chip Antennas." In the 24th Annual International Conference. ACM Press, 2018. http://dx.doi.org/10.1145/3241539.3270100.

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Testa, Paolo Valerio, Vincent Ries, Corrado Carta, and Frank Ellinger. "200 GHz chip-to-chip wireless power transfer." In 2018 IEEE Radio and Wireless Symposium (RWS). IEEE, 2018. http://dx.doi.org/10.1109/rws.2018.8304962.

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Oveis-Gharan, Masoud, and Gul Khan. "Power and Chip-Area Aware Network-on-Chip Modeling for System on Chip Simulation." In Seventh International Conference on Simulation Tools and Techniques. ICST, 2014. http://dx.doi.org/10.4108/icst.simutools.2014.254626.

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Gonzalez-Nino, David, Lauren Boteler, Damian P. Urciuoli, Iain M. Kierzewski, Dimeji Ibitayo, and Pedro O. Quintero. "Multifunctional Chip for Use in Thermal Analysis of Power Systems." In ASME 2018 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2018. http://dx.doi.org/10.1115/ipack2018-8355.

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Many military electronic systems experience thermal transient pulses, in the sub-second range, during operation. Transient thermal solutions are being developed to address these transient pulses. In order to determine the performance of these thermal solutions, precise measurement of device junction temperature during the pulse is critical. Researchers have been patterning heaters onto chips using high temperature coefficient of resistance materials, thus allowing the use of the heater as a resistance temperature detector (RTD). For a given RTD material, in order to increase the sensitivity, a high resistance value is required; however, this equates to high voltages needed to get high heat fluxes. This work aims to design a test chip which balances between the instrumentation preferring a large resistance and the desire to maintain reasonable input voltages prompting a low resistance. This work demonstrates a novel multi-functional thermal test chip, which consists of 25 high resistance RTDs connected in parallel. This parallel connection strikes the desired balance by allowing a small overall chip resistance while allowing probing on a much higher resistance single RTD. Furthermore, this design allows optional temperature sensing at multiple locations on the chip’s surface, the possibility to create thermal gradients by controlled powering of individual resistors at different locations on the chip’s surface, and uniform heat flux over the entire chip surface.

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Parhizi, Mohammad, Ali Akbar Merrikh, and Ankur Jain. "Investigation of Two-Phase, Vapor Chamber Based Thermal Management of Multiple Microserver Chips." In ASME 2014 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2014. http://dx.doi.org/10.1115/imece2014-39928.

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Thermal management of microserver chips is of much interest to the semiconductor industry due to the significant performance benefits associated with heat spreading, resulting in very effective hot spot cooling in active cooling environments. This paper investigates thermal management of a multi-chip microserver module using two-phase heat transfer in a vapor chamber. A simulation model capturing two-phase flow of H2O in a vapor chamber was developed for understanding the effect of various parameters on thermal performance of the vapor chamber. The performance of a single high power chip is compared with a system of multiple lower power chips. Emphasis is on the impact of using multiple lower power chips instead of a single high power chip on the heat spreading capability of a flat, thin, vapor chamber. Also, it is shown that using a system of multiple low power chips, provides designers with the opportunity for designing vapor chamber with same functionality as single chip but reduced mass. Results highlight the challenges and opportunities involved in such an approach. The results shown in this paper will be useful for the design of two-phase cooling for microserver chips.

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FOK, C. W., and D. L. PULFREY. "FULL-CHIP POWER-SUPPLY NOISE: THE EFFECT OF ON-CHIP POWER-RAIL INDUCTANCE." In Proceedings of the 2002 Workshop on Frontiers in Electronics (WOFE-02). WORLD SCIENTIFIC, 2003. http://dx.doi.org/10.1142/9789812796912_0031.

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Roberts, Jordan, M. Kaysar Rahim, Jeffrey C. Suhling, Richard C. Jaeger, Pradeep Lall, and Ron Zhang. "Characterization of Die Stress Distributions in Area Array Flip Chip Packaging." In ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability. ASMEDC, 2009. http://dx.doi.org/10.1115/interpack2009-89383.

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On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during thermal cycling and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach also allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, initial experiments have been performed to analyze the effects of thermal cycling and power cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). Power cycling of selected parts was performed by exciting the on-chip heaters on the test chips with power levels typical of microprocessor die. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show some cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of temperature cycling duration are currently being correlated with the delaminations occurring at the interfaces between the die and underfill and the die and lid adhesive. In addition, finite element models of the packages are being developed and correlated with the data.

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Reports on the topic "Power Chip on Chip"

1

Rahman, Abdur, Mohammad Marufuzzaman, Jason Street, et al. A comprehensive review on wood chip moisture content assessment and prediction. Engineer Research and Development Center (U.S.), 2024. http://dx.doi.org/10.21079/11681/48220.

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Wood chips are the primary sources of raw materials for numerous industries, including pelleting mills, biorefineries, pulp-and-paper industries, and biomass-based power generation facilities. Unfortunately, when wood chips are utilized as a renewable and environmentally friendly resource, industries are constantly challenged by the consistency of the wood chip qualities (e.g., moisture/ash contents, size distributions) - a historically recognized problem on a global scale. Among other wood chip quality attributes, the moisture content is considered the most pressing one as it directly impacts the energy content, storage stability, and handling properties of the raw and finished products. Therefore, accurate wood chip moisture content prediction can help optimize the drying process and reduce energy consumption. In this review, a survey was conducted on various techniques and models employed for predicting wood chip moisture content. The advantages and limitations of these approaches, as well as their potential applications and future directions were also discussed. This review aims to provide a comprehensive overview of the current state-of-the-art in wood chip moisture content prediction and to highlight the challenges and opportunities for further research and development in this field.

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2

Lee, Fred, Qiang Li, Yipeng Su, et al. Power Supplies on a Chip (PSOC). Office of Scientific and Technical Information (OSTI), 2015. http://dx.doi.org/10.2172/1167001.

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3

Mehrotra, Vivek. Integrated Power Chip Converter for Solid State Lighting. Office of Scientific and Technical Information (OSTI), 2013. http://dx.doi.org/10.2172/1569260.

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4

Michelogiannakis, George, and John Shalf. Variable-Width Datapath for On-Chip Network Static Power Reduction. Office of Scientific and Technical Information (OSTI), 2013. http://dx.doi.org/10.2172/1164909.

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SCHROEPPEL, RICHARD C., CHERYL L. BEAVER, TIMOTHY J. DRAELOS, RITA A. GONZALES, and RUSSELL D. MILLER. A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip. Office of Scientific and Technical Information (OSTI), 2002. http://dx.doi.org/10.2172/802030.

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6

Pande, Kanupriya. Power Chic. Iowa State University, Digital Repository, 2014. http://dx.doi.org/10.31274/itaa_proceedings-180814-991.

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7

Horowitz, Mark, Don Stark, Zain Asgar, et al. Chip Generators Study. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada505937.

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VIANCO, PAUL T., and STEVEN N. BURCHETT. Solder Joint Reliability Predictions for Leadless Chip Resistors, Chip Capacitors, and Ferrite Chip Inductors Using the SRS Software. Office of Scientific and Technical Information (OSTI), 2001. http://dx.doi.org/10.2172/783992.

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9

Dally, William J., and Charles L. Seitz. The Torus Routing Chip. Defense Technical Information Center, 1986. http://dx.doi.org/10.21236/ada442968.

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10

Solomon, Emilia A. NMJ-on-a-chip. Office of Scientific and Technical Information (OSTI), 2018. http://dx.doi.org/10.2172/1459852.

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