Relevant bibliographies by topics / Power-delay product

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Power-delay product'

Author: Grafiati
Published: 4 June 2021
Last updated: 11 February 2022

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Journal articles on the topic "Power-delay product"

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Baba Fayaz, D., and Patri Sreehari Rao. "Power‐efficient voltage up level shifter with low power–delay product." International Journal of Circuit Theory and Applications 49, no. 7 (February 22, 2021): 2158–69. http://dx.doi.org/10.1002/cta.2980.

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Xue, H., and S. Ren. "Low power‐delay‐product dynamic CMOS circuit design techniques." Electronics Letters 53, no. 5 (March 2017): 302–4. http://dx.doi.org/10.1049/el.2016.4173.

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Saini, Jitendra Kumar, Avireni Srinivasulu, and Renu Kumawat. "A Low Power - High Speed CNTFETs Based Full Adder Cell With Overflow Detection." Micro and Nanosystems 11, no. 1 (April 2, 2019): 80–87. http://dx.doi.org/10.2174/1876402911666190211154634.

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The transformation from the development of enabling technology to mass production of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the product as implicit pre-cursors. The Carbon Nanotube Field Effect Transistor (CNFET) is the present day technology. In this manuscript, we have used CNFET as the enabling technology to design a 1-bit Full Adder (1b-FA16) with overflow detection. The proposed 1b-FA16 is designed using 16 transistors. Finally, the proposed 1b-FA16 is further used to design a Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) circuit and RCA with overflow bit detection. Methods and Results: The proposed 1b-FA16 circuit was designed with CNFET technology simulated at 32 nm with a voltage supply of +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM. Comparison of the existing full adder designs with the proposed 1b-FA16 design was done to validate the improvements in terms of power, delay and Power Delay Product (PDP). Table 2, shows the results of comparison for the proposed 1b-FA16 with the existing full adder designs implemented using CNFET for parameters like power, delay and power delay product. Conclusion: It can be concluded that the proposed 1b-FA16 yielded better results as compared to the existing full adder designs implemented using CNFET. The improvement in power, delay and power delay product was approximately 11%, 9% and 24% respectively. Hence, the proposed circuit implemented using CNFET gives a substantial rate of improvements over the existing circuits.
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Kavitha, V., and S. Mohanraj. "Power Efficient MAC Unit Based Digital PID Controllers." JOURNAL OF ADVANCES IN CHEMISTRY 12, no. 9 (November 3, 2016): 4324–29. http://dx.doi.org/10.24297/jac.v12i9.4090.

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Proper closed loop has been an ever hot issue in the automotive industry. The industrial equipments governed by PID controllers have very simple control architecture and efficiency but still they find a trouble dueto large power consumption and slow mathematical computation. Many researchers have worked out and are trying to design a low power, less delay PID. This paper reviews three MAC architectures with array, booth and wallace tree multipliers incorporated in PID architecture. The simulations are done and the area, power, delay results are synthesized using Xilinx ISE. Comparisons are made between these three architectures in terms of power delay product and area delay product.
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., T. P. Darewar. "ENHANCEMENT IN POWER-DELAY PRODUCT BY DRIVER AND INTERCONNECT OPTIMIZATION." International Journal of Research in Engineering and Technology 03, no. 06 (June 25, 2014): 411–17. http://dx.doi.org/10.15623/ijret.2014.0306076.

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Liu, Pei, Tian Zhao, Feng Liang, Jizhong Zhao, and Peilin Jiang. "A power-delay-product efficient and SEU-tolerant latch design." IEICE Electronics Express 14, no. 23 (2017): 20170972. http://dx.doi.org/10.1587/elex.14.20170972.

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Jso-Sun Choi and Kwyro Lee. "Design of CMOS tapered buffer for minimum power-delay product." IEEE Journal of Solid-State Circuits 29, no. 9 (1994): 1142–45. http://dx.doi.org/10.1109/4.309912.

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Han, Zitong. "The power-delay product and its implication to CMOS Inverter." Journal of Physics: Conference Series 1754, no. 1 (February 1, 2021): 012131. http://dx.doi.org/10.1088/1742-6596/1754/1/012131.

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Meghana, Madabhushi Sai. "Low Power and Fast Full Adder by Exploring New XOR and XNOR Gates." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 20, 2021): 1956–63. http://dx.doi.org/10.22214/ijraset.2021.35286.

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In this project, novel circuits for FULL ADDER are proposed using new XOR or XNOR gates. The conventional design of XOR or XNOR gates shows that the not gate in the schematic has drawbacks. So by investigating advanced XOR or XNOR gates we proposed the schematic design. The proposed schematics are optimized in terms of speed, delay, power and power delay product. We developed six novel hybrid full adder schematics based on exploring new XOR or XNOR gates. Each designed schematics have their specifications of energy consumption, delay, power delay product. To simulate the performance of the proposed designs, we use mentor graphics, tanner tool. The simulation yields a 45-nm CMOS innovation model that focuses on the proposed plans having best speed and power other than the plan of any full adder. The proposed Full Adders has 2-28% increment in consumption of energy and power delay product compared to other design schematics. The proposed hybrid full adders are investigated with voltage 1.8V, speed ,size of transistors, area, power consumption and delay.
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Cao, Ruiping, and Jianping Hu. "Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits." Journal of Electrical and Computer Engineering 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/836019.

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In high-speed applications, MOS current mode logic (MCML) is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP). However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML) circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.
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Dissertations / Theses on the topic "Power-delay product"

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Yongyi, Yuan. "Investigation and implementation of data transmission look-ahead D flip-flops." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2529.

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This thesis investigates four D flip-flops with data transmission look-ahead circuits. Based on logical effort and power-delay products to resize all the transistor widths along the critical path in µm CMOS technology. The main goal is to verify and proof this kind of circuits can be used when the input data have low switching probabilities. From comparing the average energy consumption between the normal D flip-flops and D flip-flops with look-ahead circuits, D flip-flops with look-ahead circuits consume less power when the data switching activities are low.

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Llanos, Roger Vicente Caputo. "Voltage scaling interfaces for multi-voltage digital systems." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/159617.

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Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação.
Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.
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Chou, Yung-Pei, and 周詠備. "Low Power-Delay-Product Full Adder Design." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/30223752083979381214.

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碩士
國立高雄大學
電機工程學系碩士班
97
In this thesis, we propose a low power-delay product full adder designed in hybrid logic which combines the concepts of static logic, dynamic logic, and multi-threshold CMOS. In this design, the circuit for sum and the circuit for carry out are designed separately for alleviating the loading effect in the interconnections. The multi-threshold CMOS technology does reduce the leakage current either in the circuit for sum or the circuit for carry out. The whole simulations are performed by HSPICE with TSMC 0.18-μm 1P6M process technology. The simulation results show that the proposed full adder can achieve a power-delay product of 0.063 pJ for sum block and 0.021 pJ for carry out block at 400 MHz.
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JIAN, WEN-TONG, and 簡文通. "CMOS power-delay product verification using signal probability." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/71046326375953588270.

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Karakaya, Fuat. "Automated exploration of the asic design space for minimum power-delay-area product at the register transfer level." 2004. http://etd.utk.edu/2004/KarakayaFuat.pdf.

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Thesis (Ph. D.)--University of Tennessee, Knoxville, 2004.
Title from title page screen (viewed May 13, 2004). Thesis advisor: Donald W. Bouldin. Document formatted into pages (x, 102 p. : ill. (some col.)). Vita. Includes bibliographical references (p. 99-101).
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Tsai, Hsiu-Chun, and 蔡修群. "A High Voltage Bidirectional Current Sensor and A Single-ended Disturb-free 6T SRAM with Low Power-Delay Product." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/537n9w.

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碩士
國立中山大學
電機工程學系研究所
107
This thesis investigates two research topics, including a high voltage bidirectional current sensor and a low power SRAM design. The current sensor was realized by TSMC 0.50 m CMOS High Voltage Mixed Signal Based LDMOS AI_USG Polycide 2P3M (T50UHV) Process to justify the expected accuracy of current detection. The singleended disturb-free 6T SRAM demonstrated in the second topic is realized by TSMC 45 nm CMOS LOGIC General Purpose Superb (40G) ELK Cu 1P10M 0.9/2.5V (TN40G) Process to enhance the stability which would be severely affected by the large leakage current in deep sub-micro CMOS technologies. The HV current sensor was designed monitor the battery current such that it is able to be applied in battery management systems. By taking advantage of a current mirror and a comparator to sense the current direction such that the charging or discharging status can be decided. Moreover, a T flip-flop is used to control a switch to achieve more precise current sensing. The simulation results show that the input voltage range of the battery string is from 8 V to 20 V and the sensing error is better than 0.85 %. The second topic means to improve the single-ended disturb-free SRAM developed by our laboratory. To avoid data hazard caused by leakage current when the memory cell in the read mode, an NMOS transistor is added at the foot to drain a leakage current path to isolate the data state in memory cell from noise. Moreover, the simulation results of average power-delay product (PDP) is improved by 11.41 % and the energy/access is 0.306 pJ. Keyword: current sensor, battery management system, static random access memory, leakage current, read stability
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Yadav, Avinash. "Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness." Thesis, 2020. http://hdl.handle.net/1805/24772.

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Indiana University-Purdue University Indianapolis (IUPUI)
In this thesis, we investigated the 7 nm FinFET technology for its delay-power product performance. In our study, we explored the ASAP7 library from Arizona State University, developed in collaboration with ARM Holdings. The FinFET technology was chosen since it has a subthreshold slope of 60mV/decade that enables cells to function at 0.7V supply voltage at the nominal corner. An emphasis was focused on characterizing the Non-Ideal effects, delay variation, and power for the FinFET device. An exhaustive analysis of the INVx1 delay variation for different operating conditions was also included, to assess the robustness. The 7nm FinFET device was then employed into 6T SRAM cells and 16 function ALU. The SRAM cells were approached with advanced multi-corner stability evaluation. The system-level architecture of the ALU has demonstrated an ultra-low power system operating at 1 GHz clock frequency.
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Book chapters on the topic "Power-delay product"

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Mishra, Vishwas, and Shyam Akashe. "Calculation of Power Delay Product and Energy Delay Product in 4-Bit FinFET Based Priority Encoder." In Springer Proceedings in Physics, 283–89. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2367-2_36.

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Sakshi Bhatnagar, Harsh Gupta, and Swapnil Jain. "Modified D-Latch Enabled BEC1 Carry-Select Adder with Low Power-Delay Product and Area Efficiency." In Proceedings of the International Conference on Recent Cognizance in Wireless Communication & Image Processing, 441–49. New Delhi: Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2638-3_51.

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Gupta, Mangaldeep, B. P. Pandey, and R. K. Chauhan. "CMOS-Based XOR Gate Design for Full Swing Output Voltage and Minimum Power Delay Product (PDP)." In Intelligent Computing and Communication, 99–107. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1084-7_11.

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Ahmed, Jameel, Mohammed Yakoob Siyal, Shaheryar Najam, and Zohaib Najam. "Energy-Delay Product and Throughput." In Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System, 17–22. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-3120-5_2.

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Gupta, Priya, Anu Gupta, and Abhijit Asati. "Detailed Analysis of Ultra Low Power Column Compression WALLACE and DADDA Multiplier in Sub-Threshold Regime." In Advances in Computational Intelligence and Robotics, 78–123. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-9474-3.ch004.

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In this chapter, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace and Dadda in sub-threshold regime. In order to reduce the hardware which ultimately reduces area, power and overall power delay product, an energy efficient basic modules of the multipliers like AND gates, half adders, full adders and partial product generate units have been analyzed for sub-threshold operation. At the last stage ripple carry adder is used in both multipliers. The performance metrics considered for the analysis of the multipliers are: power, delay and PDP. Simulation studies are carried out for 8x8-bit and 16x16-bit input data width. The proposed circuits show energy efficient results with Spectre simulations for the TSMC 180nm CMOS technology at 0.4V supply voltage. The proposed multipliers so implemented outperform its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional multipliers.
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Singh, Gurmohan, Manjit Kaur, and Yadwinder Kumar. "CNTFET for Logic Gates Design." In Advances in Computer and Electrical Engineering, 54–71. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1393-4.ch004.

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The novel characteristics of CNTFET have eliminated many technological and fundamental hindrances being faced by CMOS transistors. CNTFET is emerging as prospective replacement for CMOS transistors in digital circuits and systems. This chapter introduces design of CNTFET-based basic logic gates. The basic logic gates analyzed are inverter, NAND, and NOR gates. The designed gates are evaluated in terms of delay, power consumption, and figure-of-merit power-delay-product (PDP). The standard H-SPICE CNTFET model of Stanford University has been used for all simulations. The impact of dielectric material variations on performance parameters of carbon nanotube field effect transistor based universal gates has been analyzed. Comparison between CMOS and CNTFET-based logic circuits is carried out for different dielectric material at 16 nm technology node.
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Sandha, Karmjit Singh. "CNT as Interconnects." In Advances in Computer and Electrical Engineering, 130–59. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1393-4.ch007.

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The chapter will start with brief introduction to the interconnects and its importance in an integrated circuit at deep sub-micron technology nodes. The brief discussion about the concept of scaling, interconnects models, and material in use are presented. The limitations of conventional materials at scaled down technology nodes will be discussed next. The focus of the chapter is to present the electrical equivalent circuit model to estimate the impedance parameters of SWCNT bundle and MWCNT bundle as interconnects at different nano-scaled technology nodes for global level interconnect length. Using ESC model of SWCNT, MWCNT, and copper, the performance comparative analysis for delay and power delay product (PDP) will be presented for different interconnect lengths at nano-scaled technology nodes. Finally, the chapter summary and conclusion will be written at the end of the chapter.
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Layne-Farrar, Anne. "Assessing IPR Disclosure within Standard Setting." In Advances in IT Standards and Standardization Research, 86–105. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-6332-9.ch006.

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As part of its “policy project to examine the legal and policy issues surrounding the problem of potential patent ‘hold-up' when patented technologies are included in collaborative standards,” the Federal Trade Commission held an all-day workshop on June 21, 2011. The first panel of the day focused on patent disclosure rules intended to encourage full knowledge of patents “essential” for a standard and therefore to prevent patent ambush. When patents are disclosed after a standard is defined, the patent holder may have enhanced bargaining power that it can exploit to charge excessive royalties (e.g., greater than the value the patented technology contributes to the product complying with the standard). In this chapter, the authors present a case study on patent disclosure within the ICT sector. Specifically, they take an empirical look at the timing of patent disclosures within the European Telecommunications Standards Institute, the body responsible for some of the world's most prevalent mobile telephony standards. They find that most members officially disclose their potentially relevant patents after the standard is published, and sometimes considerably so. On the other hand, the authors also find that the delay in declaring patents to ETSI standards has been shrinking over time, with disclosures occurring closer to (although for the most part still after) the standard publication date for more recent standard generations as compared to earlier ones. This latter finding coincides with ETSI policy changes, suggesting that standards bodies may be able to improve patent disclosure with more precise rules.
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Gent, Stephen E., and Mark J. C. Crescenzi. "China." In Market Power Politics, 170–205. Oxford University Press, 2021. http://dx.doi.org/10.1093/oso/9780197529805.003.0007.

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This chapter examines how the pursuit of market power over rare earth elements (REEs) influences China’s use of strategic delay in East and South China Seas. As the dominant global producer of REEs, China has the ability to set prices in this market. The desire to maintain this market power motivates China to continue to push its long-standing claims to sovereignty over seabed resources in the East and South China Seas. International institutions such as UNCLOS and the International Seabed Authority do not provide a dispute-resolution option that allows China to maintain unfettered access to deep sea mineral extraction. At the same time, China’s economic dependence on Japan and the global REE market constrains China from turning to military escalation to press its claims. Instead, China has relied upon strategic delay and gray zone tactics to gradually expand its presence in the East and South China Seas.
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Krim, Saber, Soufien Gdaim, Abdellatif Mtibaa, and Mimouni Mohamed Faouzi. "A Position Control With a Field Programmable Gate Array-Sun-Tracking System for Photovoltaic Panels." In Advances in System Dynamics and Control, 192–231. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-4077-9.ch007.

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Photovoltaic system applications should operate under good conditions. The maximum power point depends on the sunlight angle on the panel surface. In this chapter, an induction motor (IM) controlled with a direct torque control (DTC) is used to control the photovoltaic panel position. The conventional DTC is chosen thanks to its capability to develop the maximum of torque when the motor is standstill. However, the DTC produces a torque with high ripples and it is suffer from the flux demagnetization phenomenon, especially at low speed. To overcome these problems, two DTC approaches are proposed in this chapter: (1) the DTC based on the fuzzy logic and (2) the DTC based on space vector modulation (SVM) and proportional integral (PI) controllers (DTC-SVM-PI). The suggested approaches are implemented on a field programmable gate array (FPGA) Virtex 5 circuit in order to reduce the sampling period of the system and the delay in the control loop. The simulation and hardware implementation results demonstrate that the DTC-SVM-PI offers best the results in terms of ripples.
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Conference papers on the topic "Power-delay product"

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Maheshwari, Sachin, Jimit Patel, Sumit K. Nirmalkar, and Anu Gupta. "Logical effort based power-delay-product optimization." In 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE, 2014. http://dx.doi.org/10.1109/icacci.2014.6968530.

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Rashid, M., and A. Muhtaroglu. "Power delay product optimized hybrid full adder circuits." In 2017 International Artificial Intelligence and Data Processing Symposium (IDAP). IEEE, 2017. http://dx.doi.org/10.1109/idap.2017.8090319.

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Caruso, Giuseppe, and Alessio Macchiarella. "Minimum power-delay product design of MCML gates." In 2008 International Conference on Signals and Electronic Systems. IEEE, 2008. http://dx.doi.org/10.1109/icses.2008.4673370.

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Deepa, K., and K. S. Deepika. "Keeper topology for optimization of power delay product." In 2014 International Conference on Electronics and Communication Systems (ICECS). IEEE, 2014. http://dx.doi.org/10.1109/ecs.2014.6892580.

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Ganesh Kumar, G., and Subhendu K. Sahoo. "Power-delay product minimization in high-performance fixed-width multiplier." In TENCON 2015 - 2015 IEEE Region 10 Conference. IEEE, 2015. http://dx.doi.org/10.1109/tencon.2015.7372864.

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Dutt, Shantanu, and Ouwen Shi. "Power-delay product based resource library construction for effective power optimization in HLS." In 2017 18th International Symposium on Quality Electronic Design (ISQED). IEEE, 2017. http://dx.doi.org/10.1109/isqed.2017.7918321.

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Elgreatly, Aimed Lutfi, Aimed Ahmed Shaaban, and El-Sayed M. El-Rabaie. "Enhancing Power Delay Product in DRAMs using resonant tunneling diode buffer." In 2015 27th International Conference on Microelectronics (ICM). IEEE, 2015. http://dx.doi.org/10.1109/icm.2015.7438030.

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Bolla, Raffaele, Roberto Bruschi, Franco Davoli, and Paolo Lago. "Optimizing the power-delay product in energy-aware packet forwarding engines." In 2013 24th Tyrrhenian International Workshop on Digital Communications - Green ICT (TIWDC). IEEE, 2013. http://dx.doi.org/10.1109/tiwdc.2013.6664195.

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Chren, William A. "Low delay-power product CMOS design using one-hot residue coding." In the 1995 international symposium. New York, New York, USA: ACM Press, 1995. http://dx.doi.org/10.1145/224081.224107.

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Chaitanya, Ch V. S., and Psathish Kumar. "Design and Analysis of Booth Multiplier with Optimised Power Delay Product." In 2018 International Conference on Computer Communication and Informatics (ICCCI). IEEE, 2018. http://dx.doi.org/10.1109/iccci.2018.8441236.

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