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Journal articles on the topic 'Power-delay product'

Author: Grafiati

Published: 4 June 2021

Last updated: 11 February 2022

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1

Baba Fayaz, D., and Patri Sreehari Rao. "Power‐efficient voltage up level shifter with low power–delay product." International Journal of Circuit Theory and Applications 49, no. 7 (February 22, 2021): 2158–69. http://dx.doi.org/10.1002/cta.2980.

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2

Xue, H., and S. Ren. "Low power‐delay‐product dynamic CMOS circuit design techniques." Electronics Letters 53, no. 5 (March 2017): 302–4. http://dx.doi.org/10.1049/el.2016.4173.

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3

Saini, Jitendra Kumar, Avireni Srinivasulu, and Renu Kumawat. "A Low Power - High Speed CNTFETs Based Full Adder Cell With Overflow Detection." Micro and Nanosystems 11, no. 1 (April 2, 2019): 80–87. http://dx.doi.org/10.2174/1876402911666190211154634.

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The transformation from the development of enabling technology to mass production of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the product as implicit pre-cursors. The Carbon Nanotube Field Effect Transistor (CNFET) is the present day technology. In this manuscript, we have used CNFET as the enabling technology to design a 1-bit Full Adder (1b-FA16) with overflow detection. The proposed 1b-FA16 is designed using 16 transistors. Finally, the proposed 1b-FA16 is further used to design a Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) circuit and RCA with overflow bit detection. Methods and Results: The proposed 1b-FA16 circuit was designed with CNFET technology simulated at 32 nm with a voltage supply of +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM. Comparison of the existing full adder designs with the proposed 1b-FA16 design was done to validate the improvements in terms of power, delay and Power Delay Product (PDP). Table 2, shows the results of comparison for the proposed 1b-FA16 with the existing full adder designs implemented using CNFET for parameters like power, delay and power delay product. Conclusion: It can be concluded that the proposed 1b-FA16 yielded better results as compared to the existing full adder designs implemented using CNFET. The improvement in power, delay and power delay product was approximately 11%, 9% and 24% respectively. Hence, the proposed circuit implemented using CNFET gives a substantial rate of improvements over the existing circuits.

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4

Kavitha, V., and S. Mohanraj. "Power Efficient MAC Unit Based Digital PID Controllers." JOURNAL OF ADVANCES IN CHEMISTRY 12, no. 9 (November 3, 2016): 4324–29. http://dx.doi.org/10.24297/jac.v12i9.4090.

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Proper closed loop has been an ever hot issue in the automotive industry. The industrial equipments governed by PID controllers have very simple control architecture and efficiency but still they find a trouble dueto large power consumption and slow mathematical computation. Many researchers have worked out and are trying to design a low power, less delay PID. This paper reviews three MAC architectures with array, booth and wallace tree multipliers incorporated in PID architecture. The simulations are done and the area, power, delay results are synthesized using Xilinx ISE. Comparisons are made between these three architectures in terms of power delay product and area delay product.

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., T. P. Darewar. "ENHANCEMENT IN POWER-DELAY PRODUCT BY DRIVER AND INTERCONNECT OPTIMIZATION." International Journal of Research in Engineering and Technology 03, no. 06 (June 25, 2014): 411–17. http://dx.doi.org/10.15623/ijret.2014.0306076.

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6

Liu, Pei, Tian Zhao, Feng Liang, Jizhong Zhao, and Peilin Jiang. "A power-delay-product efficient and SEU-tolerant latch design." IEICE Electronics Express 14, no. 23 (2017): 20170972. http://dx.doi.org/10.1587/elex.14.20170972.

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7

Jso-Sun Choi and Kwyro Lee. "Design of CMOS tapered buffer for minimum power-delay product." IEEE Journal of Solid-State Circuits 29, no. 9 (1994): 1142–45. http://dx.doi.org/10.1109/4.309912.

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8

Han, Zitong. "The power-delay product and its implication to CMOS Inverter." Journal of Physics: Conference Series 1754, no. 1 (February 1, 2021): 012131. http://dx.doi.org/10.1088/1742-6596/1754/1/012131.

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9

Meghana, Madabhushi Sai. "Low Power and Fast Full Adder by Exploring New XOR and XNOR Gates." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 20, 2021): 1956–63. http://dx.doi.org/10.22214/ijraset.2021.35286.

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In this project, novel circuits for FULL ADDER are proposed using new XOR or XNOR gates. The conventional design of XOR or XNOR gates shows that the not gate in the schematic has drawbacks. So by investigating advanced XOR or XNOR gates we proposed the schematic design. The proposed schematics are optimized in terms of speed, delay, power and power delay product. We developed six novel hybrid full adder schematics based on exploring new XOR or XNOR gates. Each designed schematics have their specifications of energy consumption, delay, power delay product. To simulate the performance of the proposed designs, we use mentor graphics, tanner tool. The simulation yields a 45-nm CMOS innovation model that focuses on the proposed plans having best speed and power other than the plan of any full adder. The proposed Full Adders has 2-28% increment in consumption of energy and power delay product compared to other design schematics. The proposed hybrid full adders are investigated with voltage 1.8V, speed ,size of transistors, area, power consumption and delay.

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10

Cao, Ruiping, and Jianping Hu. "Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits." Journal of Electrical and Computer Engineering 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/836019.

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In high-speed applications, MOS current mode logic (MCML) is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP). However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML) circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

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11

Abid, Z., Dalia A. El-Dib, and Rizwan Mudassir. "Modified Operand Decomposition Multiplication for High Performance Parallel Multipliers." Journal of Circuits, Systems and Computers 25, no. 12 (September 2, 2016): 1650149. http://dx.doi.org/10.1142/s0218126616501498.

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A low power operand decomposition multiplication architecture implementation is modified to further reduce its power dissipation and delay. First, the multiplier’s implementation was modified to generate the partial products using NAND gates instead of AND and OR gates in order to reduce the number of transistors (area utilized) and to reduce the delay. Then, new types of adders and (4:2) compressors, that accept negatively weighted bits are used to reduce the number of inverters. Therefore, the resulting multiplier architecture reduces the number of transistors significantly. These modifications result in 20% and 36% reduction in power consumption and energy delay product (EDP), respectively.

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12

Pandey, A. K., R. A. Mishra, and R. K. Nagaria. "Static Switching Dynamic Buffer Circuit." Journal of Engineering 2013 (2013): 1–11. http://dx.doi.org/10.1155/2013/646214.

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We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

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13

Morad, Milad Jalalian Abbasi, Seyyed Reza Talebiyan, and Ebrahim Pakniyat. "Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications." Ciência e Natura 37 (December 19, 2015): 285. http://dx.doi.org/10.5902/2179460x20784.

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This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. Using a novel structure for implementation of the proposed full adder caused it has better performance in terms of propagation delay and power-delay product (PDP) compared to its counterparts. According to the simulation results, the propagation delay of the proposed full adder is 22.8% less than the propagation delay of next fastest full adder, and the power-delay product of the proposed full adder is 22.7% less than the next best PDP. HSpice simulations using 65nm technology with a power supply of 1.2V was utilized to evaluate the performance of the circuits.

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14

OH, M. H. "Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 5 (May 1, 2005): 1379–83. http://dx.doi.org/10.1093/ietfec/e88-a.5.1379.

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15

Jain, Anjana, Remya Susan, Sanjana Accamma, Susan Jose, and Ashly John. "A Comparative Study on the Power Delay Product of Efficient Adders." International Journal of Computer Applications 163, no. 3 (April 17, 2017): 33–36. http://dx.doi.org/10.5120/ijca2017913491.

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16

Gupta, Deepika, Nitin Tiwari, and R. K. Sarin. "Analysis of Modified Feed-Through Logic with Improved Power Delay Product." International Journal of Computer Applications 69, no. 5 (May 17, 2013): 5–8. http://dx.doi.org/10.5120/11836-7557.

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17

Chren, W. A. "One-hot residue coding for low delay-power product CMOS design." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 3 (March 1998): 303–13. http://dx.doi.org/10.1109/82.664236.

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18

Kwak, Sang-Hoon, Jeong-Gun Lee, and Jeong-A. Lee. "Power-Delay Product Optimization of Heterogeneous Adder Using Integer Linear Programming." Journal of the Korea Society of Computer and Information 15, no. 10 (October 31, 2010): 1–9. http://dx.doi.org/10.9708/jksci.2010.15.10.001.

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19

Pasala, Raja Prakasha Rao, and Rajendra Naik Bhukya. "An Efficient Power Delay Product of ZigBee Transmitter Using Verilog HDL." IOSR Journal of Electronics and Communication Engineering 12, no. 03 (July 2017): 18–26. http://dx.doi.org/10.9790/2834-1203041826.

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20

Prasada G.S, Sai Venkatramana, G. Seshikala, and S. Niranjana. "Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 13, no. 6 (November 4, 2020): 864–70. http://dx.doi.org/10.2174/2352096513666200107091932.

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Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

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21

Vo, Minh. "Comparative Study on Power Gating Techniques for Lower Power Delay Product, Smaller Power Loss, Faster Wakeup Time." EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 5, no. 15 (September 19, 2018): 155236. http://dx.doi.org/10.4108/eai.27-6-2018.155236.

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22

Dattatraya, Kore Sagar, Belgudri Ritesh Appasaheb, Ramdas Bhanudas Khaladkar, and V. S. Kanchana Bhaaskaran. "Low Power, High Speed and Area Efficient Binary Count Multiplier." Journal of Circuits, Systems and Computers 25, no. 04 (February 2, 2016): 1650027. http://dx.doi.org/10.1142/s0218126616500274.

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Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

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23

Nagarajan, P., N. Ashok Kumar, and P. Venkat Ramana. "Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems." International Journal of Wavelets, Multiresolution and Information Processing 18, no. 01 (June 11, 2019): 1941009. http://dx.doi.org/10.1142/s0219691319410091.

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The flip-flops are considered as major contributors to the power dissipation of the clocking system, which is made up of the clock provision network and storage elements (latches, flip-flops). The power- and delay-efficient new implicit-pulsed dual-edge triggering flip-flop circuit (IP-DETFF) is proposed with two latching stages by employing an implicit-pulse triggering, dual-edge clocking and reducing the number of clocked loads. This leads to the reduction of power consumption due to clock allocation tree (pclk-tree) and reduces the delay time. The dual-edge clocking technique is incorporated into this proposed design without an increment of the number of transistors and minimizes the operating frequency as half. This methodology is also employed in this proposed design to construct new latching part of the flip-flop circuit. The performance of proposed flip-flop is analyzed by simulating the circuit at 0.12[Formula: see text][Formula: see text]m CMOS (complementary metal oxide semiconductor) process technology. The simulation results show that the proposed design achieves power saving from 11.22% to 54.81%, improvement of speed from 67% to 71.50%, power-delay product (PDP) from 74.85% to 81.26 %, energy-delay product (EDP) from 87.86% to 92.4% and power-energy product (PEP) from 75.24% to 93.57% compared to the conventional flip-flops.

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24

Babu CH, Ashok, J. V.R. Ravindra, and K. Lalkishore. "Design of ALU System Using Novel PMOS and NMOS for Low Power and High Speed Applications." International Journal of Engineering & Technology 7, no. 2.23 (April 20, 2018): 498. http://dx.doi.org/10.14419/ijet.v7i2.23.15343.

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This paper tailors 8 bit ALU for high speed and low power applications. In this design a novel PMOS and NMOS are used in place of conventional PMOS and NMOS. The main disadvantage of conventional PMOS and NMOS is low speed. With the technique of forward body biasing a novel PMOS and NMOS are derived and speed is improved. For each sub module of ALU power delay product percentage is calculated. Percentage improvement in power delay product of Novel ALU is shown in table 27.

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25

Kumar, Manoj, Sandeep K. Arya, and Sujata Pandey. "Low power CMOS full adder design with body biasing approach." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 75–80. http://dx.doi.org/10.29292/jics.v6i1.341.

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In this paper, five different low power full adders using XOR/XNOR gates and multiplexer blocks with body biasing have been presented. In the first methodology, the adder depicts minimum power dissipation of 204.09μW and delay of 5.9849 ns. In the second, an improvement in power consumption has been reported at 128.92μW with delay of 5.9875 ns by using voltage biasing of two PMOS (P1 &P2) along with substrate biasing. In the third methodology, adder gives minimum power dissipation of 0.223nW with a delay of 5.2352 ns. Further, in fourth, it shows minimum power consumption of 0.199nW with a delay of 5.1002 ns and finally in fifth methodology, minimum power reduces to 0.192nW.Moreover, power delay product (PDP) results also have been compared for these methodologies. Comparisons have been made with earlier reported circuits and proposed circuits show better performance in terms of power consumption and delay.

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26

CHANG, ROBERT C., HSIN-LEI LIN, and I.-HAO WANG. "LOW-POWER EIGHT-BIT SCSDL CLA WITH A NOVEL SPLIT-LEVEL CHARGE-SHARING DIFFERENTIAL LOGIC (SCSDL)." Journal of Circuits, Systems and Computers 16, no. 03 (June 2007): 389–402. http://dx.doi.org/10.1142/s0218126607003733.

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A novel logic family, called Split-Level Charge-Sharing Differential Logic (SCSDL), is proposed in this letter. The SCSDL uses the charge recycling technique to reduce power dissipation of differential logic in the precharge phase. The simulation results show that the SCSDL has the best power-delay product compared to several other differential logic families. An eight-bit carry lookahead adder (CLA) designed using the proposed SCSDL can reduce at least 30.64% of power-delay product compared to DCVSL CLA dissipation. A test chip was fabricated to illustrate the feasibility of the SCSDL circuit.

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27

Xue, H., R. Patel, N. V. V. K. Boppana, and S. Ren. "Low‐power‐delay‐product radix‐4 8*8 Booth multiplier in CMOS." Electronics Letters 54, no. 6 (March 2018): 344–46. http://dx.doi.org/10.1049/el.2017.3996.

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28

Neve, A., H. Schettler, T. Ludwig, and D. Flandre. "Power-delay product minimization in high-performance 64-bit carry-select adders." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, no. 3 (March 2004): 235–44. http://dx.doi.org/10.1109/tvlsi.2004.824305.

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29

Aggarwal, S., and K. Khare. "Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic CORDIC Algorithm." Computer Journal 55, no. 5 (October 28, 2011): 616–28. http://dx.doi.org/10.1093/comjnl/bxr109.

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30

CVS, Chaitanya, Sundaresan C, and P. R Venkateswaran. "ASIC design of low power-delay product carry pre-computation based multiplier." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (February 1, 2019): 845. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp845-852.

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High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyam sutra of Vedic Multiplication has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

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31

Panahifar, Ehsan, and Alireza Hassanzadeh. "A Modified Signal Feed-Through Pulsed Flip- Flop for Low Power Applications." International Journal of Electronics and Telecommunications 63, no. 3 (August 28, 2017): 241–46. http://dx.doi.org/10.1515/eletel-2017-0032.

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AbstractIn this paper a modified signal feed-through pulsed flip-flop has been presented for low power applications. Signal feed-through flip-flop uses a pass transistor to feed input data directly to the output. Feed through transistor and feedback signals have been modified for delay, static and dynamic power reduction. HSPICE simulation shows 22% reduction in leakage power and 8% of dynamic power. Delay has been reduced by 14% using TSMC 90nm technology parameters. The proposed pulsed flip-flop has the lowest PDP (Power Delay Product) among other pulsed flip-flops discussed.

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32

Sharma, Anjali, Harsh Sohal, and Harsimran Jit Kaur. "Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design." Journal of Circuits, Systems and Computers 28, no. 12 (November 2019): 1950197. http://dx.doi.org/10.1142/s0218126619501974.

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This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65[Formula: see text]nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the efficiency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65[Formula: see text]nm technology.

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Saini, Jitendra Kumar, Avireni Srinivasulu, and Renu Kumawat. "High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology." International Journal of Sensors, Wireless Communications and Control 9, no. 4 (September 17, 2019): 462–67. http://dx.doi.org/10.2174/2210327909666190206144601.

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Background: The advent of High Performance Computing (HPC) applications and big data applications has made it imparitive to develop hardware that can match the computing demands. In such high performance systems, the high speed multipliers are the most sought after components. A compressor is an important part of the multiplier; it plays a vital role in the performance of multiplier, also it contributes to the efficiency enhancement of an arithmetic circuit. The 5:2 compressor circuit design proposed here improves overall performance and efficiency of the arithmetic circuits in terms of power consumption, delay and power delay product. The proposed 5:2 compressor circuit was implemented using both CMOS and Carbon Nano Tube Field Effect Transistor (CNTFET) technologies and it was observed that the proposed circuit has yielded better results with CNTFETs as compared to MOSFETs. Methods/Results: The proposed 5:2 compressor circuit was designed with CMOS technology simulated at 45 nm with voltage supply 1.0 V and compared it with the existing 5:2 compressor designes to validate the improvements. Thereafter, the proposed design was implemented with CNTFET technology at 32 nm and simulated with voltage supply 0.6 V. The comparision results of proposed 5:2 compressor with existing designs implemented using CMOS. The results also compare the proposed design on CMOS and CNTFET technologies for parameters like power, delay, power delay product. Conclusion: It can be concluded that the proposed 5:2 compressor gives better results as compared to the existing 5:2 compressor designs implemeted using CMOS. The improvement in power, delay and power delay product is approx 30%, 15% and 40% respectively. The proposed circuit of 5:2 compressor is also implemented using CNTFET technology and compared, which further enhances the results by 30% (power consumption and PDP). Hence, the proposed circuit implemented using CNTFET gives substantial improvements over the existing circuits.

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34

Murugeswari, P., A. P. Kabilan, and V. E. Jayanthi. "Effect of Current Mode Signaling in Carbon Nanotube On-Chip Interconnect." Journal of Nano Research 45 (January 2017): 42–48. http://dx.doi.org/10.4028/www.scientific.net/jnanor.45.42.

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A novel signaling technique for on-chip carbon nanotube interconnect aiming a higher bitrate in the range of Terahertz (THz) with low power dissipation, employing the current mode signal transportation is proposed in this paper. The technique exploits the combined advantages of current mode signaling and carbon nanotube. Using the equivalent circuit model, the transfer function is derived for the current mode carbon nanotube interconnect. Current mode signaling through carbon nanotube interconnect is simulated in MATLAB and HSPICE to study its efficiency and performance. The results are compared with the existing voltage mode CNT, current mode copper and optical interconnect. The proposed current mode signaling for carbon nanotube interconnect achieves 102 times lesser power delay product and 90% lesser delay than voltage mode. It exhibits lesser delay, 1000 times in local and 1.2 times in global and lesser power delay product by the factor of 1000 as compared with optical interconnect.

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35

R. Murthy, A. S., and Sridhar T. "Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (April 1, 2018): 27. http://dx.doi.org/10.11591/ijeecs.v10.i1.pp27-36.

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<p>In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and power distribution to multi-core architectures is also posing a challenge to power distribution networks in the integrated circuits. Clock distribution networks for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. Therefore, this paper introduce low swing signaling schemes to decrease delay and power consumption. A comparative study presented of low voltage signaling schemes in terms of delay, power consumption and power delay product. Here, we have presented a power efficient signaling topology for driving the clocks to higher interconnect lengths.</p>

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Nirlakalla, Ravi, Rao Subba, and Talari Jayachandra-Prasad. "Performance evaluation of high speed compressors for high speed multipliers." Serbian Journal of Electrical Engineering 8, no. 3 (2011): 293–306. http://dx.doi.org/10.2298/sjee1103293n.

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This paper describes high speed compressors for high speed parallel multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. These compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2 steps. These compressors are simulated with H-Spice at a temperature of 25?C at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay, Power Delay Product (PDP) and Energy Delay Product (EDP) of the compressors are calculated to analyze the total propagation delay and energy consumption. All the compressors are designed with half adder and full Adders only.

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Rosenbaum, M., W. Sauer-Greff, and R. Urbansky. "Inverse filtering for time, delay and integration X-ray imaging." Advances in Radio Science 9 (July 29, 2011): 135–38. http://dx.doi.org/10.5194/ars-9-135-2011.

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Abstract. In food industry, most finished products are scanned by X-ray for contaminations. These X-ray machines continuously scan the product passing through. To minimize the required X-ray power, a Time, Delay and Integration (TDI) CCD sensor is used to capture the image. While the product moves across the sensor area, the angle of the X-rays changes during the pass. This can be compensated for by adjusting the sensor shift speed to focus on a single plane of the product. If the product has a significant thickness, the image will show artifacts due to the laminographic effect. In this contribution we demonstrate that by the use of inverse filtering images which are focused on planes of different height can be generated out of a single X-ray image.

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Chren, W. A. "PN code generator with low delay-power product for spread-spectrum communication systems." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46, no. 12 (1999): 1506–11. http://dx.doi.org/10.1109/82.809536.

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Ghasemazar, Mohammad, and Massoud Pedram. "Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 10 (October 2011): 1493–506. http://dx.doi.org/10.1109/tcad.2011.2159218.

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Chuang, C. T., J. D. Warnock, and J. D. Cressler. "AC-coupled complementary push-pull ECL circuit with 34 fJ power-delay product." Electronics Letters 29, no. 22 (1993): 1938. http://dx.doi.org/10.1049/el:19931290.

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Cressler, J. D., J. Warnock, D. L. Harame, J. N. Burghartz, K. A. Jenkins, and C. T. Chuang. "A high-speed complementary silicon bipolar technology with 12-fJ power-delay product." IEEE Electron Device Letters 14, no. 11 (November 1993): 523–26. http://dx.doi.org/10.1109/55.258003.

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Arulkarthick, V. J., Rajagopal Thiruvengadam, Chakrapani Arvind, and K. Srihari. "Area and power delay product efficient level restored hybrid full adder (LR-HFA)." Analog Integrated Circuits and Signal Processing 109, no. 1 (May 10, 2021): 165–72. http://dx.doi.org/10.1007/s10470-021-01852-9.

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Wairya, Subodh, Rajendra Kumar Nagaria, and Sudarshan Tiwari. "Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design." VLSI Design 2012 (April 4, 2012): 1–18. http://dx.doi.org/10.1155/2012/173079.

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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 m process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

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Huang, Chun Lei, Lun Yao Wang, Hao Liang, and Yin Shui Xia. "A Design of Three-Input Low-Power AND/XOR Complex Gate." Applied Mechanics and Materials 687-691 (November 2014): 3149–52. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3149.

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For the deficiencies of the existing complex circuit designs, a novel transistor-level three-input AND/XOR logic complex gate with simple and symmetry structure is proposed. HPSICE simulation results show that the proposed circuit has correct operation. Further, in 55nm process CMOS technology, compared with the conventional cell-based cascaded AND/XOR circuit at different operation frequencies, the proposed circuit has a significant improvement at delay, power consumption and power delay product (PDP).

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Chuan, Mu Wen, Kien Liong Wong, Munawar Agus Riyadi, Afiq Hamzah, Shahrizal Rusli, Nurul Ezaila Alias, Cheng Siong Lim, and Michael Loong Peng Tan. "Semi-analytical modelling and evaluation of uniformly doped silicene nanotransistors for digital logic gates." PLOS ONE 16, no. 6 (June 14, 2021): e0253289. http://dx.doi.org/10.1371/journal.pone.0253289.

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Silicene has attracted remarkable attention in the semiconductor research community due to its silicon (Si) nature. It is predicted as one of the most promising candidates for the next generation nanoelectronic devices. In this paper, an efficient non-iterative technique is employed to create the SPICE models for p-type and n-type uniformly doped silicene field-effect transistors (FETs). The current-voltage characteristics show that the proposed silicene FET models exhibit high on-to-off current ratio under ballistic transport. In order to obtain practical digital logic timing diagrams, a parasitic load capacitance, which is dependent on the interconnect length, is attached at the output terminal of the logic circuits. Furthermore, the key circuit performance metrics, including the propagation delay, average power, power-delay product and energy-delay product of the proposed silicene-based logic gates are extracted and benchmarked with published results. The effects of the interconnect length to the propagation delay and average power are also investigated. The results of this work further envisage the uniformly doped silicene as a promising candidate for future nanoelectronic applications.

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Choubey, Abhishek, SPV Subbarao, and Shruti B. Choubey. "Design of delay efficient Booth multiplier using pipelining." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 94. http://dx.doi.org/10.14419/ijet.v7i2.16.11423.

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Multiplication is one of the most an essential arithmetic operation used in numerous applications in digital signal processing and communications. These applications need transformations, convolutions and dot products that involve an enormous amount of multiplications of an operand with a constant. Typical examples include wavelet, digital filters, such as FIR or IIR. However, multiplier structures have relatively large area-delay product, long latency and significantly high power consumption compared to other the arithmetic structure. Therefore, low power multiplier design has been always a significant part of DSP structure for VLSI design. The Booth multiplier is promising as the most efficient amongst the others multiplier as it reduces the complexity of considerably than others. In this paper, we have proposed Booth-multiplier using seamless pipelining. Theoretical comparison results show that the proposed Booth multiplier requires less critical path delay compared to traditional Booth multiplier. ASIC simulation results show proposed radix-16 Booth multiplier 13% less critical path delay for word width n=16 and 17% less critical path delay compared for bit width n=32 to best existing radix-16 Booth multiplier.

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K. Rama Naidu, M. Madhu Babu,. "Area and Power Efficient Fused Floating-point Dot Product Unit based on Radix-2r Multiplier & Pipeline Feedforward-Cutset-Free Carry-Lookahead Adder." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 2 (April 2, 2021): 782–88. http://dx.doi.org/10.17762/itii.v9i2.411.

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Fused floating point operations play a major role in many DSP applications to reduce operational area & power consumption. Radix-2r multiplier (using 7-bit encoder technique) & pipeline feedforward-cutset-free carry-lookahead adder(PFCF-CLA) are used to enhance the traditional FDP unit. Pipeline concept is also infused into system to get the desired pipeline fused floating-point dot product (PFFDP) operations. Synthesis results are obtained using 60nm standard library with 1GHz clock. Power consumption of single & double precision operations are 2.24mW & 3.67mW respectively. The die areas are 27.48 mm2 , 46.72mm2 with an execution time of 1.91 ns , 2.07 ns for a single & double precision operations respectively. Comparison with previous data has also been performed. The area-delay product(ADP) & power-delay product(PDP) of our proposed architecture are 18%,22% & 27%,18% for single and double precision operations respectively.

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Battula, Brahmaiah, Valeti SaiLakshmi, Karpurapu Sunandha, S. Durga Sri Sravya, Putta Vijaya Lakshmi, and S. Navya Sri. "Design a Low Power and High Speed Parity Checker using Exclusive–or Gates." International Journal of Innovative Technology and Exploring Engineering 10, no. 4 (February 28, 2021): 121–25. http://dx.doi.org/10.35940/ijitee.d8522.0210421.

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In the presented paper we designed the parity checker by using EX-OR modules. The two EX-OR modules are presented to design the parity checker and correlated their outcomes based on the constraints like power, area, delay and power delay product (PDP). The previous design is with eight transistors EX-OR, but in the present six transistors EX-OR is used to design the parity checker. While correlating the parity checker design with 8T EX-OR and 6T EX-OR, the 6T EX-OR parity checker design gives optimized power, delay, area and PDP over the 8T EX-OR parity checker design. Simulations are done by using the 130nm mentor graphics tool. Finally the constraints like power, area, delay and PDP gets optimized successfully with the presented technology. Also, alternatively we can replace EXOR modules with NAND modules to design parity checker.

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Jaikumar, R., and P. Poongodi. "Noise measurement in high-speed domino pseudo-CMOS keeper." Measurement and Control 52, no. 1-2 (November 28, 2018): 20–27. http://dx.doi.org/10.1177/0020294018813642.

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Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.

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Cho, Geun Rae, and Tom Chen. "On Mixed PTL/Static Logic for Low-power and High-speed Circuits." VLSI Design 12, no. 3 (January 1, 2001): 399–406. http://dx.doi.org/10.1155/2001/59548.

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We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure that mixes conventional PTL structure with static logic gates can achieve better performance and lower power consumption compared to conventional PTL structure. The goal is to use the static gates to perform both logic functions as well as buffering. Our experimental results demonstrate that the proposed mixed PTL structure beats pure static structure and conventional PTL in 9 out of 15 test cases for either delay or power consumption or both in a 0.25 μm CMOS process. The average delay, power consumption, and power-delay product of the proposed structure for 15 test cases are 10% to 20% better of than the pure static implementations and up to 50% better than the conventional PTL implementations.

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