Dissertations / Theses: 'Power Factor Correction (PFC) boost'

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Grote, Tobias [Verfasser]. "Digital control for interleaved boost power factor correction (PFC) rectifiers / Tobias Grote." Paderborn : Universitätsbibliothek, 2014. http://d-nb.info/105184813X/34.

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Gamboa, Gustavo. "REALIZATION OF POWER FACTOR CORRECTION AND MAXIMUM POWER POINT TRACKING FOR LOW POWER WIND TURBINES." Master's thesis, University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4283.

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In recent years, wind energy technology has become one of the top areas of interest for energy harvesting in the power electronics world. This interest has especially peaked recently due to the increasing demand for a reliable source of renewable energy. In a recent study, the American Wind Energy Association (AWEA) ranked the U.S as the leading competitor in wind energy harvesting followed by Germany and Spain. Although the United States is the leading competitor in this area, no one has been able successfully develop an efficient, low-cost AC/DC convertor for low power turbines to be used by the average American consumer. There has been very little research in low power AC/DC converters for low to medium power wind energy turbines for battery charging applications. Due to the low power coefficient of wind turbines, power converters are required to transfer the maximum available power at the highest efficiency. Power factor correction (PFC) and maximum power point tracking (MPPT) algorithms have been proposed for high power wind turbines. These turbines are out of the price range of what a common household can afford. They also occupy a large amount of space, which is not practical for use in one's home. A low cost AC/DC converter with efficient power transfer is needed in order to promote the use of cheaper low power wind turbines. Only MPPT is implemented in most of these low power wind turbine power converters. The concept of power factor correction with MPPT has not been completely adapted just yet. The research conducted involved analyzing the effect of power factor correction and maximum power point tracking algorithm in AC/DC converters for wind turbine applications. Although maximum power to the load is always desired, most converters only take electrical efficiency into consideration. However, not only the electrical efficiency must be considered, but the mechanical energy as well. If the converter is designed to look like a purely resistive load and not a switched load, a wind turbine is able to supply the maximum power with lower conduction loss at the input side due to high current spikes. Two power converters, VIENNA with buck converter and a Buck-boost converter, were designed and experimentally analyzed. A unique approach of controlling the MPPT algorithm through a conductance G for PFC is proposed and applied in the VIENNA topology. On the other hand, the Buck-boost only operates MPPT. With the same wind profile applied for both converters, an increase in power drawn from the input increased when PFC was used even when the power level was low. Both topologies present their own unique advantages. The main advantage for the VIENNA converter is that PFC allowed more power extraction from the turbine, increasing both electrical and mechanical efficiency. The buck-boost converter, on the other hand, presents a very low component count which decreases the overall cost and volume. Therefore, a small, cost-effective converter that maximizes the power transfer from a small power wind turbine to a DC load, can motivate consumers to utilize the power available from the wind.
M.S.E.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE

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Wang, Chuanyun. "Investigation on Interleaved Boost Converters and Applications." Diss., Virginia Tech, 2009. http://hdl.handle.net/10919/28635.

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With the rapid evolving IT technologies, today, the power factor correction (PFC) design is facing many challenges, such as power scalability, high entire-load-range efficiency, and high power density. Power scalability is a very desirable and cost-effective approach in the PFC design in order to keep up with serversâ growing power requirements. Higher power density can eventually reduce the converter cost and allows for accommodating more equipment in the existing infrastructures. Driven strongly by economic and environmental concerns, high entire-load-range efficiency is more and more required by various organizations and programs, such as the U.S. Energy Star, Climate Savers, and German Blue Angel. Today, the existing boost PFC is reaching its limitations to meet these challenges simultaneously. Using the cutting-edge semiconductor devices, further efficiency improvement at light load is still needed. There are limited approaches available for increasing the power density due to the large EMI filter and inductor size. Interleaved multi-channel boost PFC is a promising candidate to meet those challenges, but the interleaved boost converter is a less explored area. On the other hand, the multi-channel interleaved buck converter for the VR application has been intensively studied and thoroughly explored. One basic approach of this study is trying to extend the existing knowledge and techniques obtained from multiphase buck converters to the multi-channel interleaved boost converters since there are similarities existed between the multi-phase buck and the multi-channel boost converters. The existing studies about the interleaving impact on the EMI filter design are based on the time domain ripple cancellation effect. This approach is good enough for most of the filter designs. However, unlike the conventional filter designs, the EMI filter design is a specification related process. Both the EMI standard and the EMI measurement are based on the frequency domain spectrum. Limited by the existing analysis approaches, it is difficult to provide a clear picture about how exactly the multi-channel interleaving will impact the EMI filter design. The interleaving impact on the Common Mode (CM) noise also has not been studied in any existing literatures for the same reason. In this study, the frequency domain analysis method was adopted. With the double Fourier integral transformation, a closed-form expression of all the harmonics of the noise sources can be obtained. With all the detailed phase relationship of the switching frequency harmonics and all the side band harmonics, the multi-channel interleaving impact on both the differential mode (DM) and CM filter design can be clearly understood and summarized. According to the design curves provided, the EMI filter size can be effectively reduced by properly choosing the interleaving channel number and the switching frequency. The multi-channel interleaving impact on the output capacitor current ripple is also studied and summarized in this dissertation. It should be pointed out that interleaving only reduces the total input and output current ripples; the inductor current in each channel still has large ripple if small inductance is used. Similar to the multi-phase buck converter, coupling inductors result in different equivalent inductances for input current ripple and inductor current ripple for boost converters. Keeping the inductor current ripple magnitude the same, inverse coupling inductors between the interleaved channels can reduce the inductor size. However, the DM filter size is increased due to larger input current. Based on the investigation on the total magnetic component weight, inverse coupling inductor can reduce the total magnetic component weight. The reduction is more pronounced for lower switching frequency design when the inductor size is dominating among the total magnetic components. Based on the harmonic cancellation, and with all the detailed phase relationship of the switching frequency harmonics and all the side band harmonics, a novel phase angle control method is proposed to maximize the reduction of the EMI filter. For example, in a 2-channel interleaved PFC, just by changing the interleaving scheme to 90 degree phase shift, 39% total volume reduction of the EMI filter can be achieved. The proposed phase angle controlled multi-channel PFC is experimentally demonstrated and verified on a digital controlled 4-channel PFC. The phase angle control method proposed in the multi-channel boost converter can be applied back to the multi-phase buck converter as well. The harmonic cancellation principle will be the same as the multi-channel boost converter. The same benefits can be obtained when the requirement is defined in the frequency domain, e.g. the EMI Standard. The interleaved multi-channel configuration makes it possible to implement the phase-shedding to improve the PFC light load efficiency. By decreasing the number of active channels according to the load, the PFC light load efficiency can be optimized. However, shedding phases can reduce the ripple cancellation effect as well, which will result in the EMI noise increase and losing the benefit on the EMI filter. By applying the proposed phase-shedding with phase angle control strategy, the phase shedding impact on the EMI filter design can be minimized. The light load efficiency can be improved without compromising the EMI filter size. Then, adaptive frequency controlled PFC is proposed to further improve the PFC light load efficiency. The proposed light load efficiency improvement strategies are combined and implemented on the platform of the digital controlled 4-channel PFC. The benefit of improving the light load efficiency is experimentally verified. The EMI performance is also evaluated with the EMI measurement results obtained from the PFC prototype. Following the same approach explored, the benefits of interleaved boost converter can be further extended other applications, such as the boost converter in the Hybrid Electric Vehicles (HEV) and photovoltaic (PV) system.
Ph. D.

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Lee, Moonhyun. "Digital-Based Zero-Current Switching (ZCS) Control Schemes for Three-Level Boost Power-Factor Correction (PFC) Converter." Diss., Virginia Tech, 2020. http://hdl.handle.net/10919/99694.

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With the increasing demands on electronic loads (e.g. desktop, laptop, monitor, LED lighting and server) in modern technology-driven lives, performance of switched-mode power supply (SMPS) for electronics have been growing to prominence. As front-end converters in typical SMPS structure, ac-dc power-factor correction (PFC) circuits play a key role in regulations of input power factor, harmonics and dc output voltage, which has a decisive effect on entire power-supply performances. Universal ac-line and low-power system (90–264 Vrms, up to 300–400 W) is one of the most common power-supply specifications and boost-derived PFC topologies have been widely used for the purpose. In order to concurrently achieve high efficiency and low-cost system in the PFC stage, zero-current switching (ZCS) control schemes are highly employed in control principles. Representative schemes are discontinuous conduction mode (DCM) and critical conduction mode (CRM). Both modes can realize ZCS turn-on without diode reverse recovery so that low switching losses and low-cost diode utilizations are obtainable. Among various boost-family PFC topologies, three-level boost (TLB) converter has generated considerable research interest in high-voltage high-power applications. It is mainly due to the fact that the topology can have halved component voltage stresses, improved waveform qualities and electromagnetic interference (EMI) from phase interleaved continuous conduction mode (CCM) operations, compared to other two-level boost PFC converters. On the other hand, in the field of universal-line low-power applications, TLB PFC has been thoroughly out of focus since doubled component counts and increased control complexity than two-level topologies are practical burden for the low-cost systems. However, recent researches on TLB PFC with ZCS control schemes have found that cost-competitiveness of the topology is actually comparable to two-level boost PFC converters because the halved component voltage stresses enable usage of low voltage-rating components of which unit prices are cheaper than higher-rating ones. Based on the justification, researches on ZCS control schemes for TLB PFC have been conducted to get enhanced waveform qualities and performance factors. Following the research stream, a three-level current modulation scheme that can be adopted in both DCM and CRM is proposed in Chapter 2 of this dissertation. Main concept of the proposed current modulation is additional degree-of-freedom in current-slope shaping by differentiating on-times of two active switches, which cannot be found from any other single-phase boost-derived PFC topologies. Using the multilevel feature, proposed operations in one switching period consist of three steps: common-switch on-time, single-switch on-time and common-switch off-time. The single-switch on-time step is key design factor of the proposed modulation that can be utilized either in fixed or adjustable form depending on control purpose. Based on the basic modulation concept, three-level CRM control scheme, adjustable three-level DCM control scheme, and spread-spectrum frequency modulation (SSFM) with adjustable three-level DCM scheme are proposed in Chapter 3–5, respectively. In each chapter, implemented control scheme aims to improve different performance factors. In Chapter 3, the proposed three-level CRM scheme uses increased single-switch on-time period to reduce peak inductor current and magnitude of variable switching frequency. It is generally accepted fact that CRM operations suffer from high switching losses and poor efficiency at light load due to considerable increment of switching frequency. Thus, efficiency improvement effect by the proposed CRM scheme becomes remarkable as load condition goes lighter. In experimental verifications, maximum improvement is measured by 1.2% at light load (20%) and overall efficiency is increased by at least 0.4% all over the load range. In Chapter 4, three-level DCM control scheme adopts adjustable single-switch on-time period in fixed switching-frequency framework. The purpose of adjustable control scheme is to widen the length of non-zero inductor current period as much as possible so that discontinued current period and high peak current of DCM operations can be minimized. Experiment results show that, compared to conventional two-level DCM control, full-load peak inductor currents are reduced by 20.2% and 17.1% at 110 and 220 Vrms input voltage conditions, respectively. Moreover, due to turn-off switching energy decrements by the turn-off current reductions, efficiency is also improved by at least 0.4% regardless of input voltage and load conditions. In Chapter 5, a downward SSFM technique is developed first for DCM operations of boosting PFC converters including two-level topologies. This chapter aims to achieve significant reduction of high differential-mode (DM) EMI amplitudes from DCM operations, which is major drawback of DCM control. By using the simple linearized frequency modulation, peak DM EMI noise at full load condition is reduced by 12.7 dBμV than conventional fixed-frequency DCM control. On top of the proposed SSFM, the adjustable three-level DCM control scheme in Chapter 4 is adopted to get further reductions of EMI noises. Experimental results prove that the collaborations of SSFM and adjustable DCM scheme reduce the EMI amplitudes further by 2.5 dBμV than the result of SSFM itself. The reduced EMI amplitudes are helpful to design input EMI filter with higher cut-off frequency and smaller size. Different from two-level boosting PFC converters, TLB PFC topology has two output capacitors in series and inherently suffers from voltage unbalancing issue, which can be noted as topological trade-off. In Chapter 6, two simple but effective voltage balancing schemes are introduced. The balancing schemes can be easily built into the proposed ZCS control schemes in Chapter 3–5 and experimental results validate the effectiveness of the proposed balancing principles. For all the proposed control schemes in this dissertation, detailed operation principles, derivation process of key equations, comparative analyses, implementation method with digital controller and experimental verifications with TLB PFC prototype are provided.
Doctor of Philosophy
Electronic-based devices and loads have been essential parts of modern society founded on rapid advancements of information technologies. Along with the progress, power supplying and charging of electronic products become routinized in daily lives, but still remain critical requisites for reliable operations. In many power-electronics-based supplying systems, ac-dc power-factor correction (PFC) circuits are generally located at front-end to feed back-end loads from universal ac-line sources. Since PFC stages have a key role in regulating ac-side current quality and dc-side voltage control, the importance of PFC performances cannot be emphasized enough from entire system point of view. Thus, advanced control schemes for PFC converters have been developed in quantity to achieve efficient operations and competent power qualities such as high power factor, low harmonic distortions and low electromagnetic interferences (EMI) noises. In this dissertation, a sort of PFC topologies named three-level boost (TLB) converter is chosen for target topology. Based on inherent three-level waveform capability of the topology, multiple zero-current switching (ZCS) control schemes are proposed. Compared to many conventional two-level PFC topologies, TLB PFC can provide additional degree-of-freedom to current modulation. The increased control flexibility can realize improvements of various waveform qualities including peak current stress, switching frequency range, harmonics and EMI amplitude. From the experimental results in this dissertation, improvements of waveform qualities in TLB PFC with the proposed schemes are verified with comparison to two-level current control schemes; in terms of efficiency, the results show that TLB PFC with the proposed schemes can have similar converter efficiency with conventional two-level boost converter in spite of increased component counts in the topology. Further, the proposed three-level control schemes can be utilized in adjustable forms to accomplish different control objectives depending on system characteristics and applications. In each chapter of this dissertation, a novel control scheme is proposed and explained with details of operation principle, key equations and digital implementation method. All the effectiveness of proposals and analyses are validated by a proper set of experimental results with a TLB PFC prototype.

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Damasceno, Daniel da Motta Souto. "Metodologia de projeto de conversores boost para correção de fator de potência apliocada a sistemas ininterruptos de energia." Universidade Federal de Santa Maria, 2006. http://repositorio.ufsm.br/handle/1/8539.

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This Master Thesis presents a design methodology to a boost PFC converter operating as an Uninterruptible Power Supply rectifier input stage. This methodology defines, making use of a group of current ripples and switching frequencies, the converter minimum volume point analyzing the volumes of the boost inductor, the electromagnetic interference filter and the heat-sinks. Thus, it's developed along this work, each design mentioned above, analyzing the impact of different magnetic materiaIs, input filter topologies and semiconductors technologies. Previously, it is designed the controller and it is developed a simulation structure. ln a second moment, it's designed the boost inductor for a predetermined temperature elevation. After this, it's designed the electromagnetic filter analyzing the impact of different topologies. The heat-sinks are also designed to guarantee the semiconductors operation within the temperature limits. Finally, the methodology based on the previous designs is accomplished, using the procedures and equations already mentioned, becoming possible to define the converter minimum volume point.
Esta Dissertação de Mestrado apresenta uma metodologia de projeto para o conversor boost operando como estágio retificador de entrada em uma fonte de alimentação ininterrupta. Essa metodologia se baseia em definir, através de um conjunto de freqüências de comutação e ondulações de corrente, o ponto de minimização do volume do conversor considerando o volume do indutor, do filtro de interferência eletromagnética conduzida e dos dissipadores. Assim, é desenvolvido ao longo desse trabalho o projeto de cada elemento mencionado estudando o impacto do uso de diferentes materiais magnéticos, topologias de filtro de entrada e tecnologias de semicondutores. Inicialmente é projetado o controlador e desenvolvida a estrutura de simulação do conversor. Em um segundo momento é projetado o indutor boost para uma determinada elevação de temperatura. A seguir é projetado o filtro de interferência eletromagnética analisando o impacto de diferentes topologias. Também são projetados os dissipadores que garantem a operação dos semicondutores dentro dos limites de temperatura estabelecidos pelos fabricantes. Por fim, é formalizada a metodologia baseada nos projetos anteriores, pela qual, fazendo uso dos procedimentos e equações fornecidos, torna-se possível definir o ponto de minimização do volume do conversor.

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JÃnior, JosÃ Ailton LeÃo Barboza. "A Double boost converter with PFC and series/parallel input connection for uninterrupted power system." Universidade Federal do CearÃ, 2012. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=16257.

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fator de potÃncia e recurso para operar com dois valores de tensÃo de entrada. O mesmo Ã aplicÃvel a sistemas ininterruptos de energia do tipo dupla conversÃo ou on-line com caracterÃsticas de tensÃo de entrada bivolt (110 Vca e 220 Vca) e desta maneira Ã descartada a utilizaÃÃo de um autotransformador com seletor de tensÃo. O conversor em estudo Ã composto por dois conversores CA-CC boost clÃssicos, em que, para uma tensÃo de entrada de 110 Vca as entradas sÃo conectadas em paralelo e para uma tensÃo de entrada de 220 Vca as entradas sÃo conectadas em sÃrie. A ideia Ã fazer com que se tenha uma divisÃo equilibrada na entrada de cada conversor quando a tensÃo da rede elÃtrica for 220 Vca. Assim cada conversor boost clÃssico recebe metade da tensÃo total de alimentaÃÃo do conversor proposto. A estratÃgia de controle Ã baseada no controle por modo corrente mÃdia aplicada a ambos os conversores para proporcionar a correÃÃo do fator de potÃncia e a regulaÃÃo da tensÃo de saÃda. Para verificar o estudo teÃrico foi desenvolvido o projeto do circuito de potÃncia e controle validando atravÃs de resultados de simulaÃÃo e experimentais para um protÃtipo de 2,4 kW. Para a conexÃo paralelo e sÃrie das entradas, os resultados obtidos foram satisfatÃrios e o conversor operou adequadamente.
This work presents a study of a Double Boost AC-DC Converter with power factor correction and dual input voltage operation capability via a selector switch. Such converter can be applied to on-line uninterruptible power supplies with dual voltage input characteristics, this way avoiding the usage of a low frequency autotransformer. The studied structure is composed by two AC-DC classical boost converters, in which for input voltage of 110 Vac both its inputs are connected in parallel, and, for 220 Vac, they are connected in series. The control strategy is based in the average current mode control applied to both converters, in order to provide the power factor correction and output voltage regulation. Simulation and experimental results for 2.4 kW are presented, and so are validate the theoretical study and design. Connecting the inputs in parallel and series, the results were satisfactory and the converter operated properly.

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Zientarski, Jonatan Rafael Rakoski. "Análise, modelagem e validação experimental de uma metodologia para o projeto do indutor em conversores Boost PFC." Universidade Federal de Santa Maria, 2009. http://repositorio.ufsm.br/handle/1/8464.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
This work presents the development of a methodology for design of inductor in singlephase PFC boost converters operating in CCM mode in agreement with international standards IEC 61000-3-2 and CISPR 22. Such converters are used in front-end modules of information technology equipment. This methodology is based on the investigation of the relationship among magnetic volume; switching frequency and input current ripple of the converter, presented in previous work and extended to allow the optimization of inductors with three magnetic materials: Kool Mμ, Molypermalloy and High-Flux. An analysis of some constructive characteristics of the inductors is performed, such as, magnetic materials and most appropriate type of winding, taking into account factors that can determine the lowest volume of the inductor, such as winding and magnetic losses, the flux density, and conducted electromagnetic interference (EMI). In construction of the inductors, it is discussed the use of single-layer winding, presenting their main haracteristics, advantages when seeking the reduction of conducted EMI, and considering the disadvantage of increasing of volume that this type winding may cause. An algorithm for this methodology is developed, that uses models able to estimate the differential mode conducted EMI for frequencies up to 30 MHz, as well the temperature rise of boost inductor by simulating the input current of the converter, considering soft saturation characteristics of magnetic materials and the use of commercial cores. Additionally, it is performed an experimental validation of the developed algorithm by construction of prototypes that uses three selected materials and operate at three different points of operation.
Este trabalho apresenta o desenvolvimento de uma metodologia de projeto do indutor em conversores boost PFC CCM monofásicos de acordo com as normas internacionais IEC 61000-3-2 e CISPR 22. Tais conversores são utilizados como estágio de entrada em fontes de equipamentos da tecnologia da informação. A metodologia é baseada na investigação da dependência existente entre o volume dos elementos magnéticos com a freqüência de comutação e a ondulação da corrente de entrada nestes conversores. O trabalho dá continuidade a trabalhos anteriores, ampliando a análise para a otimização de indutores de três materiais magnéticos: Kool Mμ, Molypermalloy e High-Flux. É realizada uma análise de algumas características construtivas destes indutores, entre elas, os materiais magnéticos mais apropriados e o tipo de enrolamento utilizado levando-se em consideração fatores que permitem a redução do volume do indutor, como as perdas magnéticas e nos enrolamentos, a densidade de fluxo magnético e a interferência eletromagnética (EMI) conduzida. Na implementação dos indutores, é discutida a utilização de enrolamentos de única camada, apresentando suas principais características, as vantagens de sua utilização quando se busca a redução da EMI conduzida, e considerando-se a desvantagem do aumento de volume do indutor que este tipo de enrolamento pode causar. Um algoritmo é desenvolvido para esta metodologia, no qual são utilizados modelos capazes de estimar a EMI conduzida DM para freqüências de até 30 MHz, assim como a elevação da temperatura do indutor, por meio de uma simulação da corrente de entrada do conversor que considera os efeitos da saturação suave dos materiais magnéticos e a utilização de núcleos com dimensões comerciais. É também realizada a validação experimental deste algoritmo, por meio da construção de protótipos que utilizam indutores dos três materiais escolhidos e operam em três pontos de operação distintos.

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Hertz, Erik M. "Thermal and EMI Modeling and Analysis of a Boost PFC Circuit Designed Using a Genetic-based Optimization Algorithm." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/34234.

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The boost power factor correction (PFC) circuit is a common circuit in power electronics. Through years of experience, many designers have optimized the design of these circuits for particular applications. In this study, a new design procedure is presented that guarantees optimal results for any application. The algorithm used incorporates the principles of evolution in order to find the best design. This new design technique requires a rethinking of the traditional design process. Electrical models have been developed specifically for use with the optimization tool. One of the main focuses of this work is the implementation and verification of computationally efficient thermal and electro-magnetic interference (EMI) models for the boost PFC circuit. The EMI model presented can accurately predict noise levels into the 100's of kilohertz range. The thermal models presented provide very fast predictions and they have been adjusted to account for different thermal flows within the layout. This tuning procedure results in thermal predictions within 10% of actual measurement data. In order to further reduce the amount of analysis that the optimization tool must perform, some of the converter design has been performed using traditional methods. This part of the design is discussed in detail. Additionally, a per unit analysis of EMI and thermal levels is introduced. This new analysis method allows EMI and thermal levels to be compared on the same scale thus highlighting the tradeoffs between the both behaviors.
Master of Science

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Pham, Thi Thuy Linh. "Contribution à l’étude de nouveaux convertisseurs sécurisés à tolérance de panne pour systèmes critiques à haute performance. Application à un PFC Double- Boost 5 Niveaux." Thesis, Toulouse, INPT, 2011. http://www.theses.fr/2011INPT0095/document.

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Les conditionneurs alternatifs – continu à absorption sinusoïdale (PFC) pour les applications critiques se distinguent par un haut niveau de performances tel que les THD réduits, un haut rendement et une bonne fiabilité. Leur importance est d’autant plus nécessaire qu’une continuité de service des alimentations est requise même en présence d’une défaillance interne de composant. Deux types de structures associées à leur commande sont réalisés à cet effet, les structures à redondance parallèle et les structure à redondance en série. Elles consistent respectivement en l’ajout d’un bras d’interrupteur dans le cas de la redondance parallèle, qui est une option plus compliquée et en une suppression d’une cellule de commutation dans le deuxième cas. L’étude présentée ici, consiste en premier lieu en une exploration et une évaluation de nouvelles familles de topologies multi-niveaux, caractérisée par un partitionnement cellulaire en série. Ces nouvelles topologies, ainsi que leurs variantes, comportent au moins une redondance structurelle avec des cellules mono-transistor à défaut de commande non critique et symétriques à point-milieu. Elles sont donc génériques pour la mise en parallèle et l’extension en triphasé. Cependant, elles sont pour la plupart peu compétitives à cause des composants qui sont souvent surdimensionnés et donc plus onéreuses, en comparaison avec la structure PFC Double-Boost 5 Niveaux à composants standards 600 V (brevetée par l’INPT – LAPLACE –CNRS en 2008) que nous étudions. Cette dernière constitue le meilleur compromis entre un bon rendement et une maîtrise des contraintes en mode dégradé. Sur le plan théorique nous montrons que le seul calcul de fiabilité basé uniquement sur un critère de premier défaut est inadapté pour décrire ce type de topologie. La prise en compte de la tolérance de panne est nécessaire et permet d'évaluer la fiabilité globale sur une panne effective (i.e. au second défaut). L'adaptation de modèles théoriques de fiabilité à taux de défaillance constant mais prenant en compte, au niveau de leurs paramètres, le report de contrainte en tension et l'augmentation de température qui résulte d'un premier défaut, permet de chiffrer en valeur relative, le gain obtenu sur un temps court. Ce résultat est compatible avec les systèmes embarqués et la maintenance conditionnelle. Un prototype monophasé de PFC double-boost 5 niveaux à commande entièrement numérique et à MLI optimisée reconfigurable en temps réelle a été réalisé afin de valider l’étude. Il permet une adaptation automatique de la topologie de 5 à 4 puis 3 niveaux par exemple. Ce prototype a également servi de test d'endurance aux transistors CoolMos et diodes SiC volontairement détruits dans des conditions d'énergie maîtrisée et reproductibles. D’autres campagnes d'endurance en modes dégradés ont été réalisées en laboratoire sur plusieurs centaines d’heures en utilisant ce même prototype. Nous nous sommes axés sur la détection de défauts internes et le diagnostic (localisation) rapide, d'une part par la surveillance directe et le seuillage des tensions internes (tensions flottantes) et d'autre part, par la détection d’harmoniques (amplitude et phase) en temps réel. Ces deux techniques ont été intégrées numériquement et évaluées sur le prototype, en particulier la seconde qui ne requiert qu'un seul capteur. Enfin, nous proposons une nouvelle variante PFC expérimentée en fin de mémoire, utilisant deux fois moins de transistors et de drivers pour les mêmes performances fréquentielles au prix d'un rendement et d'une répartition des pertes légèrement moins favorable que la structure brevetée
This work is an exploration and an evaluation of new variants of multi-level AC/DC topologies (PFC) considering their global reliability and availability: electrical safety with an internal failure and post-failure operation. They are based on a non-differential AC and centre tap connection that led to symmetrical arrangement cells in series. These topologies permit an intrinsic active redundancy between cells in a same group and a segregation capability between the two symmetrical groups of cells. More again, they are modular and they can be paralleled and derived to any number of levels. Only single low-voltage (600V) transistor pear cell is used avoiding the short-circuit risk due to an unwanted control signal. Comparisons, taking into account losses, distribution losses, rating and stresses (overvoltage and over-temperature) during the post-operation are presented. Results highlight the proposed 5-level Double-Boost Flying Capacitor topology. This one was patented at the beginning of thesis, as a solution with the best compromise. On the theoretical side, we show that the reliability calculation based only on a "first fault occurrence" criterion is inadequate to really describe this type of topology. The inclusion of fault tolerance capability is needed to evaluate the overall reliability law (i.e. including a second failure). The adaptation of theoretical models with constant failure rate including overvoltage and over-temperature dependencies exhibit an increasing of the reliability over a short time. This property is an advantage for embedded systems with monitoring condition. Local detection and rapid diagnosis of an internal failure were also examined in this work. Two methods are proposed firstly, by a direct flying caps monitoring and secondly, by a realtime and digital synchronous demodulation of the input sampled voltage at the switching frequency (magnitude and phase). Both techniques have been integrated on FPGA and DSP frame and evaluated on a AC230V-7kW DC800V – 31kHz lab. set-up. We put forward the interest of the second method which only uses one input voltage sensor. Finally, we propose in this dissertation a new generic X-level PFC Vienna using, in 5-level version, half transistors and drivers for identical input frequency and levels. At the cost of a slight increase of losses and density losses, this topology appears very attractive for the future. A preliminary lab. set-up and test were also realized and presented at the end of the thesis

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10

Pham, Thi Thuy Linh. "Contribution à l'étude de nouveaux convertisseurs sécurisés à tolérance de panne pour systèmes critiques à haute performance. Application à un PFC Double- Boost 5 Niveaux." Phd thesis, Institut National Polytechnique de Toulouse - INPT, 2011. http://tel.archives-ouvertes.fr/tel-00656620.

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Ce travail vise une exploration et une évaluation de nouvelles variantes de topologies multiniveaux AC/DC non réversibles (PFC) du point de vue de leur sûreté de fonctionnement : recherche d'une grande sécurité électrique sur destruction interne et maintien d'une continuité de fonctionnement. Elles sont caractérisées par une connexion AC non différentielle, un partitionnement cellulaire en série et symétrique autour d'un point milieu. Cette organisation permet d'exploiter la redondance active série entre les cellules d'un même groupe et l'effet de ségrégation topologique qui apparaît entre les deux groupes de cellules. Les structures étudiées sont modulaires et peuvent être parallélisées et étendues à un nombre quelconque de phases. Elles ne possèdent que des cellules mono-transistors basse-tension (Si et SiC 600V max) performantes et intrinsèquement tolérantes aux imperfections de la commande et aux parasites donc naturellement sécurisées. Les comparaisons prenant en compte les pertes, la répartition des pertes, le dimensionnement et le report de contraintes sur défaut interne mettent en avant la structure PFC Double- Boost Flying Cap. à 5 Niveaux, brevetée en début de thèse, comme une solution ayant le meilleur compromis. Sur le plan théorique nous montrons que le seul calcul de la fiabilité basé uniquement sur un critère d'occurrence au premier défaut est inadapté pour décrire ce type de topologie. La prise en compte de la tolérance de panne est nécessaire et permet d'évaluer la fiabilité globalement sur une panne effective (i.e. au second défaut). L'adaptation de modèles théoriques de fiabilité à taux de défaillance constant mais prenant en compte, au niveau de leurs paramètres, le report de contrainte en tension et l'augmentation de température qui résulte d'un premier défaut, permet de chiffrer par intégration et en valeur relative, le gain obtenu sur un temps court. Ce résultat est compatible avec les systèmes embarqués et la maintenance conditionnelle. Un prototype monophasé à 5 niveaux, à commande entièrement numérique et à MLI optimisée reconfigurable en temps réel a été réalisé afin de valider l'étude. Il permet une adaptation automatique de la topologie de 5 à 4 puis à 3 niveaux par exemple. Ce prototype a également servi de banc de test d'endurance du mode de défaillance sur claquage - avalanche de transistors CoolMos™ et diodes SiC, volontairement détruits individuellement dans des conditions d'énergie maîtrisée et reproductibles, afin de prouver expérimentalement le maintien du service sur plusieurs centaines d'heures au prix d'un derating de 30% maximum en puissance seulement. La détection et le diagnostic rapide de défauts internes ont également été traités dans ce travail. D'une part, par la surveillance directe et le seuillage des tensions internes (tensions flottantes) et d'autre part, par une détection harmonique de la fréquence de base (amplitude et phase) en temps réel. Ces deux techniques ont été intégrées numériquement et évaluées sur le prototype, en particulier la seconde qui ne requiert qu'un seul capteur. VI Enfin, nous proposons dans ce travail une nouvelle variante PFC Vienna multicellulaire expérimentée en fin de mémoire, utilisant deux fois moins de transistors et de drivers pour les mêmes performances fréquentielles au prix d'un rendement et d'une répartition des pertes légèrement moins favorables que la structure brevetée.

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11

Baisden, Andrew Carson. "Modeling and Characterization of Power Electronic Converters with an Integrated Transmission-Line Filter." Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/33188.

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In this work, a modeling approach is delineated and described in detail; predominantly done in the time domain from low frequency, DC, to high frequencies, 100 MHz. Commercially available computer aided design tools will be used to determine the propagation path in a given structure. Next, an integrated transmission-line filter â fabricated using planar processing technologies â is modeled to accurately predict the EMI characteristics of the system. A method was derived to model the filterâ s performance in the time-domain while accurately depicting the highly frequency dependant transmission-line properties. A system model of a power factor correction (PFC) boost converter was completed by using active device models for diodes, MOSFETs, and the gate driver. In addition, equivalent circuits were used to characterize high frequency impedances of the passive components. A PFC boost converter was built and used to validate the model. The PFC operated at a peak output power of 1 kW, switching at 400 kHz, with a universal input ranging from 90-270 VRMS with unity power factor. The time-domain and EMI frequency spectrum waveforms are experimentally measured and agree very well with the simulated values; within 5 dB for EMI. The transmission-line filter was also manufactured for model verification, and it is tested for the first time with an operating converter: a PFC at 50 W output and 50 VDC input. The small signal characteristics match the model very well. In addition, impedance interactions between the filter, the converter, and the EMI measurement set-up are discussed, evaluated, measured, and improved to minimize undesired resonances and increase low-frequency EMI attenuation. Experimentally measured attenuation provided by the filter in the range from 100 kHz to 100 MHz was 20-50 dBμV. The simulation also shows a similar attenuation, with the exception of one key resonance not seen in the simulation.
Master of Science

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12

Williams, David. "Active power decoupling for a boost power factor correction circuit." Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/59145.

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During AC-DC conversion, the ripple power at the input of the converter must be filtered from the output. This filtering can be easily done by placing a capacitor on the DC bus. For systems with power output of hundreds of Watts or more, this capacitor must be quite high to effectively perform the filtering, and in order to be cost effective, an aluminum electrolytic capacitor (Al e-caps) needs to be used. The lifespan of Al e-caps is notoriously short, so for long lifespan systems, their use is not advisable. Film capacitors have longer lifespans than Al e-caps but are more expensive on a cost per Farad basis. Methods have been proposed to reduce the required capacitance so that film capacitors can be cost effectively used. One of these methods is to use a separate decoupling port in the circuit that can filter the ripple power without the limitation of being connected directly to the DC bus. The first contribution is a method of using an active power decoupling (APD) port with a buck-based circuit that does not require direct measurement of the AC input signal for controlling the ripple power to the port. This APD port requires only two extra switches and some simple signal processing circuitry to generate a reference signal and control the voltage to the APD port capacitor. The second contribution is a design guide for a sliding mode control (SMC) system for the APD port. SMC shows promise as a control system for power electronics circuits and has never been demonstrated on an APD port before. The proposed circuit and control system is used in a 700 Watt AC-DC converter with power factor correction and is compared in simulation to a benchmark converter using a passive capacitor on the DC bus. The capacitance is reduced from 300μF to a 35μF and a 75μF capacitor without any effect on performance as indicated by measures of the voltage ripple, power factor and total harmonic distortion. The capacitance reduction results in a cost savings of $175 on capacitors when using prices that were current at time of publication.
Applied Science, Faculty of
Engineering, School of (Okanagan)
Graduate

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13

George, Mark S. "Power factor correction using a boost quasi-resonant converter." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41901.

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A steady-state analysis of a quasi-resonant zero current boost converter is performed in its application to a single-phase power factor correction circuit. The known closed-form expressions are used to design the boost converter and the multiloop control circuit. The operating characteristics are simulated by using PSPICE and are experimentally verified. Considerations for a practical design are based upon hardware operating at a maximum of 1 megahertz, with a 115 VRMS input, 200 VDC and 100 watt output.

Master of Science

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14

Xie, Manjing. "Digital Control for Power Factor Correction." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34258.

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This thesis focuses on the study, implementation and improvement of a digital controller for a power factor correction (PFC) converter. The development of the telecommunications industry and the Internet demands reliable, cost-effective and intelligent power. Nowadays, the telecommunication power systems have output current of up to several kilo amperes, consisting of tens of modules. The high-end server system, which holds over 100 CPUs, consumes tens of kilowatts of power. For mission-critical applications, communication between modules and system controllers is critical for reliability. Information about temperature, current, and the total harmonic distortion (THD) of each module will enable the availability of functions such as dynamic temperature control, fault diagnosis and removal, and adaptive control, and will enhance functions such as current sharing and fault protection. The dominance of analog control at the modular level limits system-module communications. Digital control is well recognized for its communication ability. Digital control will provide the solution to system-module communication for the DC power supply. The PFC converter is an important stage for the distributed power system (DPS). Its controller is among the most complex with its three-loop structure and multiplier/divider. This thesis studies the design method, implementation and cost effectiveness of digital control for both a PFC converter and for an advanced PFC converter. Also discussed is the influence of digital delay on PFC performance. A cost-effective solution that achieves good performance is provided. The effectiveness of the solution is verified by simulation. The three level PFC with range switch is well recognized for its high efficiency. The range switch changes the circuit topology according to the input voltage level. Research literature has discussed the optimal control for both range-switch-off and range-switch-on topologies. Realizing optimal analog control requires a complex structure. Until now optimal control for the three-level PFC with analog control has not been achieved. Another disadvantage of the three-level PFC is the output capacitor voltage imbalance. This thesis proposes an active balancing solution to solve this problem.
Master of Science

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15

Marzouk, Mounir. "Développement de chargeurs intégrés pour véhicules hybrides plug-in." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT088/document.

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Ces travaux de thèse consistent en la conception et la réalisation d’une chaîne de tractionintégrée pour véhicule hybride plug-in. L’étude s’oriente vers une solution de convertisseur mutualisé,dans l’objectif de partager la traction et les modes chargeurs de batteries, la structure en NPC à 3niveaux est retenue. Le chargeur monophasé se base une topologie de redresseur à MLI monophaséavec trois bras entrelacés, avec l’utilisation des enroulements du moteur pour le filtrage. En chargeurtriphasé nous adaptons la topologie pour réaliser un montage en double boost triphasé. Pour chaqueconfiguration, les passifs sont dimensionnés pour répondre aux contraintes en courant BF et HF. Lecontrôle adopté se base sur les correcteurs résonants. Enfin, un prototype de 5 kW a été réalisé pourvalider les différents modes de l’application.Dans une seconde partie, nous proposons une solution de chargeur isolé sans étage continu auprimaire à double ponts actifs (DAB). La topologie est modélisée au premier harmonique et unecommande assurant l’absorption sinusoïdale est étudiée. Une configuration isolée triphasée permetl’accès aux puissances plus élevées ainsi que la réduction des ondulations de courant BF en sortie
This thesis consists on the design and realization of a plug-in hybrid vehicle integrated tractiondrive supply. The work turns to a solution of a mutualized converter, in the objective to imagine asolution which shared drive and battery chargers modes, the three-level NPC topology has beenretained. The single phase charger is based on an interleaved PWM rectifier, and motor windings areused as smoothing inductors. A double-boost PFC configuration is introduced to ensure the threephasecharger. Passives are sized in each configuration in order to take in account the whole currentconstraints (LF and HF). The PFC behavior is based on the resonant controllers. Then, a 5 kWprototype has been realized to validate the different application modes.In a second part, a single-stage isolated charger based on a Dual-Active-Bridge (DAB) isproposed. The topology is modeled to the fundamental and the PFC control law is studied. A threephaseconfiguration is simulated in order to achieve higher charging powers and to reduce batterycurrent low-frequency ripple

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16

Tan, Benjamin H. "A Novel Arc Welding Power Supply with Improved Power Factor Correction." DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2199.

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This paper presents the design and development of a novel Arc Welding Power Supply utilizing a modified two-switch forward converter topology. The proposed design improves the power quality by improving power factor to near unity and reducing total harmonic distortion. State space analysis of the proposed circuit showed that the circuit followed a boost-buck input output relationship. Simulation of the circuit was first implemented in LTspice to verify the functionality of the new topology. Hardware implementation of the proposed design was built on a scaled-down prototype for a proof-of-concept of the new topology. The prototype specifications were created for a 5A, 20V output with a 20-24V, 60Hz input. This project demonstrated that the proposed new topology was successful in obtaining a near unity power factor and a total harmonic distortion of less than 2%. Additionally, the prototype followed the simulation and calculations of a boost-buck function while varying duty cycle, and the final measurements aligned well with waveforms from the simulation.

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17

Busquets-Monge, Sergio. "Application of Optimization Techniques to the Design of a Boost Power Factor Correction Converter." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/34156.

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This thesis analyzes the procedural approach and benefits of applying optimization techniques to the design of a boost power factor correction (PFC) converter with an input electromagnetic interference (EMI) filter at the component level. The analysis is performed based on the particular minimum cost design study of a 1.15 kW unit satisfying a set of specifications. A traditional design methodology is initially analyzed and employed to obtain a first design. A continuous design optimization is then formulated and solved to gain insight into the converter design tradeoffs and particularities. Finally, a discrete optimization approach using a genetic algorithm is defined to develop a completely automated user-friendly software design tool able to provide in a short period of time globally optimum designs of the system for different sets of specifications. The software design tool is then employed to optimize the system design, and the savings with respect to the traditional design methodology are highlighted. The optimization problem formulation in both the continuous and discrete cases is presented in detail. The system design variables, objective function (system component cost) and constraints are identified. The objective function is expressed as a function of the design variables. A computationally efficient and experimentally validated model of the system, including second-order effects, allows the constraint values (also as a function of the design variables) to be obtained.
Master of Science

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18

Huang, Qihong. "Harmonic Reduction IN a Single-Switch Three-Phase Boost Rectifier With Harmonic-Injected PWM." Thesis, Virginia Tech, 1997. http://hdl.handle.net/10919/36538.

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A constant switching frequency with the sixth-order harmonic injection PWM concept is established, and a sixth-order harmonic injection technique is developed for the harmonic reduction of a single-switch three-phase boost rectifier. The approach employs a constant duty cycle with sixth-order harmonic injection to suppress the dominant (fifth-order) harmonic in the input currents. Hence, to meet the THD<10% requirement, the rectifier voltage gain can be designed down to 1.45; to meet the IEC 1000-3-2 (A) standard, the output power can be pushed up to 10 kW for the application with a 3X220 V input and a 800 V output. The results are verified on a 6-kW prototype. The injection principle is graphically explained in current waveforms and mathematically proved. Two injection methods are proposed to meet either the THD requirement or the IEC standard. The injection implementation and design guidelines are provided. The boost inductor design and EMI filter design are discussed. An average small- signal model based on the equivalent multi-module model is developed and experimentally verified. The variations of the small-signal model against load are demonstrated, and the compensator design is discussed. The results show that at no load, the dominant pole of the control-to-output transfer function approaches the origin and causes more phase delay, making the control design difficult. To avoid the no load case and to simplify the control design, a 50-W dummy load (1% of the full load) is added. Finally, a simple nonlinear gain control circuit is presented to mitigate the load effect and reduce the dummy load to 10 W.
Master of Science

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19

Louganski, Konstantin. "Generalized Average-Current-Mode Control of Single-Phase AC-DC Boost Converters with Power Factor Correction." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/27331.

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The dissertation presents a generalized average-current-mode control technique (GACMC), which is an extension of the average-current-mode control (ACMC) for single-phase ac-dc boost converters with power factor correction (PFC). Traditional ACMC is generalized in a sense that it offers improved performance in the form of significant reduction of the current control loop bandwidth requirement for a given line frequency in unidirectional and bidirectional boost PFC converters, and additional functionality in the form of reactive power control capability in bidirectional converters. These features allow using a relatively low switching frequency and slow-switching power devices such as insulated-gate bipolar transistors (IGBTs) in boost PFC converters, including those designed for higher ac line frequencies such as in aircraft power systems (360â 800 Hz). In bidirectional boost PFC converters, including multilevel topologies, the GACMC offers a capability to supply a prescribed amount of reactive power (with leading or lagging current) independently of the dc load power, which allows the converter to be used as a static reactive power compensator in the power system.

A closed-loop dynamic model for the current control loop of the boost PFC converter with the ACMC has been developed. The model explains the structure of the converter input admittance, the current phase lead phenomenon, and lays the groundwork for development of the GACMC. The leading phase admittance cancellation (LPAC) principle has been proposed to completely eliminate the current phase lead phenomenon and, consequently, the zero-crossing distortion in unidirectional converters. The LPAC technique has been adapted for active compensation of the input filter capacitor current in bidirectional boost PFC converters.

The dynamic model of the current control loop for bidirectional boost PFC converters was augmented to include a reactive power controller. The proposed control strategy enables the converter to process reactive power and, thus, be used as a reactive power compensator, independently of the converter operation as an ac-dc converter.

Multiple realizations of the reactive power controller have been identified and examined in a systematic way, along with their merits and limitations, including susceptibility to the ac line noise. Frequency response characteristics of reactive elements emulated by means of these realizations have been described.

Theoretical principles and practical solutions developed in this dissertation have been experimentally verified using unidirectional and bidirectional converter prototypes. Experimental results demonstrated validity of the theory and proposed practical implementations of the GACMC.
Ph. D.

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20

Liu, Ziyong. "Design of Single Phase Boost Power Factor Correction Circuit and Controller Applied in Electric Vehicle Charging System." Digital WPI, 2016. https://digitalcommons.wpi.edu/etd-theses/1243.

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"In this thesis, based on the existing researches on power factor correction technology, I analyze, design and study the Boost type power factor correction technology, which is applied in the in-board two-stage battery charger. First I analyzed the basic working principle of the active power factor corrector. By comparing several different topologies of PFC converter main circuit and control methods, I specified the research object to be the average current control (ACM) boost power factor corrector. Then I calculated and designed the PFC circuit and the ACM controller applied in the first level charging of EVs. And I run the design in Simulink and study the important features like power factor, the input current waveform and the output DC voltage and the THD and odd harmonic magnitude."

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21

Koh, Hyunsoo. "Modeling and Control of Single Switch Bridgeless SEPIC PFC Converter." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/34125.

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Due to increasing concerns on the power quality, power factor correction (PFC) has become an important issue in light-emitting diode (LED) lighting applications. A boost converter is one of the most well-known PFC topologies, due to its simple circuitry, simple control scheme and small number of passive components. Even though a boost converter is recognized as a typical PFC converter, its output voltage must be higher than its input voltage. This feature is disadvantageous because the device requires an additional buck-stage for LED lighting systems. As an alternative to the boost converter, a single-ended primary-inductor converter (SEPIC) allows output voltage to be lower or higher than the input voltage. Thus, the SEPIC converter is gaining popularity as a LED driver because it does not require additional power conversion stage. However, designing a controller to meet stability requirements and international standards is quite challenging for SEPIC converters. Additionally, if the digital controller is adopted for its built-in communication features, creating a digitally controlled SEPIC converter would be even more challenging. This thesis focuses on the state-space averaging modeling of the SEPIC PFC converter and the design of controllers based on both analog and digital controls with precise modeling. The proposed SEPIC converter incorporates RC damping circuits to avoid the instability, and thus the entire SEPIC converter becomes a 5th order system. Such a high-order system model was derived mathematically and verified with circuit simulator modeling. After verification of the circuit model, the controller was designed with analog transfer functions and converted to and the discrete domain for digital controller implementation. A 150-W single-switch bridgeless SEPIC PFC converter prototype was built accordingly to verify the design. In addition to the current loop controller design for stability, a feed-forward compensator for is introduced and derived for better waveform quality. Simulation results and experiment results are also presented to verify the complete controller with feed-forward compensation. The Texas Instruments (TI) digital signal processor (DSP) TMS320F28335 was adopted for digital controller implementation. For comparison purpose, the TI UC3854 controller was implemented to verify the analog controller design results.
Master of Science

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22

Yilmaz, Hasan. "Design, Application And Comparison Of Single Stage Flybackand Sepic Pfc Ac/dc Converters For Power Led Lighting Application." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12615097/index.pdf.

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In this work, single stage power factor corrected AC/DC converters for LEDs
single stage Flyback converter having different configuration from the traditional Flyback and single stage SEPIC converter is investigated. The study involves analysis, circuit design, performance comparisons and implementation. The study covers LEDs
their developments, characteristics and state-of-art in this new technology. The circuits are investigated by means of computer simulations. Operating principles and operating modes are studied along with design calculations. After applying prototypes in laboratory, the simulation results and theoretical analyses are confirmed. The single stage Flyback converter has high voltage input (220-240 Vac), and the output feeds up to 216 HB-LEDs, with the ratings of 24 V, 3.25 A with 90 W. The single stage SEPIC converter with universal input (80-265 Vac) has an output that feeds 21 power LEDs, with 67 V, 0.30 and 20 W ratings.

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23

Beltrame, Fernando. "Análise comparativa de conversores monofásicos aplicados a correção de fator de potência." Universidade Federal de Santa Maria, 2009. http://repositorio.ufsm.br/handle/1/8473.

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This work presents a study and a comparative analysis of high power single-phase converter applied to power factor correctioii in according to the international standards IEC 61000-3-4 (harmonics limitation) and CISPR 22 (electromagnetic interference limitation) for high power applications. The converters studied were the conventional boost converter, the interleaved boost converter, with two cell operating with a delay angle of 180" between each other, and the dual boost converter. Such converters are used in front-end modules of information technology equipment. AI1 converters have the same input and output voltage and the same input current. The converters were projected to provide the same total input harmonic distortion (THD), with the idea of using the same input filter. Implementation of the control laws was performed through a digital control with the use of a 16 bits microcontroller. A11 converters were, first of all, studied and presented in this dissertation. The analyzed parameters for comparison were: power factor, total harmonic distortion (THD), semiconductor losses and magnetic losses, heat-sinks volume and magnetics volume, conducted electromagnetic interference, performance and costs.
Esse trabalho apresenta um estudo e uma análise comparativa de conversores monofásicos aplicados i correção de fator de potência que estejam de acordo com as normas internacionais IEC 61000-3-4 (limitação de harmônicos) e CISPR 22 (limitação dos níveis de interferência eletromagnética) para aplicações de alta potência. Os conversores estudados foram os conversores Boost, o conversor Boost Intercalado, com duas células operando com uma defasagem de 180" entre si, e o conversor Dual Boost. Tais conversores são utilizados como estágio de entrada em fontes de equipamentos da tecnologia da informação. Todos os conversores apresentam a mesma tensão de entrada e saída, e a mesma corrente de entrada. Os conversores foram projetados para apresentarem a mesma taxa de distorção harmônica da corrente de entrada (THD) para que, dessa forma, todos tenham o mesmo filtro de entrada. A implementação das leis de controle foi realizada através de um controlador digital com o uso de um microcontrolador de 16 bits. Todos os conversores foram primeiramente estudados e são apresentados nesta dissertação. Os parâmetros analisados para a comparação das topologias foram: fator de potência, taxa de distorção harmônica, perdas nos dispositivos semicondutores e magnéticos, volume dos dissipadores e materiais magnéticos, interferência eletromagnética conduzida, eficiência e custos.

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Unal, Teoman. "Design Of A Single-phase Full-bridge Diode Rectifier Power Factor Corrector Educational Test System." Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/2/12608148/index.pdf.

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In this thesis an educational test bench for studying the power quality attributes of the commonly used single-phase full-bridge diode rectifiers with power factor correction (PFC) circuits is designed and tested. This thesis covers the active and passive power factor correction methods for single-phase bridge rectifier. Passive filtering approach with dc side inductor and tuned filter along with active filtering approach via singleswitch boost converter is considered. Analysis, simulation, and design of a single phase rectifier and PFC circuits is followed by hardware implementation and tests. In the active PFC approach, various control methods is applied and compared. The educational bench is aimed to useful for undergraduate and graduate power electronics course, power quality related laboratory studies.

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25

Hernandez, Michael. "Applications of modern control in power electronics." Paris 11, 2010. http://www.theses.fr/2010PA112161.

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Dans la première partie, cette dissertation continue le cadre pour l'analyse et la conception (probablement des compensateurs de facteur) de puissance (PF) non linéaire pour les systèmes électriques fonctionnant dans des régimes nonsinusoïdaux (mais périodiques) avec les charges non linéaires. En particulier, dans la prétention standard que le générateur est une source de tension sans l'impédance, nous avons caractérisé toutes les charges non linéaires dont le pf est amélioré avec un compensateur non linéaire indiqué. Et ce cadre est employé pour étudier le problème de lacompensation passive de pf d'un redresseur commandé par pont classique. Est donné le fonctionnement "à l'avance de phase" du redresseur qu'on s'attend à ce que la compensation capacitive améliore le pf. Il est cependant moins évident que ceci puisse également être réalisé (dans quelques conditions appropriées) avec des inducteurs. Dans la deuxième partie, on a proposé la méthodologie d’A pour concevoir les contrôleurs (PI) proportionnel-intégraux linéaires utilisés des applications de convertisseur de puissance et en assurant la stabilité asymptotique. La technique s’est fondée sur le fait de base que si un système d’affinage peut être rendu passif avec une commande constante, alors il est stabilisable avec pi. Un état structural a été imposé alors au convertisseur de puissance pour satisfaire l’ancienne propriété avec un résultat passif produit comme combinaison linéaire des états. Cette condition est technique et n’a aucune interprétation physique claire. Ce résultat est prolongé dans trois directions : d’abord, la condition mentionnée ci-dessus est enlevée ; en second lieu, une plus grande classe des convertisseurs (avec des sources extérieures de commutation) est considérée ; troisièmement, la résistance de charge est assumée qu’on propose l’inconnu et un contrôleur adaptatif de pi (avec trois estimateurs différents). La méthodologie est appliquée au problème de la compensation de facteur de puissance d’un redresseur triphasé de source de tension, avec des résultats de simulation proposés. En outre, pi adaptatif stable est conçu pour la régulation de tension de rendement d’un convertisseur quadratique de poussée montrant l’exécution au moyen de résultat expérimental. Dans la troisième partie quelques contrôleurs basés sur le concept de la commande de charge pour un convertisseur utilisé dans une mise sous tension la correction de facteur sont montrés. Le convertisseur se compose par le raccordement intercalé de deux convertisseurs ou plus de poussée reliée à la grille à l’aide d’un redresseur de diode non commandé. La commande de charge représente une solution bon marché pour garantir la mise en commun courante entre les différents convertisseurs impliqués, et est normalement employée en combination avec d’autres contrôleurs. Les deux contrôleurs sont d’abord conçus pour garantir le facteur de puissance de près d’un avec la tension CC Réglée, à laquelle la commande de charge est ajoutée pour distribuer le courant égal parmi les convertisseurs. En conclusion, on présente une simplification avec l’exécution semblable qui élimine l’utilisation des sondes courantes, excepté les transformateurs de courant exigés pour mettre en application la commande de charge, des résultats expérimentaux accomplissent cette cloison. La quatrième partie, présente l’exécution et la programmation d’une méthode pour dépister le point de puissance maximum (MPP) dans des applications (PV) photovoltaïques. Ce point de fonctionnement est d’intérêt spécial pendant qu’on l’exige pour extraire la puissance maximum disponible à partir des rangées photovoltaïques
In the first part, this dissertation continues with the framework for analysis and design of (possibly nonlinear) power factor (PF) compensators for electrical systems operating in non-sinusoidal (but periodic) regimes with nonlinear loads. In particular, under the standard assumption that the generator is a voltage source with no impedance, we characterized all nonlinear loads whose PF is improved with a given nonlinear compensator. And this framework is used to study the problem of passive PF compensation of a classical half-bridge controlled rectifier. Given the “phase advance” operation of the rectifier it is expected that capacitive compensation improves PF, it is however less obvious that this can also be achieved (under some suitable conditions) with inductors. In the second part, A methodology to design linear proportional-integral (PI) controllers used in power converter applications and ensuring asymptotic stability was proposed. The technique relied on the basic fact that if an affine system can be rendered passive with a constant control, then it is stabilizable with a PL A structural condition was imposed then on the power converter to satisfy the former property with a passive output generated as a linear combination of the states. This condition is technical and has no clear physical interpretation. This result is extended in three directions : first, the aforementioned condition is removed ; second, a larger class of converters (with switching external sources) is considered ; third, the load resistance is assumed unknown and an adaptive PI controller (with three different estimators) is proposed. The methodology is applied to the problem of power factor compensation of a 3-phase. Voltage source rectifier, with simulation results proposed. Also, a stable adaptive PI is designed for the output voltage regulation of a quadratic boost converter showing the performance by means of experimental result. In the third part some controllers based on the concept of charge control for a converter used in an application of power factor correction are shown. The converter is composed by the interleaved connection of two or more boost converters connected to the grid by means of a non controlled diode rectifier. Charge control represents a cheap solution to guarantee current sharing among the different converters involved, and is normally used in combination with other controllers. The two controllers are first designed to guarantee the power factor close to one with regulated DC voltage, to which charge control is added to distribute equal current among the converters. Finally, a simplification with similar performance is presented that eliminates the use of current sensors, except for the current transformers required to implement the charge control, experimental results complete this part. The fourth part presents the implementation and programming of a method to track the maximum power point (MPP) in photovoltaic (PV) applications. This operation point is of special interest as it is required to extract the maximum power available from the photovoltaic arrays

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Sun, Jing. "New leading/trailing edge modulation strategies for two-stage AC/DC PFC adapters to reduce DC-link capacitor ripple current." Thesis, Texas A&M University, 2003. http://hdl.handle.net/1969.1/5801.

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AC/DC adapters mostly employ two-stage topology: Power Factor Correction (PFC) pre-regulation stage followed by an isolated DC/DC converter stage. Low power AC/DC adapters require a small size to be competitive. Among their components, the bulk DC-link capacitor is one of the largest because it should keep the output voltage with low ripple. Also, the size of this capacitor is penalized due to the universal line voltage application. Synchronization through employing leading edge modulation for the first PFC stage and trailing edge modulation for the second DC/DC converter stage can significantly reduce the ripple current and ripple voltage of the DC-link capacitor. Thus, a smaller DC-link capacitance can be used, lowering the cost and size of the AC/DC adapter. Benefits of the synchronous switching scheme were already demonstrated experimentally. However, no mathematical analysis was presented. In this thesis, detailed mathematical analyses in per-unit quantity are given to facilitate the calculation of the DC-link capacitor ripple current reduction with Leading/Trailing Edge Modulation strategies. One of the limitations of leading/trailing edge modulation is that the switching frequencies of the two stages need to be equal to achieve the best reduction of the DC-link capacitor ripple current. The DC-link capacitor ripple current will become larger if the switching frequency of the DC/DC converter is larger than that of the PFC pre-regulator, which blocks us to employ higher frequency for isolated DC/DC converter to reduce its transformer size. This thesis proposed a new Leading/Trailing Edge Modulation strategy to further reduce the DC-link bulk capacitor ripple current when switching frequency of DC/DC converter stage is twice the switching frequency of PFC stage. This proposed pulse width modulation scheme was verified by simulation. Experimental results obtained through digital control based on FPGA are also presented in this thesis.

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JÃnior, Francisco JosÃ Barbosa de Brito. "Study, Design and Development of an AC-DC Buck+Boost Converter Applied to Battery Chargers for Electric Vehicle." Universidade Federal do CearÃ, 2013. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=11121.

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CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior
This work presents a study and design of an electronic power converter topology for on-board application in a battery charger for plug-in electric vehicles. The proposed topology is based on AC-DC converter Buck+Boost, which one is very attractive for this application due to its buck and boost characteristics in a single-stage power processing. Furthermore, this topology presents reduced weight and volume, since there is no transformer and only few components are presented in its structure. A theoretical study is performed through of qualitative and quantitative analysis, besides it is investigated the switching process and losses in the converter components. It is also performed a design example of a battery charger with rated output power of 1 kW, input voltage 220 Vac RMS and output voltage of 162 Vdc, corresponding to 12 batteries connected in series. A prototype for the indicated specifications was constructed in laboratory and tested experimentally. The simulation and experimental results obtained are used to validate the theoretical analysis and design. For rated load, it was obtained an efficiency of 96.5% and a power factor of 0.992, thus showing the effectiveness of the proposed converter.
Este trabalho apresenta o estudo e desenvolvimento de uma topologia de conversor eletrÃnico de potÃncia para a aplicaÃÃo embarcada em um carregador de baterias para veÃculos elÃtricos recarregÃveis atravÃs da rede elÃtrica. A topologia escolhida Ã baseada no conversor CA-CC Buck+Boost, onde a mesma torna-se bastante atrativa para este tipo de aplicaÃÃo por apresentar as caracterÃsticas elevadora e abaixadora de tensÃo em um Ãnico estÃgio de processamento de energia. AlÃm disso, esta topologia apresenta reduzido volume e peso, devido ao fato de nÃo apresentar transformador e possuir poucos componentes em sua estrutura. Um estudo teÃrico Ã realizado atravÃs das anÃlises qualitativa e quantitativa, alÃm das anÃlises do processo de comutaÃÃo e das perdas nos componentes do conversor. Neste trabalho Ã realizado um exemplo de projeto do carregador de baterias para aplicaÃÃo em veÃculos elÃtricos de 1 kW de potÃncia de saÃda, tensÃo de entrada eficaz de 220 Vca e tensÃo de saÃda de 162 Vcc, correspondente a 12 baterias conectadas em sÃrie. Um protÃtipo com as especificaÃÃes indicadas foi construÃdo e testado experimentalmente em laboratÃrio. Os resultados de simulaÃÃo e experimentais obtidos validaram a anÃlise teÃrica e o projeto realizado. Para carga nominal, foi obtido rendimento de 96,5% e fator de potÃncia de 0,992, comprovando assim o funcionamento da topologia utilizada.

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Wu, Jia. "Implementation of a 100kW Soft-Switched DC Bus Regulator Based on Power Electronics Building Block Concept." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/32468.

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Power electronics building blocks (PEBBs) are standardized building blocks used to integrate power electronics systems. The PEBB approach can achieve low cost, high redundancy, high reliability, high flexibility and easy maintenance for large-scale power electronics systems. This thesis presents the implementation of a 100kW PEBB-based soft-switched bus regulator for an 800V DC distributed power system. The zero current transition (ZCT) soft-switching technique is used to improve the performance of the bus regulator by minimizing switching loss and improving overall efficiency. PEBB modules and a digital control building block are the subsystems of the DC bus regulator. This thesis addresses the design issues at subsystem and system levels. These include: operational principles and design of ZCT PEBB modules; design and implementation of the digital control block, based on DSP and EPLD; and modeling and control design of the DC bus regulator. There are several considerations when using the ZCT soft-switching technique in three-phase applications: the timing of the auxiliary switch gate signals must be arranged differently; there are low-frequency harmonics caused by the pulse width limits; and there is high thermal stress on the resonant capacitors. These issues are resolved by utilizing the sensed phase current information and the design freedom in the PWM modulator. A PWM modulation technique is proposed that can considerably reduce the switching events and further remove the associated loss while keeping THD low. Reduced switching events alleviate the thermal issue of the resonant capacitors. The same modulation technique can avoid the low-frequency harmonics caused by the pulse width limits and double the sampling frequency. The phase current information is used to deal with the control timing issue of the auxiliary switches and to control the three-phase soft-switching operation in order to achieve better efficiency. Additionally, the phase current information is used to implement dead time compensation to reduce THD. The soft-switched DC bus regulator has been tested up to a 100kW power level with 20kHz switching frequency. Experimental results demonstrate that high performance of the DC bus regulator is accomplished in terms of wide control bandwidth, low THD, unity power factor, high efficiency and high power density.
Master of Science

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29

Krist, Jakub. "Spínaný napájecí zdroj." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-221027.

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The thesis is focused on design the switching power supply according to Push-pull topology rules. The work describes basic theoretic principles of Push-pull topology with design of circuit and circuit elements.

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30

Marita, Marius G. "Analysis and implementation of ripple current cancellation technique for electronic ballasts." Cleveland State University / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=csu1254485537.

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Holub, Miroslav. "DC-DC měnič pro palubní dobíjení elektromobilu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-401968.

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This master thesis deals with design of DC-DC converter for onboard charging of electric vehicle. Developed converter will mainly be used for charging stationary traction battery in laboratory. Output voltage of this charger will be adjustable by user in between 200 V and 450 V depending on the current charged battery configuration. Output current limit is set at 8 A. Since the converter will be supplied from standard household socket, the problem of power factor correction must be solved during the design. That is because a large part of this thesis is focused on describing the problematics of power factor correction. After that, active PFC module is designed, completed and performance of this module is verified. To achieve low overall losses and thus be able to keep small volume of the system, modern switching components based on Silicon Carbide were preferred. Beside laboratory use, completed system will be used to emphasize volumetric difference between onboard chargers based on old versus modern switching components.

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Eleyele, Abidemi Oluremilekun. "Isolated Single-Stage Interleave Resonant PFC Rectifier with Active and Novel Passive Output Ripple Cancellation Circuit." Thesis, Uppsala universitet, Institutionen för elektroteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-423117.

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With the increasing demand for fast, cheaper, and efficient power converters come the need for a single-stage power factor correction (PFC) converter. Various single-stage PFC converter proposed in the literature has the drawback of high DC bus voltage at the input side and together with the shift to wide bandgap switches like GaN drives the converter cost higher. However, an interleaved topology with high-frequency isolation was proposed in this research work due to the drastic reduction in the DC bus voltage and extremely low input current ripple thereby making the need for an EMI filter circuit optional. Meanwhile, this research work focuses on adapting the proposed topology for a high voltage low current application (EV charger - 400V, 7KW) and low voltage high current application (telecom power supply - 58V, 58A) owing to cost benefits. However, all single-stage PFC are faced with the drawback of second-order (100Hz) output harmonic ripple. Therefore, the design and simulation presented a huge peak to peak ripple of about 50V/3A and 26V/26A for the EV charger and telecom power supply case, respectively. This created the need for the design of a ripple cancellation circuit as the research required a peak to peak ripple of 8V and 200mV for the EV - charger and telecom power supply, respectively. A novel output passive ripple cancellation technique was developed for the EV charger case due to the ease it offers in terms of control, circuit complexity and extremely low THDi when compared with the active cancellation approach. The ripple circuit reduced the 50V ripple to 431mV with the use of a total of 2.2mF capacitance at the output stage. Despite designing the passive technique, an active ripple cancellation circuit was designed using a buck converter circuit for the telecom power supply. The active approach was chosen because the passive has a slow response and incurs more loss at a high current level. Adding the active ripple cancellation circuit led to a quasi-single stage LLC PFC converter topology. A novel duty-ratio feedforward control was added to synchronize the PFC control of the input side with the buck topology ripple cancellation circuit. The addition of the ripple circuit with the feedforward control offered a peak to peak ripple of 6.7mV and a reduced resonant inductor current by half. After analysis, an extremely low THDi of 0.47%, PF of 99.99% and a peak efficiency of 97.1% was obtained for the EV charger case. The telecom power supply offered a THDi of 2.3%, PF of 99.96% with a peak efficiency of 95%.

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33

Melo, Guilherme de Azevedo e. [UNESP]. "Retificador entrelaçado boost, no modo de condução descontínua, com técnica de correção da corrente de entrada e elevado fator de potência, para aplicação em sistema trólebus." Universidade Estadual Paulista (UNESP), 2010. http://hdl.handle.net/11449/100358.

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Esta tese apresenta o desenvolvimento e os principais resultados para um retificador monofásico pré-regulador ”boost” para aplicação em sistema trólebus, possibilitando sua alimentação em corrente alternada (CA) ou em corrente contínua (CC), mantendose o sistema tradicional de distribuição da alimentação a dois fios. A estrutura proposta é composta por um retificador monofásico convencional, conectado a um conversor “boost” entrelaçado com cinco células, operando no modo de condução descontínua (MCD), reduzindo as perdas de comutação no diodo “boost”, interferências eletromagnéticas (EMI - electromagnetic interference) e propiciando o controle de forma simples, robusta e confiável para a estrutura. Além disso, devido às características das linhas de distribuição, a estrutura proposta pode atuar como conversor CA para CC ou CC para CC, fornecendo nível de tensão dentro da faixa adequada para o barramento CC. Quando alimentado pelo sistema em CA monofásico, o conversor propicia elevado fator de potência com reduzida distorção harmônica total de corrente (DHTi), atendendo plenamente às restrições da norma internacional IEC 61000-3-4. Adicionalmente, uma técnica de correção para a corrente de entrada, utilizando referência da tensão de entrada, é utilizada para garantir os baixos níveis de distorção harmônica, uma vez que a operação do pré-regulador retificador “boost” entrelaçado em MCD ocorre com reduzido ganho estático. Para a implementação do controle da regulação de tensão e correção da corrente de entrada, é empregado um dispositivo FPGA (field programmable gate array) utilizando linguagem de descrição de hardware (VHDL - verilog hardware description language). Utilizando o mesmo dispositivo FPGA, foi desenvolvido um controle de gerenciamento da operação, promovendo a comutação automática quando...
This thesis presents the development and experimental analysis of a special input stage converter for a Trolleybus type vehicle allowing its operation in AC (two wires, singlephase) or DC distribution networks. The proposed input stage architecture is composed by a conventional single-phase rectifier connected with a five interleaved boost rectifiers operating in discontinuous conduction mode (DCM), avoiding commutation boost diode losses, electromagnetic interference (EMI) and promoting simple control actions, robustness and reliability for the structure. Furthermore, due to the power lines characteristics, the proposed input power structure can act as AC to DC or as DC to DC converter providing a proper DC output voltage range required to the DC bus. When operating as AC to DC, the converter is capable to provide high power factor with reduced input current harmonic distortion, complying with the imposed restrictions by IEC 61000-3-4 standard. In addition, a special input current correction technique, using input voltage reference, is employed in order to achieve low harmonic distortions considering operation with low voltage static gain for the DCM interleaved boost rectifier pre-regulator. For implementation of the output voltage control and input current correction was used a field programmable gate array (FPGA) device with verilog hardware description language (VHDL). In addition using the same FPGA device, a management control system was implemented, promoting the required automatic operation changes when the vehicle is commuted from the DC power supply to the AC power supply and viceversa, keeping the original electrical DC bus characteristics for the trolleybus. After a brief review, a development work process is presented, containing the design methodology with all needed mathematical expressions, simulations, control circuits, as well as a 3D Computer-Aided Designs... (Complete abstract click electronic access below)

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34

Melo, Guilherme de Azevedo e. "Retificador entrelaçado boost, no modo de condução descontínua, com técnica de correção da corrente de entrada e elevado fator de potência, para aplicação em sistema trólebus /." Ilha Solteira : [s.n.], 2010. http://hdl.handle.net/11449/100358.

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Orientador: Carlos Alberto Canesin
Banca: Falcondes Jose Mendes de Seixas
Banca: Dionizio Paschoareli Junior
Banca: Luiz Carlos de Freitas
Banca: João Batista Vieira Junior
Resumo: Esta tese apresenta o desenvolvimento e os principais resultados para um retificador monofásico pré-regulador "boost" para aplicação em sistema trólebus, possibilitando sua alimentação em corrente alternada (CA) ou em corrente contínua (CC), mantendose o sistema tradicional de distribuição da alimentação a dois fios. A estrutura proposta é composta por um retificador monofásico convencional, conectado a um conversor "boost" entrelaçado com cinco células, operando no modo de condução descontínua (MCD), reduzindo as perdas de comutação no diodo "boost", interferências eletromagnéticas (EMI - electromagnetic interference) e propiciando o controle de forma simples, robusta e confiável para a estrutura. Além disso, devido às características das linhas de distribuição, a estrutura proposta pode atuar como conversor CA para CC ou CC para CC, fornecendo nível de tensão dentro da faixa adequada para o barramento CC. Quando alimentado pelo sistema em CA monofásico, o conversor propicia elevado fator de potência com reduzida distorção harmônica total de corrente (DHTi), atendendo plenamente às restrições da norma internacional IEC 61000-3-4. Adicionalmente, uma técnica de correção para a corrente de entrada, utilizando referência da tensão de entrada, é utilizada para garantir os baixos níveis de distorção harmônica, uma vez que a operação do pré-regulador retificador "boost" entrelaçado em MCD ocorre com reduzido ganho estático. Para a implementação do controle da regulação de tensão e correção da corrente de entrada, é empregado um dispositivo FPGA (field programmable gate array) utilizando linguagem de descrição de hardware (VHDL - verilog hardware description language). Utilizando o mesmo dispositivo FPGA, foi desenvolvido um controle de gerenciamento da operação, promovendo a comutação automática quando... (Resumo completo, clicar acesso eletrônico abaixo)
Abstract: This thesis presents the development and experimental analysis of a special input stage converter for a Trolleybus type vehicle allowing its operation in AC (two wires, singlephase) or DC distribution networks. The proposed input stage architecture is composed by a conventional single-phase rectifier connected with a five interleaved boost rectifiers operating in discontinuous conduction mode (DCM), avoiding commutation boost diode losses, electromagnetic interference (EMI) and promoting simple control actions, robustness and reliability for the structure. Furthermore, due to the power lines characteristics, the proposed input power structure can act as AC to DC or as DC to DC converter providing a proper DC output voltage range required to the DC bus. When operating as AC to DC, the converter is capable to provide high power factor with reduced input current harmonic distortion, complying with the imposed restrictions by IEC 61000-3-4 standard. In addition, a special input current correction technique, using input voltage reference, is employed in order to achieve low harmonic distortions considering operation with low voltage static gain for the DCM interleaved boost rectifier pre-regulator. For implementation of the output voltage control and input current correction was used a field programmable gate array (FPGA) device with verilog hardware description language (VHDL). In addition using the same FPGA device, a management control system was implemented, promoting the required automatic operation changes when the vehicle is commuted from the DC power supply to the AC power supply and viceversa, keeping the original electrical DC bus characteristics for the trolleybus. After a brief review, a development work process is presented, containing the design methodology with all needed mathematical expressions, simulations, control circuits, as well as a 3D Computer-Aided Designs... (Complete abstract click electronic access below)
Doutor

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Santelo, Thiago Naufal [UNESP]. "Célula de comutação de três estados aplicada ao pré-regulador boost de estágio único e elevado fator de potência." Universidade Estadual Paulista (UNESP), 2006. http://hdl.handle.net/11449/87241.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
Este trabalho apresenta um novo conversor PWM monofásico CA-CC, com um único estágio de retificação e correção do fator de potência, utilizando a célula de comutação de três estados. É demonstrado o conversor proposto empregando duas destas células, em substituição as configurações convencionais de duplo estágio, um estágio retificador e outro pré-regulador. A célula de comutação de três estados é composta basicamente por dois interruptores ativos, dois passivos e dois indutores acoplados magneticamente. A topologia desta célula permite que apenas metade da potência de entrada seja processada pelos interruptores ativos, reduzindo assim a corrente de pico sobre estes à metade do valor da corrente de pico da entrada, tornando importante para aplicações em potências mais elevadas. O volume dos elementos reativos (indutores e capacitores) é reduzido, pois, por características topológicas, a freqüência da ondulação da corrente e da tensão é o dobro da freqüência de operação dos interruptores, sendo assim, possível operar o conversor com menores freqüências, diminuindo consequentemente as perdas na comutação. As perdas totais são distribuídas entre todos semicondutores, facilitando a dissipação de calor. O paralelismo dos interruptores é muito atraente para a configuração do circuito estudado, possibilitando o uso de interruptores mais baratos. Outra vantagem é possuir uma menor faixa de operação na região de descontinuidade, ou seja, a faixa de operação no modo de condução contínua é ampliada. É realizado um estudo do conversor boost CC-CC operando com razão cíclica (0 < D < 0,5) e (0,5 < D < 1). Em seguida este conversor é empregado, operando em toda faixa de variação da razão cíclica (0 LÜD LÜ1), no conversor CA-CC de estágio único. O circuito do conversor em questão funciona em malha fechada utilizando o circuito integrado UC3854 para...
This work presents a new AC-to-DC PWM single-phase converter, with only one stage including rectification and power factor correction, using the three-state switching cell. It is demonstrated the proposed converter using two of these cells, instead of the conventional configurations that use a rectifier stage and a high-frequency pre-regulator. The three-state switching cell comprises two active switches, two diodes and two coupled inductors. In this topology only part of the input energy is processed by the active switches, reducing the peak current in these switches in a half of the peak value of the input current, making this topology suitable to the operation in larger power levels. The volume of the power reactive elements (inductors and capacitors) is also decreased since the ripple frequency on the output is twice the switching frequency. For a smaller operating frequency, the switching losses are decreased. Due to the topology of the converter, the total losses are distributed among all semiconductors, facilitating the heat dissipation. The parallelism of switches is very attractive for the studied configuration, facilitating the use of cheaper switches. Another advantage of this converter is the smaller region to operate in discontinuous conduction mode or, in other words, the operation range in continuous conduction mode is enlarged. It is developed a study of the DC-to-DC boost converter operating with duty (0 < D < 0,5) and (0,5 < D < 1). Then, this converter was used in full variation range of the duty-cycle (0 < D < 1) in the AC-to-DC single-stage converter. The circuit of this issue converter works with a feedback control line using the integrated circuit UC3854 to do the control in continuous conduction mode for input current with instantaneous average mode. Besides the mathematical analysis and development through...

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36

Morais, Douglas Carvalho. "Retificador trifásico boost semi-controlado, com elevado fator de potência e controle por razão cíclica variável." Universidade Estadual Paulista (UNESP), 2018. http://hdl.handle.net/11449/153785.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
Este trabalho tem como objetivo a proposição de um retificador trifásico boost semi-controlado, com correção ativa do fator de potência, que faça uso de técnicas de controle de razão cíclica variável, visando reduzir o conteúdo harmônico de corrente em baixa frequência. O conversor proposto opera em modo de condução descontínua, desta forma, a corrente de entrada segue uma envoltória senoidal. Além disso, devido ao modo de condução, o conversor apresenta a entrada em condução da chave com corrente nula, diminuindo assim, as perdas por chaveamento. Inicialmente, são apresentados, estudos teóricos da topologia em questão e, por meio de gráficos e equações, verifica-se a distorção harmônica imposta devida à operação com razão cíclica constante. Funções que permitam a variação permanente da razão cíclica, durante um ciclo da rede, serão apresentadas. Tais funções possuem o intuito de minimizar a distorção harmônica da corrente de entrada, com foco principal na 5ª componente harmônica. Resultados de simulação demonstram eficácia das técnicas de controle por razão cíclica variável e apontam redução no conteúdo harmônico de corrente. Resultados experimentais demonstram conteúdo harmônico de corrente em torno de 18% para operação do conversor com razão cíclica constante. A utilização de razão cíclica variável proporciona uma redução no conteúdo harmônico de corrente para 13%, resultando em um aumento do fator de potência.
This work aims propose a three-phase rectifier boost half-controlled, with power factor correction, that makes use variable duty cycle control techniques, in order to reduce the harmonic content of current in low frequency. The proposed converter operates in a discontinuous current conduction mode, this way, the input current is naturally corrected. Moreover, due to the conduction mode, the converter presents entry in conduction of switch with null current, thus decreasing, the losses by switching. Initially, are presented theoretical studies of the topology in question and, through of graphs and equations, the harmonic distortion imposed by operation due constant duty cycle is verified. Functions that allow permanently the variation of duty cycle, during a network cycle, are presented. These functions have as main objective minimize the harmonic distortion in the input current, with focus in the 5th harmonic component. Simulation results demonstrate efficacy of techniques by variable duty cycle control and indicate a reducing of harmonic content of current. Experimental results demonstrate a reducing around 18% for operation with constant duty cycle. The use of variable duty cycle provides a reducing around 13%, resulting in an increase of the power factor.

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37

Santelo, Thiago Naufal. "Célula de comutação de três estados aplicada ao pré-regulador boost de estágio único e elevado fator de potência /." Ilha Solteira : [s.n.], 2006. http://hdl.handle.net/11449/87241.

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Resumo: Este trabalho apresenta um novo conversor PWM monofásico CA-CC, com um único estágio de retificação e correção do fator de potência, utilizando a célula de comutação de três estados. É demonstrado o conversor proposto empregando duas destas células, em substituição as configurações convencionais de duplo estágio, um estágio retificador e outro pré-regulador. A célula de comutação de três estados é composta basicamente por dois interruptores ativos, dois passivos e dois indutores acoplados magneticamente. A topologia desta célula permite que apenas metade da potência de entrada seja processada pelos interruptores ativos, reduzindo assim a corrente de pico sobre estes à metade do valor da corrente de pico da entrada, tornando importante para aplicações em potências mais elevadas. O volume dos elementos reativos (indutores e capacitores) é reduzido, pois, por características topológicas, a freqüência da ondulação da corrente e da tensão é o dobro da freqüência de operação dos interruptores, sendo assim, possível operar o conversor com menores freqüências, diminuindo consequentemente as perdas na comutação. As perdas totais são distribuídas entre todos semicondutores, facilitando a dissipação de calor. O paralelismo dos interruptores é muito atraente para a configuração do circuito estudado, possibilitando o uso de interruptores mais baratos. Outra vantagem é possuir uma menor faixa de operação na região de descontinuidade, ou seja, a faixa de operação no modo de condução contínua é ampliada. É realizado um estudo do conversor boost CC-CC operando com razão cíclica (0 < D < 0,5) e (0,5 < D < 1). Em seguida este conversor é empregado, operando em toda faixa de variação da razão cíclica (0 LÜD LÜ1), no conversor CA-CC de estágio único. O circuito do conversor em questão funciona em malha fechada utilizando o circuito integrado UC3854 para...
Abstract: This work presents a new AC-to-DC PWM single-phase converter, with only one stage including rectification and power factor correction, using the three-state switching cell. It is demonstrated the proposed converter using two of these cells, instead of the conventional configurations that use a rectifier stage and a high-frequency pre-regulator. The three-state switching cell comprises two active switches, two diodes and two coupled inductors. In this topology only part of the input energy is processed by the active switches, reducing the peak current in these switches in a half of the peak value of the input current, making this topology suitable to the operation in larger power levels. The volume of the power reactive elements (inductors and capacitors) is also decreased since the ripple frequency on the output is twice the switching frequency. For a smaller operating frequency, the switching losses are decreased. Due to the topology of the converter, the total losses are distributed among all semiconductors, facilitating the heat dissipation. The parallelism of switches is very attractive for the studied configuration, facilitating the use of cheaper switches. Another advantage of this converter is the smaller region to operate in discontinuous conduction mode or, in other words, the operation range in continuous conduction mode is enlarged. It is developed a study of the DC-to-DC boost converter operating with duty (0 < D < 0,5) and (0,5 < D < 1). Then, this converter was used in full variation range of the duty-cycle (0 < D < 1) in the AC-to-DC single-stage converter. The circuit of this issue converter works with a feedback control line using the integrated circuit UC3854 to do the control in continuous conduction mode for input current with instantaneous average mode. Besides the mathematical analysis and development through...
Orientador: Falcondes José Mendes de Seixas
Coorientador: Grover Victor Torrico Bascopé
Banca: Fabio Toshiaki Wakabayashi
Banca: João Onofre Pereira Pinto
Mestre

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38

Almeida, Pedro Santos. "Conversor integrado SEPIC buck-boost aplicado ao acionamento de LEDs de potência em iluminação pública." Universidade Federal de Juiz de Fora, 2012. https://repositorio.ufjf.br/jspui/handle/ufjf/2037.

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CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
Este trabalho apresenta um estudo acerca da alimentação de diodos emissores de luz (LEDs) a partir da rede elétrica empregando conversores eletrônicos com correção do fator de potência. O estudo visa o desenvolvimento de um conversor que pode ser aplicado em iluminação pública, que atenda às demandas típicas de alto fator de potência, alta eficiência, reduzido número de componentes, baixa distorção harmônica da corrente de entrada e possa atingir uma elevada vida útil, através da substituição de capacitores eletrolíticos no circuito de potência por capacitores de filme. É proposta uma nova topologia de conversor para implementar tal acionamento, baseado em uma integração entre dois estágios, que passam a compartilhar um único interruptor estático. Os conversores SEPIC e buck-boost operando em modo de condução descontínua (DCM) são escolhidos para compor cada um destes estágios, atuando o primeiro na correção do fator de potência e o segundo na regulação de corrente na carga. Uma metodologia de projeto que visa excluir os capacitores eletrolíticos é desenvolvida, partindo de dados fotométricos que permitem aplicar nos LEDs uma ondulação limite de 50% em amplitude, sem causar prejuízos ao seu desempenho fotométrico. Um protótipo de 70 W é apresentado, cujos resultados experimentais demonstram alto fator de potência (0,998), baixa distorção harmônica de corrente (3,2%) e alta eficiência (90,2%), enquanto empregando somente capacitores de filme metalizado, de longa vida útil, no circuito de potência. Uma abordagem das possibilidades de se implementar um controlador digital para o novo conversor proposto é feita, partindo de um modelo de pequenos sinais para o conversor operando em DCM.
This work presents a study regarding the feeding of light-emitting diodes (LEDs) from mains (grid power) employing electronic drivers with power factor correction. The study aims the development of an LED driver which can be applied to public and street lighting, complying with the typical demands of high power factor, high efficiency, reduced component count, low total harmonic distortion (THD) of input current and which can attain long lifespan, through the substitution of electrolytic capacitors within the power circuit by film capacitors. It is proposed a new converter topology to implement such driver, based on an integration between two stages which share a common static power switch. The SEPIC and buck-boost converters operating in discontinuous conduction mode (DCM) are chosen to make up each of these two stages, the first acting as a power factor corrector and the second as a load currentcontrolling stage. A design methodology which aims the exclusion of electrolytic capacitors is developed, stemming from photometric data which allow the LEDs to be operated with current ripples up to 50% in amplitude, without causing any harm to their photometric performance. A 70 W prototype is presented, whose experimental results demonstrate high power factor (0.998), low current harmonic distortion (3.2%) and high efficiency (90.2%), while employing only long-life metallised-film capacitors on the power circuit. An approach to the possibilities of implementing a digital controller for the proposed novel converter is done, starting from a small-signal model for the converter operating in DCM.

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39

Soares, Antonio Wallace Antunes. "Projeto em FPGA de um controlador unificado para corre??o de fator de pot?ncia em retificadores boost bidirecionais monof?sicos." Universidade Federal do Rio Grande do Norte, 2013. http://repositorio.ufrn.br:8080/jspui/handle/123456789/15499.

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Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior
The use of Field Programmable Gate Array (FPGA) for development of digital control strategies for power electronics applications has aroused a growing interest of many researchers. This interest is due to the great advantages offered by FPGA, which include: lower design effort, high performance and highly flexible prototyping. This work proposes the development and implementation of an unified one-cycle controller for boost CFP rectifier based on FPGA. This controller can be applied to a total of twelve converters, six inverters and six rectifiers defined by four single phase VSI topologies and three voltage modulation types. The topologies considered in this work are: full-bridge, interleaved full-bridge, half-bridge and interleaved half-bridge. While modulations are classified in bipolar voltage modulation (BVM), unipolar voltage modulation (UVM) and clamped voltage modulation (CVM). The proposed project is developed and prototyped using tools Matlab/Simulink? together with the DSP Builder library provided by Altera?. The proposed controller was validated with simulation and experimental results
A utiliza??o de Field Programmable Gate Array (FPGA) para o desenvolvimento de estrat?gias de controle digital para aplica??es em eletr?nica de pot?ncia tem despertado um crescente interesse entre muitos pesquisadores. Tal interesse se deve as grandes vantagens apresentadas pelo FPGA, que incluem: menor esfor?o de projeto, alto desempenho e grande flexibilidade de prototipagem. Este trabalho prop?e o desenvolvimento e implementa??o de um controlador unificado, mediante o uso de FPGA, utilizando a t?cnica de controle de um ciclo (One-Cycle Control Technique) para corre??o de fator de pot?ncia com retificadores boost. Este controlador pode ser aplicado a um total de doze conversores, sendo seis inversores e seis retificadores, definidos pela topologia e pelo tipo de modula??o de tens?o. As topologias consideradas neste trabalho s?o: ponte completa, ponte completa intercalada, meia ponte e meia ponte intercalada. Enquanto que as modula??es s?o classificadas em modula??o bipolar de tens?o (MBT), modula??o unipolar de tens?o (MUT) e modula??o com grampeamento de tens?o (MGT). O projeto ? desenvolvido e prototipado utilizando as ferramentas Matlab?/Simulink em conjunto com a biblioteca DSP Builder, disponibilizada pela Altera?. O controlador proposto ? com resultados de simula??o e experimentais

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40

Ozturk, Salih Baris. "Direct torque control of permanent magnet synchronous motors with non-sinusoidal back-EMF." [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2728.

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41

Wu, Rong-hui, and 吳榮輝. "DESIGN OF TWO-STAGE BOOST POWER FACTOR CORRECTION." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/84559969850444277906.

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碩士
大同大學
電機工程學系(所)
97
ABSTRACT This thesis presents the problem with respect to the dual boost technique of the power factor correction ( PFC ) application. In the PFC a series problem will occur when the PFC is worked in single boost ( only one section_PFC bus is 400V ) even in low mains input, it will then generate a low mains voltage of switching loss on the PFC MOSFET to reduce the efficiency in low mains input . Therefore, In order to prevent this issue happened, we need to change the design concept from single boost to two-stage boost which can improve the efficiency when the input is in low mains voltage for EPA standard application. We knew that if we want to improve the efficiency in low mains voltage that is also passed EPA standard requirement which have to change the design concept to increase low mains voltage efficiency that means as below : Low mains input_90Vac~160Vac : PFC voltage is setting in 250Vdc High mains input_170Vac~264Vac : PFC voltage is setting in 400Vdc

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42

Liu, Kuan-Cheng, and 劉冠呈. "Quadratic High Gain Boost Converter with Power Factor Correction." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/94486285772842122777.

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碩士
輔仁大學
電機工程學系碩士在職專班
103
This thesis presents a quadratic high gain boost converter with power factor correction for high power application. It can be used to convert the AC input power to DC high output voltage and achieve high power factor. A quadratic high gain boost converter with switched capacitor and couple inductor circuit are used in this paper. Combined reboost and boost schemes, coupled inductor and charge-pump circuit is proposed to achieve high voltage gain. A commercial continuous conduction mode (CCM) control IC UC3854 is adopted as the PFC controller. The input current can be shaped as a sinusoidal waveform in phase with the input AC grid voltage. High efficiency and high power factor can be achieved by the proposed converter. The operating principles and design criteria are analyzed and discussed in details. A converter prototype was implemented and tested. The simulation and experimental results are shown to verify the feasibility of the proposed PFC converter.

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43

CHEN, JUN-TING, and 陳俊廷. "A Boundary-Mode Boost Power Factor Correction Control IC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/90884151565225112837.

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碩士
國立臺灣科技大學
電子工程系
98
This thesis aims to realize a boundary-mode control IC for single-switch boost power factor correction (PFC) converters. To reduce the low-frequency harmonics of the source current and achieve high power factor, the duty cycle must be regulated according to the ratio of the instantaneous source voltage and the output voltage for each switching period. In this thesis, a novel PFC control scheme with variable duty cycle is proposed. The operation principles and design considerations are analyzed and discussed. Compared with the conventional DCM PFC control method with fixed switching frequency and constant duty cycle, the proposed variable duty cycle control method has many merits such as low harmonics, high power factor, good voltage regulation, high efficiency, and simple circuit. The TSMC 0.35μm 2P4M 3.3/5V CMOS process is adopted for the implementation of this chip. The simulation results under different environment and process variations are shown to verify the feasibility of the proposed scheme.

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44

Rui-CheWang and 王睿澈. "Non-Inverting Buck-Boost Power-Factor-Correction Front-End Converter." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/45729638506489911403.

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碩士
國立成功大學
電機工程學系碩博士班
98
This thesis presents a boundary-conduction-mode (BCM) non-inverting buck-boost based power-factor-correction (PFC) converter for the wide input-voltage-range applications. This proposed converter has the functionality of both step-up and step-down conversion to provide the positive DC output-voltage. In order to achieve high power factor, high step-up voltage-conversion-ratio of the conventional boost PFC converter is required but leads to high voltage stress and cost of the components for the PFC stage and the following DC-DC converter stage. To reduce the voltage stress, the non-inverting buck-boost PFC converter with the step-up and step-down conversion functionality is utilized. In order to reduce the switching-loss in high-frequency applications, the BCM current control for the power switch to achieve zero-current turn-on switching is required. Finally, this thesis presents the design and implementation of the 70-watt prototype circuit for the proposed PFC converter. The experimental results are provided to validate the performance and feasibility of the proposed circuit.

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45

Yu, Yu-Wei, and 余育崴. "Application of Novel Buck-Boost Converter for Power Factor Correction." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/62948188713562734913.

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碩士
崑山科技大學
電機工程研究所
101
The article to the new drop - boost converter as the main core architecture, use of open-loop architecture, thus improving the power factor. This article mentioned the new drop - the choice of the boost converter parts,when the current in continuous operation can have a good conversion efficiency, content inclusion principle, motion analysis,AC input 60V DC output 40V experimental results. In the design of the circuit,first completion of the IsSpice simulation software simulation,with entities circuit experimental results to validate. The circuit portion without using a conventional linear regulator can be completed the step-up/step-down mode, can save circuit space, implement circuit results confirmed that this circuit power factor can reach 0.8, this circuit can be achieved a conversion efficiency of 75.9%.

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46

Zai, Zong-ru, and 蔡宗儒. "Design of Robust Dual Boost Converter Power Factor Correction Circuits." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/77714214170830200229.

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碩士
國立中山大學
電機工程學系研究所
99
The traditional AC/DC rectifier usually has the defects of low power factor and serious harmonic distortion and it results in serious pollution to the power system. This thesis proposes active power factor correction technique using a new AC/DC Dual Boost Converter. For power factor correction, inductor current is operated in the continuous conduction mode. First, the converter is analyzed by state space averaging method. Furthermore, we design applicable compensator by frequency analysis to implement a good power factor system. A classical PFC circuit with PI control law has low power factor under light load. In order to overcome problem, the thesis proposes a Dual Boost Converter circuit with robust performance. Comparing with circuits using PFC IC “UC3854”, the proposed system obtains higher power factor under the condition of the same light load.

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47

Chen, Chuen-Shiu, and 陳春旭. "The design of zero-voltage-transition(ZVT) power factor correction(PFC) circuit." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/16706264659421257343.

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48

Cheng, Yung-Sheng, and 鄭永昇. "Implementation of Analog and Digital Controlled Boost Power-Factor-Correction Rectifiers." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/77115711325218179337.

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碩士
崑山科技大學
電機工程研究所
98
The active power-factor-correction (PFC) rectifier based on a boost converter with average current-mode control (ACC) technique is investigated in the thesis. It would comply with the international current standards on power factor and input current distortion of power supplies. A boost PFC rectifier with ACC is controlled by two feedback loops, a fast inner current loop and a slow outer voltage loop. The current control of inner loop regulates the input current, so that its average value follows the rectified input voltage to achieve high power factor. The voltage control of outer loop maintains the rectifier output voltage at a reference level, against variation in load and fluctuation in line voltage. Form the control point of view, the main limitation of ACC-controlled PFC rectifiers is that the bandwidth of the voltage loop is less than 20 Hz in order to properly attenuate the contents of the second line harmonic at the control signal. Therefore, the dynamic response of the output voltage to load variation is slow. A load-current-injection control technique is applied to remedy the drawback. Both of analog and digital control methods are implemented for the boost PFC rectifiers. The analog control part with universal input voltage , output voltage and rated power is based on integrated circuit. The digital control part, with input voltage , output voltage and rated power is based on digital signal processor dsPIC30F4011. The experimental results are provided to verify the high power factor and the well output voltage regulation against the input voltage variation and load change.

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49

Huang, Po-Chun, and 黃柏鈞. "Analog Multiplier for Boundary Conduction Mode Boost Power Factor Correction Circuit." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/10298047996209696947.

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碩士
國立臺灣大學
電子工程學研究所
97
In recent years, harmonic distortion problem has been emphasized. To achieve the standards which were made by each country, power factor correctors have played an important role in switching power supplies. In current architecture of active power factor corrector, input current is controlled by input voltage which multiplies feedback control signal to become sinusoidal wave; hence analog multipliers are the heart of the control circuits. This thesis mainly discusses on an analog multiplier which can be applied to power factor corrector, and purposes a method by shifting input voltage up one threshold voltage, improving the analog multiplier using linear variable resistor applies in non-inverting amplifier. The linear variable resistor is composed of two MOS in parallel. One is operated in linear region, and the other is operated in saturation region. The value of linear variable resistance will change by input; therefore change the gain of non-inverting amplifier to realize multiplier. In this thesis, a complete boundary conduction mode boost PFC circuit is built with the proposed multiplier. Finally, simulation outcomes of Hspice verify that the purposed multiplier can be used for PFC circuit.

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Shy, Kuen-Horng, and 施錕鴻. "Dynamic Analysis and Controllers Design for High Power Factor Correction Boost Converters." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/57027632328681863686.

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Abstract:

碩士
國立成功大學
工程科學系
87
On the whole, the electricity quality depends upon the electricity supplied by power company. In addition, the load in the user end is also an essential factor on electricity quality. When the electric appliance with capacitive and/or inductive loads, or generating impulsive current with high harmonics the power factor is greatly degraded. This leads to large amount of energy losses. As a result, high power factor correction circuits are needed to avoid energy waste for a power company. There are two kinds of power factor correction (PFC) circuits. One is passive, and the other is active. Compared with the low efficiency, large volume and heavy weight of the traditional passive power factor correction circuit, the switching power factor correction circuits working in high frequency are the best choice. In this dissertation, the boost topology is used as the fundamental structure of the power factor correction circuit, because it can not only decrease current impulse, but also absorb the line voltage spike by inductor at input. The design of the active power factor correction circuit controllers includes an inner-loop current compensation and an outer-loop voltage compensation. There are three kinds of continuous current mode control : average current mode, peak current mode and hysteresis. In this dissertation, the hysteresis scheme is adopted. Then the equivalent small signal model of the power factor correction circuit with hysteresis is derived. Finally, three different compensators of classical controller, variable-structure controller and robust controller are designed. Their closed-loop dynamical behaviors are compared. The experimental results show that these controllers can improve power factor and regulate the output voltage inspite of the variations of load and output voltage. Finally, the preregulator UC3854 is used for high power factor correction of 160 W output power. The UC3854 uses average current-mode control without slope compensation needed in peak current-mode control. The experiment results show that the input current can track the input voltage in shape to achieve high power factor correction.

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