Dissertations / Theses: 'Power Factor Correction (PFC)'

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Xie, Manjing. "Digital Control for Power Factor Correction." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34258.

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This thesis focuses on the study, implementation and improvement of a digital controller for a power factor correction (PFC) converter. The development of the telecommunications industry and the Internet demands reliable, cost-effective and intelligent power. Nowadays, the telecommunication power systems have output current of up to several kilo amperes, consisting of tens of modules. The high-end server system, which holds over 100 CPUs, consumes tens of kilowatts of power. For mission-critical applications, communication between modules and system controllers is critical for reliability. Information about temperature, current, and the total harmonic distortion (THD) of each module will enable the availability of functions such as dynamic temperature control, fault diagnosis and removal, and adaptive control, and will enhance functions such as current sharing and fault protection. The dominance of analog control at the modular level limits system-module communications. Digital control is well recognized for its communication ability. Digital control will provide the solution to system-module communication for the DC power supply. The PFC converter is an important stage for the distributed power system (DPS). Its controller is among the most complex with its three-loop structure and multiplier/divider. This thesis studies the design method, implementation and cost effectiveness of digital control for both a PFC converter and for an advanced PFC converter. Also discussed is the influence of digital delay on PFC performance. A cost-effective solution that achieves good performance is provided. The effectiveness of the solution is verified by simulation. The three level PFC with range switch is well recognized for its high efficiency. The range switch changes the circuit topology according to the input voltage level. Research literature has discussed the optimal control for both range-switch-off and range-switch-on topologies. Realizing optimal analog control requires a complex structure. Until now optimal control for the three-level PFC with analog control has not been achieved. Another disadvantage of the three-level PFC is the output capacitor voltage imbalance. This thesis proposes an active balancing solution to solve this problem.
Master of Science

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Grote, Tobias [Verfasser]. "Digital control for interleaved boost power factor correction (PFC) rectifiers / Tobias Grote." Paderborn : Universitätsbibliothek, 2014. http://d-nb.info/105184813X/34.

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Gamboa, Gustavo. "REALIZATION OF POWER FACTOR CORRECTION AND MAXIMUM POWER POINT TRACKING FOR LOW POWER WIND TURBINES." Master's thesis, University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4283.

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In recent years, wind energy technology has become one of the top areas of interest for energy harvesting in the power electronics world. This interest has especially peaked recently due to the increasing demand for a reliable source of renewable energy. In a recent study, the American Wind Energy Association (AWEA) ranked the U.S as the leading competitor in wind energy harvesting followed by Germany and Spain. Although the United States is the leading competitor in this area, no one has been able successfully develop an efficient, low-cost AC/DC convertor for low power turbines to be used by the average American consumer. There has been very little research in low power AC/DC converters for low to medium power wind energy turbines for battery charging applications. Due to the low power coefficient of wind turbines, power converters are required to transfer the maximum available power at the highest efficiency. Power factor correction (PFC) and maximum power point tracking (MPPT) algorithms have been proposed for high power wind turbines. These turbines are out of the price range of what a common household can afford. They also occupy a large amount of space, which is not practical for use in one's home. A low cost AC/DC converter with efficient power transfer is needed in order to promote the use of cheaper low power wind turbines. Only MPPT is implemented in most of these low power wind turbine power converters. The concept of power factor correction with MPPT has not been completely adapted just yet. The research conducted involved analyzing the effect of power factor correction and maximum power point tracking algorithm in AC/DC converters for wind turbine applications. Although maximum power to the load is always desired, most converters only take electrical efficiency into consideration. However, not only the electrical efficiency must be considered, but the mechanical energy as well. If the converter is designed to look like a purely resistive load and not a switched load, a wind turbine is able to supply the maximum power with lower conduction loss at the input side due to high current spikes. Two power converters, VIENNA with buck converter and a Buck-boost converter, were designed and experimentally analyzed. A unique approach of controlling the MPPT algorithm through a conductance G for PFC is proposed and applied in the VIENNA topology. On the other hand, the Buck-boost only operates MPPT. With the same wind profile applied for both converters, an increase in power drawn from the input increased when PFC was used even when the power level was low. Both topologies present their own unique advantages. The main advantage for the VIENNA converter is that PFC allowed more power extraction from the turbine, increasing both electrical and mechanical efficiency. The buck-boost converter, on the other hand, presents a very low component count which decreases the overall cost and volume. Therefore, a small, cost-effective converter that maximizes the power transfer from a small power wind turbine to a DC load, can motivate consumers to utilize the power available from the wind.
M.S.E.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE

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Lee, Moonhyun. "Digital-Based Zero-Current Switching (ZCS) Control Schemes for Three-Level Boost Power-Factor Correction (PFC) Converter." Diss., Virginia Tech, 2020. http://hdl.handle.net/10919/99694.

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With the increasing demands on electronic loads (e.g. desktop, laptop, monitor, LED lighting and server) in modern technology-driven lives, performance of switched-mode power supply (SMPS) for electronics have been growing to prominence. As front-end converters in typical SMPS structure, ac-dc power-factor correction (PFC) circuits play a key role in regulations of input power factor, harmonics and dc output voltage, which has a decisive effect on entire power-supply performances. Universal ac-line and low-power system (90–264 Vrms, up to 300–400 W) is one of the most common power-supply specifications and boost-derived PFC topologies have been widely used for the purpose. In order to concurrently achieve high efficiency and low-cost system in the PFC stage, zero-current switching (ZCS) control schemes are highly employed in control principles. Representative schemes are discontinuous conduction mode (DCM) and critical conduction mode (CRM). Both modes can realize ZCS turn-on without diode reverse recovery so that low switching losses and low-cost diode utilizations are obtainable. Among various boost-family PFC topologies, three-level boost (TLB) converter has generated considerable research interest in high-voltage high-power applications. It is mainly due to the fact that the topology can have halved component voltage stresses, improved waveform qualities and electromagnetic interference (EMI) from phase interleaved continuous conduction mode (CCM) operations, compared to other two-level boost PFC converters. On the other hand, in the field of universal-line low-power applications, TLB PFC has been thoroughly out of focus since doubled component counts and increased control complexity than two-level topologies are practical burden for the low-cost systems. However, recent researches on TLB PFC with ZCS control schemes have found that cost-competitiveness of the topology is actually comparable to two-level boost PFC converters because the halved component voltage stresses enable usage of low voltage-rating components of which unit prices are cheaper than higher-rating ones. Based on the justification, researches on ZCS control schemes for TLB PFC have been conducted to get enhanced waveform qualities and performance factors. Following the research stream, a three-level current modulation scheme that can be adopted in both DCM and CRM is proposed in Chapter 2 of this dissertation. Main concept of the proposed current modulation is additional degree-of-freedom in current-slope shaping by differentiating on-times of two active switches, which cannot be found from any other single-phase boost-derived PFC topologies. Using the multilevel feature, proposed operations in one switching period consist of three steps: common-switch on-time, single-switch on-time and common-switch off-time. The single-switch on-time step is key design factor of the proposed modulation that can be utilized either in fixed or adjustable form depending on control purpose. Based on the basic modulation concept, three-level CRM control scheme, adjustable three-level DCM control scheme, and spread-spectrum frequency modulation (SSFM) with adjustable three-level DCM scheme are proposed in Chapter 3–5, respectively. In each chapter, implemented control scheme aims to improve different performance factors. In Chapter 3, the proposed three-level CRM scheme uses increased single-switch on-time period to reduce peak inductor current and magnitude of variable switching frequency. It is generally accepted fact that CRM operations suffer from high switching losses and poor efficiency at light load due to considerable increment of switching frequency. Thus, efficiency improvement effect by the proposed CRM scheme becomes remarkable as load condition goes lighter. In experimental verifications, maximum improvement is measured by 1.2% at light load (20%) and overall efficiency is increased by at least 0.4% all over the load range. In Chapter 4, three-level DCM control scheme adopts adjustable single-switch on-time period in fixed switching-frequency framework. The purpose of adjustable control scheme is to widen the length of non-zero inductor current period as much as possible so that discontinued current period and high peak current of DCM operations can be minimized. Experiment results show that, compared to conventional two-level DCM control, full-load peak inductor currents are reduced by 20.2% and 17.1% at 110 and 220 Vrms input voltage conditions, respectively. Moreover, due to turn-off switching energy decrements by the turn-off current reductions, efficiency is also improved by at least 0.4% regardless of input voltage and load conditions. In Chapter 5, a downward SSFM technique is developed first for DCM operations of boosting PFC converters including two-level topologies. This chapter aims to achieve significant reduction of high differential-mode (DM) EMI amplitudes from DCM operations, which is major drawback of DCM control. By using the simple linearized frequency modulation, peak DM EMI noise at full load condition is reduced by 12.7 dBμV than conventional fixed-frequency DCM control. On top of the proposed SSFM, the adjustable three-level DCM control scheme in Chapter 4 is adopted to get further reductions of EMI noises. Experimental results prove that the collaborations of SSFM and adjustable DCM scheme reduce the EMI amplitudes further by 2.5 dBμV than the result of SSFM itself. The reduced EMI amplitudes are helpful to design input EMI filter with higher cut-off frequency and smaller size. Different from two-level boosting PFC converters, TLB PFC topology has two output capacitors in series and inherently suffers from voltage unbalancing issue, which can be noted as topological trade-off. In Chapter 6, two simple but effective voltage balancing schemes are introduced. The balancing schemes can be easily built into the proposed ZCS control schemes in Chapter 3–5 and experimental results validate the effectiveness of the proposed balancing principles. For all the proposed control schemes in this dissertation, detailed operation principles, derivation process of key equations, comparative analyses, implementation method with digital controller and experimental verifications with TLB PFC prototype are provided.
Doctor of Philosophy
Electronic-based devices and loads have been essential parts of modern society founded on rapid advancements of information technologies. Along with the progress, power supplying and charging of electronic products become routinized in daily lives, but still remain critical requisites for reliable operations. In many power-electronics-based supplying systems, ac-dc power-factor correction (PFC) circuits are generally located at front-end to feed back-end loads from universal ac-line sources. Since PFC stages have a key role in regulating ac-side current quality and dc-side voltage control, the importance of PFC performances cannot be emphasized enough from entire system point of view. Thus, advanced control schemes for PFC converters have been developed in quantity to achieve efficient operations and competent power qualities such as high power factor, low harmonic distortions and low electromagnetic interferences (EMI) noises. In this dissertation, a sort of PFC topologies named three-level boost (TLB) converter is chosen for target topology. Based on inherent three-level waveform capability of the topology, multiple zero-current switching (ZCS) control schemes are proposed. Compared to many conventional two-level PFC topologies, TLB PFC can provide additional degree-of-freedom to current modulation. The increased control flexibility can realize improvements of various waveform qualities including peak current stress, switching frequency range, harmonics and EMI amplitude. From the experimental results in this dissertation, improvements of waveform qualities in TLB PFC with the proposed schemes are verified with comparison to two-level current control schemes; in terms of efficiency, the results show that TLB PFC with the proposed schemes can have similar converter efficiency with conventional two-level boost converter in spite of increased component counts in the topology. Further, the proposed three-level control schemes can be utilized in adjustable forms to accomplish different control objectives depending on system characteristics and applications. In each chapter of this dissertation, a novel control scheme is proposed and explained with details of operation principle, key equations and digital implementation method. All the effectiveness of proposals and analyses are validated by a proper set of experimental results with a TLB PFC prototype.

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Koh, Hyunsoo. "Modeling and Control of Single Switch Bridgeless SEPIC PFC Converter." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/34125.

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Due to increasing concerns on the power quality, power factor correction (PFC) has become an important issue in light-emitting diode (LED) lighting applications. A boost converter is one of the most well-known PFC topologies, due to its simple circuitry, simple control scheme and small number of passive components. Even though a boost converter is recognized as a typical PFC converter, its output voltage must be higher than its input voltage. This feature is disadvantageous because the device requires an additional buck-stage for LED lighting systems. As an alternative to the boost converter, a single-ended primary-inductor converter (SEPIC) allows output voltage to be lower or higher than the input voltage. Thus, the SEPIC converter is gaining popularity as a LED driver because it does not require additional power conversion stage. However, designing a controller to meet stability requirements and international standards is quite challenging for SEPIC converters. Additionally, if the digital controller is adopted for its built-in communication features, creating a digitally controlled SEPIC converter would be even more challenging. This thesis focuses on the state-space averaging modeling of the SEPIC PFC converter and the design of controllers based on both analog and digital controls with precise modeling. The proposed SEPIC converter incorporates RC damping circuits to avoid the instability, and thus the entire SEPIC converter becomes a 5th order system. Such a high-order system model was derived mathematically and verified with circuit simulator modeling. After verification of the circuit model, the controller was designed with analog transfer functions and converted to and the discrete domain for digital controller implementation. A 150-W single-switch bridgeless SEPIC PFC converter prototype was built accordingly to verify the design. In addition to the current loop controller design for stability, a feed-forward compensator for is introduced and derived for better waveform quality. Simulation results and experiment results are also presented to verify the complete controller with feed-forward compensation. The Texas Instruments (TI) digital signal processor (DSP) TMS320F28335 was adopted for digital controller implementation. For comparison purpose, the TI UC3854 controller was implemented to verify the analog controller design results.
Master of Science

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Yilmaz, Hasan. "Design, Application And Comparison Of Single Stage Flybackand Sepic Pfc Ac/dc Converters For Power Led Lighting Application." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12615097/index.pdf.

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In this work, single stage power factor corrected AC/DC converters for LEDs
single stage Flyback converter having different configuration from the traditional Flyback and single stage SEPIC converter is investigated. The study involves analysis, circuit design, performance comparisons and implementation. The study covers LEDs
their developments, characteristics and state-of-art in this new technology. The circuits are investigated by means of computer simulations. Operating principles and operating modes are studied along with design calculations. After applying prototypes in laboratory, the simulation results and theoretical analyses are confirmed. The single stage Flyback converter has high voltage input (220-240 Vac), and the output feeds up to 216 HB-LEDs, with the ratings of 24 V, 3.25 A with 90 W. The single stage SEPIC converter with universal input (80-265 Vac) has an output that feeds 21 power LEDs, with 67 V, 0.30 and 20 W ratings.

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Muhammad, Khairul Safuan Bin. "Design and Practical Implementation of Bridgeless Boost PFC Rectifier With Zero-Current Switching And Fault-Tolerant Operation." Thesis, The University of Sydney, 2015. http://hdl.handle.net/2123/14309.

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In this thesis, a new family of zero-current switching (ZCS) BBR with high power factor using only two active switches is proposed. The proposed BBR is based on a totem-pole BBR (TPBBR) configuration which allows the current to flow from high side to low side and vice versa during resonance. Hence, no auxiliary active switch is needed to provide soft-switching for all semiconductor devices. The soft-switching also reduces the body diode reverse recovery problem hence allows the TPBLB to operate in continuous conduction mode (CCM). Design considerations and parameter values calculations are given. An experimental prototype is developed and tested to verify the converter performance. The proposed FTBBR is based on an H-bridge rectifier configuration. Only two out of the four switches are needed to be working in order to ensure the continuity of the converter operation. A detailed analysis of the FTBBR operation under all open-circuit faults of the switches is presented. In addition, adding resonant networks to the FTBBR is also analysed. The FTBBR is controlled using similar PWM controller as proposed in the new ZCS BBR. An experimental prototype is developed and tested to verify the converter performance. The TPBBR requires a special switching techniques and sequences, where isolated gate driver is the best solution which allows both high and low side switches to be turned on simultaneously during resonance. As a solution to the gate driver, a magnetically isolated gate driver with high immunity to leakage inductance is proposed. The proposed gate driver (PGD) is developed based on a bipolar totem-pole gate driver (non-inverting) located on the secondary side of the coupling transformer. It is able to drive a MOSFET/IGBT from standard CMOS to TTL output and down to LSTTL level. It also achieves large duty cycle ratio and small input to output delay and provides reliable isolation. The PGD is analysed and verified experimentally.

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Damasceno, Daniel da Motta Souto. "Metodologia de projeto de conversores boost para correção de fator de potência apliocada a sistemas ininterruptos de energia." Universidade Federal de Santa Maria, 2006. http://repositorio.ufsm.br/handle/1/8539.

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This Master Thesis presents a design methodology to a boost PFC converter operating as an Uninterruptible Power Supply rectifier input stage. This methodology defines, making use of a group of current ripples and switching frequencies, the converter minimum volume point analyzing the volumes of the boost inductor, the electromagnetic interference filter and the heat-sinks. Thus, it's developed along this work, each design mentioned above, analyzing the impact of different magnetic materiaIs, input filter topologies and semiconductors technologies. Previously, it is designed the controller and it is developed a simulation structure. ln a second moment, it's designed the boost inductor for a predetermined temperature elevation. After this, it's designed the electromagnetic filter analyzing the impact of different topologies. The heat-sinks are also designed to guarantee the semiconductors operation within the temperature limits. Finally, the methodology based on the previous designs is accomplished, using the procedures and equations already mentioned, becoming possible to define the converter minimum volume point.
Esta Dissertação de Mestrado apresenta uma metodologia de projeto para o conversor boost operando como estágio retificador de entrada em uma fonte de alimentação ininterrupta. Essa metodologia se baseia em definir, através de um conjunto de freqüências de comutação e ondulações de corrente, o ponto de minimização do volume do conversor considerando o volume do indutor, do filtro de interferência eletromagnética conduzida e dos dissipadores. Assim, é desenvolvido ao longo desse trabalho o projeto de cada elemento mencionado estudando o impacto do uso de diferentes materiais magnéticos, topologias de filtro de entrada e tecnologias de semicondutores. Inicialmente é projetado o controlador e desenvolvida a estrutura de simulação do conversor. Em um segundo momento é projetado o indutor boost para uma determinada elevação de temperatura. A seguir é projetado o filtro de interferência eletromagnética analisando o impacto de diferentes topologias. Também são projetados os dissipadores que garantem a operação dos semicondutores dentro dos limites de temperatura estabelecidos pelos fabricantes. Por fim, é formalizada a metodologia baseada nos projetos anteriores, pela qual, fazendo uso dos procedimentos e equações fornecidos, torna-se possível definir o ponto de minimização do volume do conversor.

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Pham, Thi Thuy Linh. "Contribution à l’étude de nouveaux convertisseurs sécurisés à tolérance de panne pour systèmes critiques à haute performance. Application à un PFC Double- Boost 5 Niveaux." Thesis, Toulouse, INPT, 2011. http://www.theses.fr/2011INPT0095/document.

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Les conditionneurs alternatifs – continu à absorption sinusoïdale (PFC) pour les applications critiques se distinguent par un haut niveau de performances tel que les THD réduits, un haut rendement et une bonne fiabilité. Leur importance est d’autant plus nécessaire qu’une continuité de service des alimentations est requise même en présence d’une défaillance interne de composant. Deux types de structures associées à leur commande sont réalisés à cet effet, les structures à redondance parallèle et les structure à redondance en série. Elles consistent respectivement en l’ajout d’un bras d’interrupteur dans le cas de la redondance parallèle, qui est une option plus compliquée et en une suppression d’une cellule de commutation dans le deuxième cas. L’étude présentée ici, consiste en premier lieu en une exploration et une évaluation de nouvelles familles de topologies multi-niveaux, caractérisée par un partitionnement cellulaire en série. Ces nouvelles topologies, ainsi que leurs variantes, comportent au moins une redondance structurelle avec des cellules mono-transistor à défaut de commande non critique et symétriques à point-milieu. Elles sont donc génériques pour la mise en parallèle et l’extension en triphasé. Cependant, elles sont pour la plupart peu compétitives à cause des composants qui sont souvent surdimensionnés et donc plus onéreuses, en comparaison avec la structure PFC Double-Boost 5 Niveaux à composants standards 600 V (brevetée par l’INPT – LAPLACE –CNRS en 2008) que nous étudions. Cette dernière constitue le meilleur compromis entre un bon rendement et une maîtrise des contraintes en mode dégradé. Sur le plan théorique nous montrons que le seul calcul de fiabilité basé uniquement sur un critère de premier défaut est inadapté pour décrire ce type de topologie. La prise en compte de la tolérance de panne est nécessaire et permet d'évaluer la fiabilité globale sur une panne effective (i.e. au second défaut). L'adaptation de modèles théoriques de fiabilité à taux de défaillance constant mais prenant en compte, au niveau de leurs paramètres, le report de contrainte en tension et l'augmentation de température qui résulte d'un premier défaut, permet de chiffrer en valeur relative, le gain obtenu sur un temps court. Ce résultat est compatible avec les systèmes embarqués et la maintenance conditionnelle. Un prototype monophasé de PFC double-boost 5 niveaux à commande entièrement numérique et à MLI optimisée reconfigurable en temps réelle a été réalisé afin de valider l’étude. Il permet une adaptation automatique de la topologie de 5 à 4 puis 3 niveaux par exemple. Ce prototype a également servi de test d'endurance aux transistors CoolMos et diodes SiC volontairement détruits dans des conditions d'énergie maîtrisée et reproductibles. D’autres campagnes d'endurance en modes dégradés ont été réalisées en laboratoire sur plusieurs centaines d’heures en utilisant ce même prototype. Nous nous sommes axés sur la détection de défauts internes et le diagnostic (localisation) rapide, d'une part par la surveillance directe et le seuillage des tensions internes (tensions flottantes) et d'autre part, par la détection d’harmoniques (amplitude et phase) en temps réel. Ces deux techniques ont été intégrées numériquement et évaluées sur le prototype, en particulier la seconde qui ne requiert qu'un seul capteur. Enfin, nous proposons une nouvelle variante PFC expérimentée en fin de mémoire, utilisant deux fois moins de transistors et de drivers pour les mêmes performances fréquentielles au prix d'un rendement et d'une répartition des pertes légèrement moins favorable que la structure brevetée
This work is an exploration and an evaluation of new variants of multi-level AC/DC topologies (PFC) considering their global reliability and availability: electrical safety with an internal failure and post-failure operation. They are based on a non-differential AC and centre tap connection that led to symmetrical arrangement cells in series. These topologies permit an intrinsic active redundancy between cells in a same group and a segregation capability between the two symmetrical groups of cells. More again, they are modular and they can be paralleled and derived to any number of levels. Only single low-voltage (600V) transistor pear cell is used avoiding the short-circuit risk due to an unwanted control signal. Comparisons, taking into account losses, distribution losses, rating and stresses (overvoltage and over-temperature) during the post-operation are presented. Results highlight the proposed 5-level Double-Boost Flying Capacitor topology. This one was patented at the beginning of thesis, as a solution with the best compromise. On the theoretical side, we show that the reliability calculation based only on a "first fault occurrence" criterion is inadequate to really describe this type of topology. The inclusion of fault tolerance capability is needed to evaluate the overall reliability law (i.e. including a second failure). The adaptation of theoretical models with constant failure rate including overvoltage and over-temperature dependencies exhibit an increasing of the reliability over a short time. This property is an advantage for embedded systems with monitoring condition. Local detection and rapid diagnosis of an internal failure were also examined in this work. Two methods are proposed firstly, by a direct flying caps monitoring and secondly, by a realtime and digital synchronous demodulation of the input sampled voltage at the switching frequency (magnitude and phase). Both techniques have been integrated on FPGA and DSP frame and evaluated on a AC230V-7kW DC800V – 31kHz lab. set-up. We put forward the interest of the second method which only uses one input voltage sensor. Finally, we propose in this dissertation a new generic X-level PFC Vienna using, in 5-level version, half transistors and drivers for identical input frequency and levels. At the cost of a slight increase of losses and density losses, this topology appears very attractive for the future. A preliminary lab. set-up and test were also realized and presented at the end of the thesis

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Wang, Chuanyun. "Investigation on Interleaved Boost Converters and Applications." Diss., Virginia Tech, 2009. http://hdl.handle.net/10919/28635.

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With the rapid evolving IT technologies, today, the power factor correction (PFC) design is facing many challenges, such as power scalability, high entire-load-range efficiency, and high power density. Power scalability is a very desirable and cost-effective approach in the PFC design in order to keep up with serversâ growing power requirements. Higher power density can eventually reduce the converter cost and allows for accommodating more equipment in the existing infrastructures. Driven strongly by economic and environmental concerns, high entire-load-range efficiency is more and more required by various organizations and programs, such as the U.S. Energy Star, Climate Savers, and German Blue Angel. Today, the existing boost PFC is reaching its limitations to meet these challenges simultaneously. Using the cutting-edge semiconductor devices, further efficiency improvement at light load is still needed. There are limited approaches available for increasing the power density due to the large EMI filter and inductor size. Interleaved multi-channel boost PFC is a promising candidate to meet those challenges, but the interleaved boost converter is a less explored area. On the other hand, the multi-channel interleaved buck converter for the VR application has been intensively studied and thoroughly explored. One basic approach of this study is trying to extend the existing knowledge and techniques obtained from multiphase buck converters to the multi-channel interleaved boost converters since there are similarities existed between the multi-phase buck and the multi-channel boost converters. The existing studies about the interleaving impact on the EMI filter design are based on the time domain ripple cancellation effect. This approach is good enough for most of the filter designs. However, unlike the conventional filter designs, the EMI filter design is a specification related process. Both the EMI standard and the EMI measurement are based on the frequency domain spectrum. Limited by the existing analysis approaches, it is difficult to provide a clear picture about how exactly the multi-channel interleaving will impact the EMI filter design. The interleaving impact on the Common Mode (CM) noise also has not been studied in any existing literatures for the same reason. In this study, the frequency domain analysis method was adopted. With the double Fourier integral transformation, a closed-form expression of all the harmonics of the noise sources can be obtained. With all the detailed phase relationship of the switching frequency harmonics and all the side band harmonics, the multi-channel interleaving impact on both the differential mode (DM) and CM filter design can be clearly understood and summarized. According to the design curves provided, the EMI filter size can be effectively reduced by properly choosing the interleaving channel number and the switching frequency. The multi-channel interleaving impact on the output capacitor current ripple is also studied and summarized in this dissertation. It should be pointed out that interleaving only reduces the total input and output current ripples; the inductor current in each channel still has large ripple if small inductance is used. Similar to the multi-phase buck converter, coupling inductors result in different equivalent inductances for input current ripple and inductor current ripple for boost converters. Keeping the inductor current ripple magnitude the same, inverse coupling inductors between the interleaved channels can reduce the inductor size. However, the DM filter size is increased due to larger input current. Based on the investigation on the total magnetic component weight, inverse coupling inductor can reduce the total magnetic component weight. The reduction is more pronounced for lower switching frequency design when the inductor size is dominating among the total magnetic components. Based on the harmonic cancellation, and with all the detailed phase relationship of the switching frequency harmonics and all the side band harmonics, a novel phase angle control method is proposed to maximize the reduction of the EMI filter. For example, in a 2-channel interleaved PFC, just by changing the interleaving scheme to 90 degree phase shift, 39% total volume reduction of the EMI filter can be achieved. The proposed phase angle controlled multi-channel PFC is experimentally demonstrated and verified on a digital controlled 4-channel PFC. The phase angle control method proposed in the multi-channel boost converter can be applied back to the multi-phase buck converter as well. The harmonic cancellation principle will be the same as the multi-channel boost converter. The same benefits can be obtained when the requirement is defined in the frequency domain, e.g. the EMI Standard. The interleaved multi-channel configuration makes it possible to implement the phase-shedding to improve the PFC light load efficiency. By decreasing the number of active channels according to the load, the PFC light load efficiency can be optimized. However, shedding phases can reduce the ripple cancellation effect as well, which will result in the EMI noise increase and losing the benefit on the EMI filter. By applying the proposed phase-shedding with phase angle control strategy, the phase shedding impact on the EMI filter design can be minimized. The light load efficiency can be improved without compromising the EMI filter size. Then, adaptive frequency controlled PFC is proposed to further improve the PFC light load efficiency. The proposed light load efficiency improvement strategies are combined and implemented on the platform of the digital controlled 4-channel PFC. The benefit of improving the light load efficiency is experimentally verified. The EMI performance is also evaluated with the EMI measurement results obtained from the PFC prototype. Following the same approach explored, the benefits of interleaved boost converter can be further extended other applications, such as the boost converter in the Hybrid Electric Vehicles (HEV) and photovoltaic (PV) system.
Ph. D.

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JÃnior, JosÃ Ailton LeÃo Barboza. "A Double boost converter with PFC and series/parallel input connection for uninterrupted power system." Universidade Federal do CearÃ, 2012. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=16257.

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fator de potÃncia e recurso para operar com dois valores de tensÃo de entrada. O mesmo Ã aplicÃvel a sistemas ininterruptos de energia do tipo dupla conversÃo ou on-line com caracterÃsticas de tensÃo de entrada bivolt (110 Vca e 220 Vca) e desta maneira Ã descartada a utilizaÃÃo de um autotransformador com seletor de tensÃo. O conversor em estudo Ã composto por dois conversores CA-CC boost clÃssicos, em que, para uma tensÃo de entrada de 110 Vca as entradas sÃo conectadas em paralelo e para uma tensÃo de entrada de 220 Vca as entradas sÃo conectadas em sÃrie. A ideia Ã fazer com que se tenha uma divisÃo equilibrada na entrada de cada conversor quando a tensÃo da rede elÃtrica for 220 Vca. Assim cada conversor boost clÃssico recebe metade da tensÃo total de alimentaÃÃo do conversor proposto. A estratÃgia de controle Ã baseada no controle por modo corrente mÃdia aplicada a ambos os conversores para proporcionar a correÃÃo do fator de potÃncia e a regulaÃÃo da tensÃo de saÃda. Para verificar o estudo teÃrico foi desenvolvido o projeto do circuito de potÃncia e controle validando atravÃs de resultados de simulaÃÃo e experimentais para um protÃtipo de 2,4 kW. Para a conexÃo paralelo e sÃrie das entradas, os resultados obtidos foram satisfatÃrios e o conversor operou adequadamente.
This work presents a study of a Double Boost AC-DC Converter with power factor correction and dual input voltage operation capability via a selector switch. Such converter can be applied to on-line uninterruptible power supplies with dual voltage input characteristics, this way avoiding the usage of a low frequency autotransformer. The studied structure is composed by two AC-DC classical boost converters, in which for input voltage of 110 Vac both its inputs are connected in parallel, and, for 220 Vac, they are connected in series. The control strategy is based in the average current mode control applied to both converters, in order to provide the power factor correction and output voltage regulation. Simulation and experimental results for 2.4 kW are presented, and so are validate the theoretical study and design. Connecting the inputs in parallel and series, the results were satisfactory and the converter operated properly.

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Hertz, Erik M. "Thermal and EMI Modeling and Analysis of a Boost PFC Circuit Designed Using a Genetic-based Optimization Algorithm." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/34234.

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The boost power factor correction (PFC) circuit is a common circuit in power electronics. Through years of experience, many designers have optimized the design of these circuits for particular applications. In this study, a new design procedure is presented that guarantees optimal results for any application. The algorithm used incorporates the principles of evolution in order to find the best design. This new design technique requires a rethinking of the traditional design process. Electrical models have been developed specifically for use with the optimization tool. One of the main focuses of this work is the implementation and verification of computationally efficient thermal and electro-magnetic interference (EMI) models for the boost PFC circuit. The EMI model presented can accurately predict noise levels into the 100's of kilohertz range. The thermal models presented provide very fast predictions and they have been adjusted to account for different thermal flows within the layout. This tuning procedure results in thermal predictions within 10% of actual measurement data. In order to further reduce the amount of analysis that the optimization tool must perform, some of the converter design has been performed using traditional methods. This part of the design is discussed in detail. Additionally, a per unit analysis of EMI and thermal levels is introduced. This new analysis method allows EMI and thermal levels to be compared on the same scale thus highlighting the tradeoffs between the both behaviors.
Master of Science

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13

Zientarski, Jonatan Rafael Rakoski. "Análise, modelagem e validação experimental de uma metodologia para o projeto do indutor em conversores Boost PFC." Universidade Federal de Santa Maria, 2009. http://repositorio.ufsm.br/handle/1/8464.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
This work presents the development of a methodology for design of inductor in singlephase PFC boost converters operating in CCM mode in agreement with international standards IEC 61000-3-2 and CISPR 22. Such converters are used in front-end modules of information technology equipment. This methodology is based on the investigation of the relationship among magnetic volume; switching frequency and input current ripple of the converter, presented in previous work and extended to allow the optimization of inductors with three magnetic materials: Kool Mμ, Molypermalloy and High-Flux. An analysis of some constructive characteristics of the inductors is performed, such as, magnetic materials and most appropriate type of winding, taking into account factors that can determine the lowest volume of the inductor, such as winding and magnetic losses, the flux density, and conducted electromagnetic interference (EMI). In construction of the inductors, it is discussed the use of single-layer winding, presenting their main haracteristics, advantages when seeking the reduction of conducted EMI, and considering the disadvantage of increasing of volume that this type winding may cause. An algorithm for this methodology is developed, that uses models able to estimate the differential mode conducted EMI for frequencies up to 30 MHz, as well the temperature rise of boost inductor by simulating the input current of the converter, considering soft saturation characteristics of magnetic materials and the use of commercial cores. Additionally, it is performed an experimental validation of the developed algorithm by construction of prototypes that uses three selected materials and operate at three different points of operation.
Este trabalho apresenta o desenvolvimento de uma metodologia de projeto do indutor em conversores boost PFC CCM monofásicos de acordo com as normas internacionais IEC 61000-3-2 e CISPR 22. Tais conversores são utilizados como estágio de entrada em fontes de equipamentos da tecnologia da informação. A metodologia é baseada na investigação da dependência existente entre o volume dos elementos magnéticos com a freqüência de comutação e a ondulação da corrente de entrada nestes conversores. O trabalho dá continuidade a trabalhos anteriores, ampliando a análise para a otimização de indutores de três materiais magnéticos: Kool Mμ, Molypermalloy e High-Flux. É realizada uma análise de algumas características construtivas destes indutores, entre elas, os materiais magnéticos mais apropriados e o tipo de enrolamento utilizado levando-se em consideração fatores que permitem a redução do volume do indutor, como as perdas magnéticas e nos enrolamentos, a densidade de fluxo magnético e a interferência eletromagnética (EMI) conduzida. Na implementação dos indutores, é discutida a utilização de enrolamentos de única camada, apresentando suas principais características, as vantagens de sua utilização quando se busca a redução da EMI conduzida, e considerando-se a desvantagem do aumento de volume do indutor que este tipo de enrolamento pode causar. Um algoritmo é desenvolvido para esta metodologia, no qual são utilizados modelos capazes de estimar a EMI conduzida DM para freqüências de até 30 MHz, assim como a elevação da temperatura do indutor, por meio de uma simulação da corrente de entrada do conversor que considera os efeitos da saturação suave dos materiais magnéticos e a utilização de núcleos com dimensões comerciais. É também realizada a validação experimental deste algoritmo, por meio da construção de protótipos que utilizam indutores dos três materiais escolhidos e operam em três pontos de operação distintos.

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Unal, Teoman. "Design Of A Single-phase Full-bridge Diode Rectifier Power Factor Corrector Educational Test System." Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/2/12608148/index.pdf.

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In this thesis an educational test bench for studying the power quality attributes of the commonly used single-phase full-bridge diode rectifiers with power factor correction (PFC) circuits is designed and tested. This thesis covers the active and passive power factor correction methods for single-phase bridge rectifier. Passive filtering approach with dc side inductor and tuned filter along with active filtering approach via singleswitch boost converter is considered. Analysis, simulation, and design of a single phase rectifier and PFC circuits is followed by hardware implementation and tests. In the active PFC approach, various control methods is applied and compared. The educational bench is aimed to useful for undergraduate and graduate power electronics course, power quality related laboratory studies.

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15

Pham, Thi Thuy Linh. "Contribution à l'étude de nouveaux convertisseurs sécurisés à tolérance de panne pour systèmes critiques à haute performance. Application à un PFC Double- Boost 5 Niveaux." Phd thesis, Institut National Polytechnique de Toulouse - INPT, 2011. http://tel.archives-ouvertes.fr/tel-00656620.

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Ce travail vise une exploration et une évaluation de nouvelles variantes de topologies multiniveaux AC/DC non réversibles (PFC) du point de vue de leur sûreté de fonctionnement : recherche d'une grande sécurité électrique sur destruction interne et maintien d'une continuité de fonctionnement. Elles sont caractérisées par une connexion AC non différentielle, un partitionnement cellulaire en série et symétrique autour d'un point milieu. Cette organisation permet d'exploiter la redondance active série entre les cellules d'un même groupe et l'effet de ségrégation topologique qui apparaît entre les deux groupes de cellules. Les structures étudiées sont modulaires et peuvent être parallélisées et étendues à un nombre quelconque de phases. Elles ne possèdent que des cellules mono-transistors basse-tension (Si et SiC 600V max) performantes et intrinsèquement tolérantes aux imperfections de la commande et aux parasites donc naturellement sécurisées. Les comparaisons prenant en compte les pertes, la répartition des pertes, le dimensionnement et le report de contraintes sur défaut interne mettent en avant la structure PFC Double- Boost Flying Cap. à 5 Niveaux, brevetée en début de thèse, comme une solution ayant le meilleur compromis. Sur le plan théorique nous montrons que le seul calcul de la fiabilité basé uniquement sur un critère d'occurrence au premier défaut est inadapté pour décrire ce type de topologie. La prise en compte de la tolérance de panne est nécessaire et permet d'évaluer la fiabilité globalement sur une panne effective (i.e. au second défaut). L'adaptation de modèles théoriques de fiabilité à taux de défaillance constant mais prenant en compte, au niveau de leurs paramètres, le report de contrainte en tension et l'augmentation de température qui résulte d'un premier défaut, permet de chiffrer par intégration et en valeur relative, le gain obtenu sur un temps court. Ce résultat est compatible avec les systèmes embarqués et la maintenance conditionnelle. Un prototype monophasé à 5 niveaux, à commande entièrement numérique et à MLI optimisée reconfigurable en temps réel a été réalisé afin de valider l'étude. Il permet une adaptation automatique de la topologie de 5 à 4 puis à 3 niveaux par exemple. Ce prototype a également servi de banc de test d'endurance du mode de défaillance sur claquage - avalanche de transistors CoolMos™ et diodes SiC, volontairement détruits individuellement dans des conditions d'énergie maîtrisée et reproductibles, afin de prouver expérimentalement le maintien du service sur plusieurs centaines d'heures au prix d'un derating de 30% maximum en puissance seulement. La détection et le diagnostic rapide de défauts internes ont également été traités dans ce travail. D'une part, par la surveillance directe et le seuillage des tensions internes (tensions flottantes) et d'autre part, par une détection harmonique de la fréquence de base (amplitude et phase) en temps réel. Ces deux techniques ont été intégrées numériquement et évaluées sur le prototype, en particulier la seconde qui ne requiert qu'un seul capteur. VI Enfin, nous proposons dans ce travail une nouvelle variante PFC Vienna multicellulaire expérimentée en fin de mémoire, utilisant deux fois moins de transistors et de drivers pour les mêmes performances fréquentielles au prix d'un rendement et d'une répartition des pertes légèrement moins favorables que la structure brevetée.

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Wu, Jia. "Implementation of a 100kW Soft-Switched DC Bus Regulator Based on Power Electronics Building Block Concept." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/32468.

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Power electronics building blocks (PEBBs) are standardized building blocks used to integrate power electronics systems. The PEBB approach can achieve low cost, high redundancy, high reliability, high flexibility and easy maintenance for large-scale power electronics systems. This thesis presents the implementation of a 100kW PEBB-based soft-switched bus regulator for an 800V DC distributed power system. The zero current transition (ZCT) soft-switching technique is used to improve the performance of the bus regulator by minimizing switching loss and improving overall efficiency. PEBB modules and a digital control building block are the subsystems of the DC bus regulator. This thesis addresses the design issues at subsystem and system levels. These include: operational principles and design of ZCT PEBB modules; design and implementation of the digital control block, based on DSP and EPLD; and modeling and control design of the DC bus regulator. There are several considerations when using the ZCT soft-switching technique in three-phase applications: the timing of the auxiliary switch gate signals must be arranged differently; there are low-frequency harmonics caused by the pulse width limits; and there is high thermal stress on the resonant capacitors. These issues are resolved by utilizing the sensed phase current information and the design freedom in the PWM modulator. A PWM modulation technique is proposed that can considerably reduce the switching events and further remove the associated loss while keeping THD low. Reduced switching events alleviate the thermal issue of the resonant capacitors. The same modulation technique can avoid the low-frequency harmonics caused by the pulse width limits and double the sampling frequency. The phase current information is used to deal with the control timing issue of the auxiliary switches and to control the three-phase soft-switching operation in order to achieve better efficiency. Additionally, the phase current information is used to implement dead time compensation to reduce THD. The soft-switched DC bus regulator has been tested up to a 100kW power level with 20kHz switching frequency. Experimental results demonstrate that high performance of the DC bus regulator is accomplished in terms of wide control bandwidth, low THD, unity power factor, high efficiency and high power density.
Master of Science

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17

Longo, Gaetano. "Analisi e simulazione di uno stadio power factor corrector per un alimentatore industriale." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017.

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Lo scopo è quello di migliorare l'assorbimento di rete di un alimentatore industriale, migliorandone fattore di potenza e distorsione armonica della corrente di rete. La tesi si concentra sull'analisi e la simulazione in Plecs di alcune tipologie di power factor corrector, in particolare: inverter trifase usato come raddrizzatore, filtro attivo e raddrizzatore Vienna. Per ogni soluzione sono state svolte simulazioni elettriche e termiche. Infine, vengono stimati i costi e i volumi di ogni PFC per fare un'analisi costi/benefici.

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18

Baisden, Andrew Carson. "Modeling and Characterization of Power Electronic Converters with an Integrated Transmission-Line Filter." Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/33188.

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In this work, a modeling approach is delineated and described in detail; predominantly done in the time domain from low frequency, DC, to high frequencies, 100 MHz. Commercially available computer aided design tools will be used to determine the propagation path in a given structure. Next, an integrated transmission-line filter â fabricated using planar processing technologies â is modeled to accurately predict the EMI characteristics of the system. A method was derived to model the filterâ s performance in the time-domain while accurately depicting the highly frequency dependant transmission-line properties. A system model of a power factor correction (PFC) boost converter was completed by using active device models for diodes, MOSFETs, and the gate driver. In addition, equivalent circuits were used to characterize high frequency impedances of the passive components. A PFC boost converter was built and used to validate the model. The PFC operated at a peak output power of 1 kW, switching at 400 kHz, with a universal input ranging from 90-270 VRMS with unity power factor. The time-domain and EMI frequency spectrum waveforms are experimentally measured and agree very well with the simulated values; within 5 dB for EMI. The transmission-line filter was also manufactured for model verification, and it is tested for the first time with an operating converter: a PFC at 50 W output and 50 VDC input. The small signal characteristics match the model very well. In addition, impedance interactions between the filter, the converter, and the EMI measurement set-up are discussed, evaluated, measured, and improved to minimize undesired resonances and increase low-frequency EMI attenuation. Experimentally measured attenuation provided by the filter in the range from 100 kHz to 100 MHz was 20-50 dBμV. The simulation also shows a similar attenuation, with the exception of one key resonance not seen in the simulation.
Master of Science

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19

Holub, Miroslav. "DC-DC měnič pro palubní dobíjení elektromobilu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-401968.

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This master thesis deals with design of DC-DC converter for onboard charging of electric vehicle. Developed converter will mainly be used for charging stationary traction battery in laboratory. Output voltage of this charger will be adjustable by user in between 200 V and 450 V depending on the current charged battery configuration. Output current limit is set at 8 A. Since the converter will be supplied from standard household socket, the problem of power factor correction must be solved during the design. That is because a large part of this thesis is focused on describing the problematics of power factor correction. After that, active PFC module is designed, completed and performance of this module is verified. To achieve low overall losses and thus be able to keep small volume of the system, modern switching components based on Silicon Carbide were preferred. Beside laboratory use, completed system will be used to emphasize volumetric difference between onboard chargers based on old versus modern switching components.

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Eleyele, Abidemi Oluremilekun. "Isolated Single-Stage Interleave Resonant PFC Rectifier with Active and Novel Passive Output Ripple Cancellation Circuit." Thesis, Uppsala universitet, Institutionen för elektroteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-423117.

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With the increasing demand for fast, cheaper, and efficient power converters come the need for a single-stage power factor correction (PFC) converter. Various single-stage PFC converter proposed in the literature has the drawback of high DC bus voltage at the input side and together with the shift to wide bandgap switches like GaN drives the converter cost higher. However, an interleaved topology with high-frequency isolation was proposed in this research work due to the drastic reduction in the DC bus voltage and extremely low input current ripple thereby making the need for an EMI filter circuit optional. Meanwhile, this research work focuses on adapting the proposed topology for a high voltage low current application (EV charger - 400V, 7KW) and low voltage high current application (telecom power supply - 58V, 58A) owing to cost benefits. However, all single-stage PFC are faced with the drawback of second-order (100Hz) output harmonic ripple. Therefore, the design and simulation presented a huge peak to peak ripple of about 50V/3A and 26V/26A for the EV charger and telecom power supply case, respectively. This created the need for the design of a ripple cancellation circuit as the research required a peak to peak ripple of 8V and 200mV for the EV - charger and telecom power supply, respectively. A novel output passive ripple cancellation technique was developed for the EV charger case due to the ease it offers in terms of control, circuit complexity and extremely low THDi when compared with the active cancellation approach. The ripple circuit reduced the 50V ripple to 431mV with the use of a total of 2.2mF capacitance at the output stage. Despite designing the passive technique, an active ripple cancellation circuit was designed using a buck converter circuit for the telecom power supply. The active approach was chosen because the passive has a slow response and incurs more loss at a high current level. Adding the active ripple cancellation circuit led to a quasi-single stage LLC PFC converter topology. A novel duty-ratio feedforward control was added to synchronize the PFC control of the input side with the buck topology ripple cancellation circuit. The addition of the ripple circuit with the feedforward control offered a peak to peak ripple of 6.7mV and a reduced resonant inductor current by half. After analysis, an extremely low THDi of 0.47%, PF of 99.99% and a peak efficiency of 97.1% was obtained for the EV charger case. The telecom power supply offered a THDi of 2.3%, PF of 99.96% with a peak efficiency of 95%.

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Reymond, Cédric. "Conception d'une structure innovante de convertisseur AC-DC de type Totem-pole avec correction du facteur de puissance : application aux chargeurs de batteries des véhicules électriques." Thesis, Tours, 2019. http://www.theses.fr/2019TOUR4015.

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Les gouvernements responsabilisent les états sur l’environnement avec la mise en œuvre de solution pour décarboner la production de l’électricité. En 2020, 20 % de l’énergie produite sera générée par les énergies renouvelables. Cependant ces énergies vertes sont intermittentes et nécessitent une capacité de stockage importante pour la gestion locale des « smart grids ». Cette solution pose deux nouvelles problématiques : la nécessité d’un convertisseur bidirectionnel et la gestion des courants d’appel. Pour faciliter l’étude de ces problématiques, la thèse propose de lier au travers d’un bilan de puissance, les performances des différents limiteurs de courant sur une topologie de convertisseur innovante. Cette analyse permet de mettre en exergue une solution alternative de limitation des courants d’appel dans la conversion de l’énergie. Enfin, un circuit novateur sur le contrôle des composants de puissance de type thyristors/Triacs sera proposé et caractérisé pour palier une des contraintes liées à la réversibilité du convertisseur
Governments empower states over the environment with implementation of solution to clean up the electricity production sources. In 2020, 20% of the produced energy will be generated by renewable energies. However, theses green energies are occasional and require a huge storage capacitance for the local smart grids management. This solution puts two new issues: the necessity of having a bidirectional converter and the inrush currents management. To facilitate the study of these problems, the thesis suggests binding through a power balance, the performances of the current limiter on an innovative topology converter. This analysis highlight an alternative solution of inrush current strategy in energy conversion. Finally, a novel control circuit for SCRs/Triacs components will be proposed and characterized for landing one of the constraints linked to the converter reversibility

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22

Ozturk, Salih Baris. "Direct torque control of permanent magnet synchronous motors with non-sinusoidal back-EMF." [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2728.

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23

Amarasinghe, Kanishka A. "Resonance mode power supplies with power factor correction." Thesis, Loughborough University, 1990. https://dspace.lboro.ac.uk/2134/23672.

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There is an increasing need for AC-DC converters to draw a pure sinusoidal current at near unity power factor from the AC mains. Most conventional power factor correcting systems employ PWM techniques to overcome the poor power factor being presented to the mains. However, the need for smaller and lighter power processing equipment has motivated the use of higher internal conversion frequencies in the past. In this context, resonant converters are becoming a viable alternative to the conventional PWM controlled power supplies. The thesis presents the implementation of active power factor correction in power supplies, using resonance mode techniques. It reviews the PWM power factor correction circuit topologies previously used. The possibility of converting these PWM topologies to resonant mode versions is discussed with a critical assessment as to the suitability of the semiconductor switching devices available today for deployment in these resonant mode supplies. The thesis also provides an overview of the methods used to model active semiconductor devices. The computer modelling is done using the PSpice microcomputer simulation program. The modifications that are needed to the built in MOSFET model in PSpice, when modeling high frequency circuits is discussed. A new two transistor model which replicates the action of a OTO thyristor is also presented. The new model enables the designer to estimate the device parameters with ease by adopting a short calculation and graphical design procedure, based on the manufacturer's data sheets. The need for a converter with a high efficiency, larger power/weight ratio, high input power factor with reduced line current distortion and reduced cost has led to the development of a new resonant mode converter topology, for power processing. The converter presents a near resistive load to the mains thus ensuring a high input power factor, while providing a stabilised de voltage at the output with a small lOOHz ripple. The supply is therefore ideal for preregulation applications. A description of the modes of operation and the analysis of the power circuit are included in the thesis. The possibility of using the converter for low output voltage applications is also discussed. The design of a 300W, 80kHz prototype model of this circuit is presented in the thesis. The design of the isolation transformer and other magnetic components are described in detail. The selection of circuit components and the design and implementation of the variable frequency control loop are also discussed. An evaluation of the experimental and computer simulated results obtained from the prototype model are included in the presentation. The thesis further presents a zero-current switching quasi-resonant flyback circuit topology with power factor correction. The reasons for using this topology for off-line power conversion applications are discussed. The use of a cascoded combination of a bipolar power transistor and two power MOSFETs i~ the configuration has enabled the circuit to process moderate levels of power while simultaneously switching at high frequencies. This fulfils the fundamental precondition for miniaturisation. It also provides a well regulated DC output voltage with a very small ripple while maintaining a high input power factor. The circuit is therefore ideal for use in mobile applications. A preliminary design of the above circuit, its analysis using PSpice, the design of the control circuit, current limiting and overcurrent protection circuitry and the implementation of closed-loop control are all included in the thesis. The experimental results obtained from a bread board model is also presented with an evaluation of the circuit performance. The power factor correction circuit is finally installed in this supply and the overall converter performance is assessed.

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24

Yeh, Thomas. "Analysis of power factor correction converters /." Online version of thesis, 1992. http://hdl.handle.net/1850/11220.

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Qian, Jinrong. "Advanced Single-Stage Power Factor Correction Techniques." Diss., Virginia Tech, 1997. http://hdl.handle.net/10919/30773.

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Five new single-stage power factor correction (PFC) techniques are developed for single-phase applications. These converters are: Integrated single-stage PFC converters, voltage source charge pump power factor correction (VS-CPPFC) converters, current source CPPFC converters, combined voltage source current source (VSCS) CPPFC converters, and continuous input current (CIC) CPPFC converters. Integrated single-stage PFC converters are first developed, which combine the PFC converter with a DC/DC converter into a single-stage converter. DC bus voltage stress at light load for the single-stage PFC converters are analyzed. DC bus voltage feedback concept is proposed to reduce the DC bus voltage stress at light load. The principle of operations of proposed converters are presented, implemented and evaluated. The experimental results verify the theoretical analysis. VS-CPPFC technique use a capacitor in series with a high frequency voltage source to achieve the PFC function. In this way, the input inductor is eliminated. VS-CPPFC AC/DC converters are developed, and their performance is evaluated. VS-CPPFC electronic ballasts with and without dimming function are also presented. The average lamp current control with duty ratio modulation is developed so that the lamp operates in constant power with a low crest factor over the line variation. The experimental results verify the CPPFC concept. CS-CPPFC technique employs a capacitor in parallel with a high frequency current source to obtain the PFC function. The unity power factor condition and principle of operation are analyzed. By doing so, the switch has less switching current stress, and deals only with the resonant inductor current. Design considerations and experimental results of the CS-CPPFC electronic ballast are presented. VSCS-CPPFC technique integrates the VS-CPPFC with the CS-CPPFC converters. The circuit derivation, unity power factor condition and design considerations are presented. The developed VSCS-CPPFC converters has constant lamp operation, low crest factor with a high power factor even without any feedback control. CIC-CPPFC technique is developed by inserting a small inductor in series with the line rectifier for the conceptual VS-CPPFC, CS-CPPFC and VSCS-CPPFC circuits. The circuit derivation and its unity power factor condition are discussed. The input current can be designed to be continuous, and a small line input filter can be used. The circulating current in the resonant tank and the switching current stress are minimized. The average lamp current control with switching frequency modulation is developed, so the developed electronic ballast operates in constant power, low crest factor. The developed CIC-CPPFC electronic ballast has features of low line input current harmonics, constant lamp power, low crest factor, continuous input current, low DC bus voltage stress, small circulating current and switching current stress over a wide range of line input voltage.
Ph. D.

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26

Jiang, Yimin. "Development of advanced power factor correction techniques." Diss., Virginia Polytechnic Institute and State University, 1994. http://hdl.handle.net/10919/53609.

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Three novel power factor correction (PFC) techniques are developed for both single-phase and three-phase applications. These techniques have advantages over the conventional approaches with regard to the converter efficiency, power density, cost, and reliability for many applications. The single-phase parallel PFC (PPFC) technique was established. Different from the conventional two-cascade-stage scheme, the PPFC technique allows 68% of input power to go to the output through only one time high frequency power conversion, but still achieves both unity power factor and tight output regulation. A family of PPFC converters were proposed for different power levels, which are simpler and more efficient than the conventional two-cascade-stage systems. Since isolated boost converters are adopted as the main power stage in some of the PPFC converters, a device based soft-switching technique was proposed for using IGBTs as the main power switches, which ensures the lower cost and higher efficiency benefits of the PPFC technique. The single-ended boost converter is the most frequently used converter in the single-phase PFC applications. For high power and/or high voltage applications, the major concerns of the conventional boost converter are the inductor volume and weight, and Iosses on the power devices, which will affect converter efficiency, power density, and cost. In this dissertation, a novel three-level boost converter was developed, which can use a much smaller inductor and lower voltage devices than the conventional one, yielding higher power density, higher efficiency, and lower cost. In three-phase applications, the three-phase boost rectifier is the most popular topology for the PFC purpose. A novel high performance boost PFC rectifier was developed, which provides several superior features than the conventional one with nearly no cost increase. lt inherently provides six-step PWM operation, which is the optimal PWM scheme with no circulating energy, minimum input ripple current, and minimum . switching events. It also greatly reduces the bridge diode reverse recovery loss, which is one of the major switching Iosses in the conventional three-phase boost rectifier. Furthermore, it can adopt very simple soft-switching techniques even with three independent analog controllers to further improve the performance. Several simple soft switched three-phase boost rectifiers have been developed. Besides, the bridge shoot-through problem is virtually eliminated. As a result, these new three-phase boost rectifiers have higher efficiency, higher power density, lower cost, and higher reliability compared with the conventional one.
Ph. D.

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27

Williams, David. "Active power decoupling for a boost power factor correction circuit." Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/59145.

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During AC-DC conversion, the ripple power at the input of the converter must be filtered from the output. This filtering can be easily done by placing a capacitor on the DC bus. For systems with power output of hundreds of Watts or more, this capacitor must be quite high to effectively perform the filtering, and in order to be cost effective, an aluminum electrolytic capacitor (Al e-caps) needs to be used. The lifespan of Al e-caps is notoriously short, so for long lifespan systems, their use is not advisable. Film capacitors have longer lifespans than Al e-caps but are more expensive on a cost per Farad basis. Methods have been proposed to reduce the required capacitance so that film capacitors can be cost effectively used. One of these methods is to use a separate decoupling port in the circuit that can filter the ripple power without the limitation of being connected directly to the DC bus. The first contribution is a method of using an active power decoupling (APD) port with a buck-based circuit that does not require direct measurement of the AC input signal for controlling the ripple power to the port. This APD port requires only two extra switches and some simple signal processing circuitry to generate a reference signal and control the voltage to the APD port capacitor. The second contribution is a design guide for a sliding mode control (SMC) system for the APD port. SMC shows promise as a control system for power electronics circuits and has never been demonstrated on an APD port before. The proposed circuit and control system is used in a 700 Watt AC-DC converter with power factor correction and is compared in simulation to a benchmark converter using a passive capacitor on the DC bus. The capacitance is reduced from 300μF to a 35μF and a 75μF capacitor without any effect on performance as indicated by measures of the voltage ripple, power factor and total harmonic distortion. The capacitance reduction results in a cost savings of $175 on capacitors when using prices that were current at time of publication.
Applied Science, Faculty of
Engineering, School of (Okanagan)
Graduate

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28

Niezrecki, Christopher. "Power factor correction and power consumption characterization of piezoelectric actuators." Thesis, Virginia Tech, 1992. http://hdl.handle.net/10919/42619.

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A piezoceramic actuator used for structural control behaves electrically as a nearly pure capacitance. When conventional amplifiers are used to drive these actuators, the current and voltage is close to 90 degrees out of phase. This causes the power factor (PF) of the load to be close to zero and results in excessive power requirements. This thesis reports the results of a study of the following question: What effect does applying power factor correction methods to piezoceramic actuators have on their power consumption characteristics? A subproblem we explored was to detennine the qualitative relationship between the power consumption of a piezoceramic actuator and the damping that actuator added to a structure. To address the subproblem, a feedback control experiment was built which used a ceramic piezoceramic actuator and a strain rate sensor configured to add damping to a cantilevered beam. A disturbance was provided by a shaker attached to the beam. The power consumption of the actuator was detennined by measuring the current and voltage of the signal to the actuator. The energy dissipated in the beam by the feedback control loop was assumed to be modeled by an ideal structural damping model. A model relating structural damping as a function of the apparent power consumed by the actuator was developed, qualitatively verified, and physically justified. Power factor correction methods were employed by adding an inductor in both parallel to and in series with the piezoceramic actuator. The inductance values were chosen such that each inductor-capacitor (LC) circuit was in resonance at the second natural frequency of the beam. Implementing the parallel LC circuit reduced the current consumption of the piezoceramic actuator by 75% when compared to the current consumption of the actuator used without an inductor. Implementing the series LC circuit produced a 300% increase in the voltage applied to the actuator compared to the case when no inductor was used. In both cases, employing power factor correction methods corrected the power factor to near unity and reduced the apparent power by 12 dB. A theoretical model of each circuit was developed. The analytical and empirical results are virtually identical. The results of this study can be used to synthesize circuits to modify piezoceramic actuators, reducing the voltage or current requirements of the amplifiers used to drive those actuators
Master of Science

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29

Zhang, Jindong. "Advanced Integrated Single-Stage Power Factor Correction Techniques." Diss., Virginia Tech, 2001. http://hdl.handle.net/10919/26480.

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This dissertation presents the in-depth study and innovative solutions of the advanced integrated single-stage power-factor-correction (S2PFC) techniques, which target at the low- to medium-level power supplies, for wide range of applications, from power adapters and computers to various communication equipment. To limit the undesirable power converter input-current-harmonicâ s impact on the power line and other electronics equipment, stringent current harmonic regulations such as IEC 61000-3-2 have already been enforced. The S2PFC techniques have been proposed and intensively studied, in order to comply these regulations with minimal additional component count and cost. This dissertation provides a systematic study of the S2PFC input-current-shaping (ICS) mechanism, circuit topology generalization and variation, bulk capacitor voltage stress and switch current stress, converter design and optimization, and evaluation of the state-of-the-art S2PFC techniques with universal-line input. Besides, this presentation also presents the development of novel S2PFC techniques with a voltage-doubler-rectifier front end to both improve the performance and reduce the cost of S2PFC converters for (international voltage range) universal-line applications. The calculation and experimental results show that the proposed techniques offer a more cost-effective and efficient solution than industriesâ current practice, with universal-line input and converter power level up to 600 W. Finally, further improved technique is also presented with reduced filter inductor size and increased power density.
Ph. D.

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30

Chan, Weng Hong. "Harmonic reduction and power factor correction in low power supply system." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1445817.

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31

Tan, Benjamin H. "A Novel Arc Welding Power Supply with Improved Power Factor Correction." DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2199.

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This paper presents the design and development of a novel Arc Welding Power Supply utilizing a modified two-switch forward converter topology. The proposed design improves the power quality by improving power factor to near unity and reducing total harmonic distortion. State space analysis of the proposed circuit showed that the circuit followed a boost-buck input output relationship. Simulation of the circuit was first implemented in LTspice to verify the functionality of the new topology. Hardware implementation of the proposed design was built on a scaled-down prototype for a proof-of-concept of the new topology. The prototype specifications were created for a 5A, 20V output with a 20-24V, 60Hz input. This project demonstrated that the proposed new topology was successful in obtaining a near unity power factor and a total harmonic distortion of less than 2%. Additionally, the prototype followed the simulation and calculations of a boost-buck function while varying duty cycle, and the final measurements aligned well with waveforms from the simulation.

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32

Saasaa, Raed. "A single-stage interleaved resonant power factor correction converter." Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/59199.

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Applications requiring DC voltages vary widely, from low power, such as LED lighting, to high power, as in industrial motor drives and battery chargers. Accordingly, a unified power architecture for all applications is not practical for efficiency, size and cost optimization. The use of LED lighting system became popular due to its many advantages. The new outdoor applications such as street and flood lighting require high power (i.e. >200 W) in contrast to the low power existing LED drivers. Generally, the conventional architecture of AC/DC converters consists of two main stages; The first is current-shaping stage to improve PF and the second is to provide isolation and tight regulation over the output voltage. Recently, the research on AC/DC converters has focused on optimizing the converter design to be more reliable and efficient for low and medium power applications. Specifically, techniques have been proposed to eliminate the DC output bus electrolytic capacitor by introducing auxiliary DC/DC converter. On the other hand, the integrated converters were deployed by many researchers to decrease the number of switches, facilitate the controller design, and improve the efficiency. This thesis presents a novel single-stage AC/DC converter that can achieve high power factor with reduced switching losses for semiconductor devices. The topology is derived by integrating the interleaved boost-type PFC and full bridge LLC resonant converters. Due to interleaving at the input, the converter exhibits less input current ripple compared to the existing topologies. Therefore, it is suitable for applications up to approximately 500 W. A detailed analysis of the operation modes is presented. Also, a 350–W prototype is designed to verify the effectiveness of the topology.
Applied Science, Faculty of
Engineering, School of (Okanagan)
Graduate

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33

George, Mark S. "Power factor correction using a boost quasi-resonant converter." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41901.

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A steady-state analysis of a quasi-resonant zero current boost converter is performed in its application to a single-phase power factor correction circuit. The known closed-form expressions are used to design the boost converter and the multiloop control circuit. The operating characteristics are simulated by using PSPICE and are experimentally verified. Considerations for a practical design are based upon hardware operating at a maximum of 1 megahertz, with a 115 VRMS input, 200 VDC and 100 watt output.

Master of Science

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34

Clark, Colin William. "Digital control techniques for power quality improvements in power factor correction applications." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/42799.

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The prevalence of standards and recommended practices to meet harmonic current limits has gained, and continues to gain, momentum over recent years. To meet these requirements, power electronic rectification devices are necessitated along with their specialized control techniques. A popular power electronic circuit to obtain low-harmonic input current is the boost power factor correction (PFC) converter, and with the advent of digital control, powerful control techniques to meet these harmonic current limits are possible. The first contribution is a detailed guide to the conversion of an analog IC-controlled boost PFC converter to a digitally controlled equivalent. Design of the voltage and current sensing networks, compensator, overview of the critical interrupt service routines, and the control implementation in a digital signal processor (DSP) is presented. The existing boost PFC converter modified for digital control is successful, and provides a flexible prototyping test bench for further use. The second contribution is a novel DSP-based discontinuous conduction mode (DCM) detection method for application to the boost PFC converter. The proposed detection method is computationally simple, and requires little or no modification to existing digitally controlled boost PFC converters using DSPs with on-board comparators. An experimental boost PFC converter verifies the effectiveness of the proposed detection method over traditional zero current detection and DCM detection techniques, enabling advanced control techniques for power quality improvements. The final contribution is a new adaptive mixed conduction mode (MCM) control technique for the boost PFC converter. This MCM control technique applies the proposed DSP-based DCM detection method to realize higher power factor and decreased total harmonic distortion (THD) over a commercially available analog controller and a conventional digital controller. Using a boost PFC converter operating in MCM with the proposed adaptive control method, THD improvements of up to 4.55% at light loads and power factor improvements of up to 17.4% are provided over the analog and conventional digital controller.

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35

Barbosa, Peter Mantovanelli. "Three-Phase Power Factor Correction Circuits for Low-Cost Distributed Power Systems." Diss., Virginia Tech, 2002. http://hdl.handle.net/10919/28651.

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Front-end converters with power factor correction (PFC) capability are widely used in distributed power systems (DPSs). Most of the front-end converters are implemented using a two-stage approach, which consists of a PFC stage followed by a DC/DC converter. The purpose of the front-end converter is to regulate the DC output voltage, supply all the load converters connected to the distributed bus, guarantee current sharing, and charge a bank of batteries to provide backup energy when the power grid breaks down. One of the main concerns of the power supply industry is to obtain a front-end converter with a low-cost PFC stage, while still complying with required harmonic standards, especially for high-power three-phase applications. Having this statement in mind, the main objective of this dissertation is to study front-end converters for DPS applications with PFC to meet harmonic standards, while still maintaining low cost and performance indices. To realize the many aforementioned objectives, this dissertation is divided into two main parts: (1) two-stage front-end converters suitable for telecom applications, and (2) single-stage low-cost AC/DC converters suitable for mainframe computers and server applications. The use of discontinuous conduction mode (DCM) boost rectifiers is extensively explored to achieve simplicity, while reducing the cost for DPS applications. Interleaving of DCM boost rectifiers is also explored as an alternative approach to further reduce the system cost by reducing the filtering requirements. All the solutions discussed are implemented for 3kW applications, while 6kW is obtained by interleaving two converters.
Ph. D.

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36

Ahmed, Saeed. "Controlled on-time power factor correction circuit with input filter." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11072008-063637/.

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37

Kalpaktsoglou, Dimitrios. "Power factor correction for stand-alone wave energy conversion buoys." Thesis, University of Newcastle Upon Tyne, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.519591.

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38

Zhang, Jindong. "Study and Improvement of Single-Stage Power Factor Correction Techniques." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/36938.

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This thesis work focuses on the study and improvement of single-stage power factor correction techniques. The generalized structures of the present pulse-width-modulation (PWM) integrated single-stage power factor correction (PFC) converters are presented. The typical PFC cells in the single-stage PFC converter are identified. After that, the necessary PFC condition is derived and verified to understand the principle of the single-stage PFC converters. As an example, the continuous current mode (CCM) current source single-stage PFC converter is studied. The circuit intuitions and design consideration of this converter are presented. Also, an improved current source single-stage PFC converter with a low-frequency auxiliary switch is proposed to overcome the problem of the previous converter. Experimental verification shows the improvement is effective. To evaluate single-stage PFC technique, a comparison study between the current source single-stage and the boost two-stage PFC converters is done in this thesis. It shows that for universal line application, due to the wide bus-capacitor voltage range, single-stage PFC converters have higher component ratings than two-stage PFC converters. This limits the application of single-stage PFC converter. Therefore, an interesting future work will be how to reduce the bus voltage range of single-stage PFC converters.
Master of Science

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39

Zhou, Chen. "Design and analysis of an active power factor correction circuit." Thesis, Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/53729.

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The design of an active-unity power factor correction circuit with variable-hysteresis control for off-line dc-to-dc switching power supplies is described. Design equations relating the boost inductor current ripple to the circuit components selection and circuit performance arc discussed. A computer-aided design program (CADO) is developed to give the optimal circuit components selection. A 500 watt, 300 volt experimental circuit is built to verify the simulation and analysis results. The control-to-output response of the power factor circuit is verified with the experimental results. Design guidelines for the low-frequency feedback network are presented. Small-signal closed-loop responses are measured with an experimental power factor circuit.
Master of Science

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40

Lord, Edward Michael. "Single-stage power factor correction converter topologies for low power off-line applications." Thesis, University of Edinburgh, 2004. http://hdl.handle.net/1842/15234.

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Since January 2001 it has been necessary for equipment connected to the low voltage public distribution network in Europe and Japan to comply with IEC 61000-3-2. The regulation IEC 61000-3-2 specifies the level of current that can be drawn for particular harmonics. Much equipment today is fitted with a Switch Mode Power Supply (SMPS) at its input to interface between the line voltage and internal low voltage electronics. This SMPS must not only convert the line voltage, but also ensure that the input current to the device meets the IEC regulations. To meet these regulations two methods are normally used, passive filtering using a large filter inductor or a boost converter cascaded with the main DC/DC SMPS converter with isolation. To try and reduce component count, cost and increase efficiency many new single-stage Power Factor Correction (PFC) topologies have been proposed. In a single-stage topology the output voltage regulation and meeting IEC 61000-3-2 are combined into a single power stage. Unfortunately very little is known about the behaviour or performance of these single-stage topologies. In this thesis two of the more promising single-stage topologies, the bi-forward and CS S²PFC converters are investigated further. A new topology using a low frequency switch (LFSPFC) is introduced. The topologies are analysed investigating input current shape and harmonic content, voltage variation on bulk capacitance and component stresses. Simulation in PSpice is used to confirm circuit operation. Four 150W output power experimental circuits were built: bi-forward converter, CS S2PFC converter, passive filtering cascaded with a forward converter and a boost pre-regulator cascaded with a forward converter. The converters operate from universal input voltage and have outputs at 5V and 12V. A 100W test circuit was built for the LFSPFC operating from 230V input voltage and with an output of 5V. Experimental results are presented showing circuit behaviour and performance of the bi-forward, CS S²PFC and LFSPFC converters. The bi-forward and CS S²PFC converters are compared to the passive filter and boost converter cascaded with a forward converter. It is demonstrated that neither of these single-stage topologies is at present a viable replacement for either present method, but the LFSPFC could be a lighter weight and less bulky alternative to passive filtering.

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41

Zhao, Yiqing. "Single Phase Power Factor Correction Circuit with Wide Output Voltage Range." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/35764.

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The conventional power factor correction circuit has a fixed output voltage. However, in some applications, a PFC circuit with a wide output voltage range is needed. A single phase power factor correction circuit with wide output voltage range is developed in this work. After a comparison of two main power stage candidates (Buck+Boost and Sepic) in terms of efficiency, complexity, cost and device rating, the buck+boost converter is employed as the variable output PFC power stage. From the loss analysis, this topology has a high efficiency from light load to heavy load. The control system of the variable output PFC circuit is analyzed and designed. Charge average current sensing scheme has been adopted to sense the input current. The problem of high input harmonic currents at low output voltage is discussed. It is found that the current loop gain and cross over frequency will change greatly when the output voltage changes. To solve this problem, an automatic gain control scheme is proposed and a detailed circuit is designed and added to the current loop. A modified input current sensing scheme is presented to overcome the problem of an insufficient phase margin of the PFC circuit near the maximum output voltage. The charge average current sensing circuit will be bypassed automatically by a logical circuit when the output voltage is higher than the peak line voltage. Instead, a resistor is used to sense the input current at that condition. Therefore, the phase delay caused by the charge average current sensing circuit is avoided. The design and analysis are based on a novel air conditioner motor system application. Some detailed design issues are discussed. The experimental results show that the variable output PFC circuit has good performance in the wide output voltage range, under both the Boost mode when the output voltage is high and the Buck+Boost mode when the output voltage is low.
Master of Science

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42

Durrani, Yamin Qaisar. "Analysis of silicon carbide based semiconductor power devices and their application in power factor correction." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2573.

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Recent technological advances have allowed silicon (Si) semiconductor technology to approach the theoretical limits of the Si material; however, power device requirements for many applications are at a stage that the present Si-based power devices cannot handle. The requirements include higher blocking voltages, switching frequencies, efficiency, and reliability. Material technologies superior to Si are needed for future power device developments. Silicon Carbide (SiC) based semiconductor devices offer one such alternative. SiC based power devices exhibit superior properties such as very low switching losses, fast switching behavior, improved reliability and high temperature operation capabilities. Power factor correction stage of power supplies is identified as an area where application of these devices would prove advantageous. In this thesis a high performance, high efficiency, SiC based power factor correction stage is discussed. The proposed topology takes advantage of the superior properties of SiC semiconductor based devices and the reduced number of devices that the dual boost power factor correction topology requires to achieve high efficiency, small size and better performance at high temperature. In addition to this analysis of SiC based power devices is carried out to study their characteristics and performance.

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43

Chen, Chuen-Shiu, and 陳春旭. "The design of zero-voltage-transition(ZVT) power factor correction(PFC) circuit." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/16706264659421257343.

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44

Xu, Xiaojun. "Next generation power factor correction (PFC) based on silicon carbide (SiC) power devices and new control strategy." 2008. http://www.lib.ncsu.edu/theses/available/etd-11262008-173420/unrestricted/etd.pdf.

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45

Chen, Chi-Lin, and 陳契霖. "Triple Loop Modulation (TLM) for High Reliability and Efficiency in Power Factor Correction (PFC) System." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/85164771988645998761.

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博士
國立交通大學
電控工程研究所
100
In general power applications, the power factor correction techniques is the one of key techniques in power saving applications and can make AC power more efficient. The PFC has slow system response because it has low one third or one sixth bandwidth smaller than 20 Hz. The low bandwidth is designed to reject AC interference of 60Hz coupling which could deteriorate system reliability in case of output load transient. This dissertation proposes the triple loop modulation (TLM) in PFC system to improve as fast transient response. When system is in steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by TLM. When output loading changes, the TLM can automatically adjust the bandwidth to increase or decrease inductor current rapidly and reduce transient response time. The mathematical analysis is deduced. This PFC chip is fabricated in VIS 0.5um 500V/40V ultra high voltage LDMOS process. Measurement results show that this PFC system with TLM in transient response is twofold faster than conventional PFC design with output load variation from 20W to 90W and the undershoot voltage is half of traditional PFC. When loading changes from 20W to 90W, the PFC with TLM in transient response is twofold faster than conventional PFC design and the overshoot voltage is about half of traditional PFC.

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46

"Accurate Estimation of Core Losses for PFC Inductors." Master's thesis, 2019. http://hdl.handle.net/2286/R.I.55521.

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abstract: As the world becomes more electronic, power electronics designers have continuously designed more efficient converters. However, with the rising number of nonlinear loads (i.e. electronics) attached to the grid, power quality concerns, and emerging legislation, converters that intake alternating current (AC) and output direct current (DC) known as rectifiers are increasingly implementing power factor correction (PFC) by controlling the input current. For a properly designed PFC-stage inductor, the major design goals include exceeding minimum inductance, remaining below the saturation flux density, high power density, and high efficiency. In meeting these goals, loss calculation is critical in evaluating designs. This input current from PFC circuitry leads to a DC bias through the filter inductor that makes accurate core loss estimation exceedingly difficult as most modern loss estimation techniques neglect the effects of a DC bias. This thesis explores prior loss estimation and design methods, investigates finite element analysis (FEA) design tools, and builds a magnetics test bed setup to empirically determine a magnetic core’s loss under any electrical excitation. In the end, the magnetics test bed hardware results are compared and future work needed to improve the test bed is outlined.
Dissertation/Thesis
Masters Thesis Electrical Engineering 2019

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47

Brolund, Andreas. "Evaluation of power quality and common design concept for AC-DC converters in aircraft." Thesis, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-337969.

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This master thesis has been carried out in collaboration with Saab, Avionics Systems in Jönköping, Sweden, during the spring of 2017. The thesis investigates unidirectional rectifier topologies in aircraft and the focus has been on evaluating the power quality requirements according to the aircraft standards, in the course of the More Electric Aircraft concept. Both passive and active power factor correction topologies are considered, discussed and compared. Simulation models are designed in MATLAB/Simulink and the procedures are presented. A modular concept regarding components is discussed where different power supplies and loads are considered. The simulations present both a passive 12-pulse auto-transformer rectifier unit and an active Delta-switch rectifier fulfilling requirements for aircraft such as the total harmonic distortion of the supply current. In addition, the input power factor is close to unity and an efficiency greater than 97% is obtained. Lastly, future aspects of each topology are discussed and necessary improvements to obtain realistic simulation models are presented.

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48

Gau, Yu-Jun, and 高鈺鈞. "Low Cost Simple Power Factor Correction." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/5uw96v.

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碩士
遠東科技大學
電機工程研究所
107
This thesis proposes a low-cost simple power factor correction converter architecture. Since the commercially available power factor correctors are upgraded to 400V without lower voltage, considering the low-voltage equipment can be used, it is proposed to achieve high-efficiency circuits at low cost. This article uses the IC ICE2PCS02 in continuous conduction mode as the correction IC for this power factor corrector. This circuit simulates the boost converter simulation in the case of input 70-130Vac boost to output 200V for three different load cases. At half load, the efficiency can reach 94-95% or more. When it is fully loaded, its efficiency can reach 98-99%, effectively achieving a low-cost and high-efficiency structure.

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49

Fan, Yang-Dian, and 范揚典. "Comparator Implemented Digital Power Factor Correction Rectifier." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/fe7tu6.

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碩士
國立高雄科技大學
電機工程系
107
Power factor correction rectifier (PFC) is the front end of most computer power supplies. Due to the climate change, high efficiency over wide load range is highly demanded in PFCs. This drives digital controller to replace analog controller. Analog to digital converters (ADC) are the essential parts for all digital powers. Some previous researches replace the ADC with a comparator and a counter for measuring the DC value of a rippled signal. Comparator based control does not only reduces system cost, but also eliminates the sampling error of the ADC. For those signals with small ripple, the comparator based digital controller injects extra analog ripple on signal feedback for signal sensing. However, in digital PFC, system operation point varies along the line voltage. The fixed analog ripple injection can only be optimized for one operating point. Therefore, a digital ripple injection is introduced in this paper. Instead of using analog circuits to generate analog ripple, a digital to analog converter (DAC) and a low pass filter can generate filtered digital ripple signal as the ripple inject. Based on digital ripple injection, a 500 watt digital PFC is implemented experimentally.

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50

Huang, Kuan-Ju, and 黃冠儒. "Development of a Digital Meter with Power Factor Correction Correction Capability." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/d8q927.

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碩士
國立臺北科技大學
自動化科技研究所
105
The thesis proposed a digital meter with power factor correction capability when the measured signal contains harmonic components. By using resistor voltage divider circuit and current clamp, the input voltage and current are transferred to small voltage signals which can be processed by the microprocessor. These voltage and current waveform are digitized through an analog-to-digital convertor (ADC). Fast Fourier Transform (FFT) is applied. The Hanning Window and frequency interpolation algorithm is used to correct the voltage and current signals. As the front-end circuit may introduce phase shift, phase compensation calculation is required. Accurate RMS voltage, RMS current, active power, reactive power, apparent power, power factor and frequency can be calculated. When measured signal contains harmonic components, the THD is calculated and is used to correct the power factor calculation. The final measurement results are displayed on the LCD and transmitted through the UART. Calibration procedure is also developed to simplify the calibration process. All of the calibration parameters are stored in nonvolatile memory.

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Dissertations / Theses on the topic 'Power Factor Correction (PFC)'

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