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1
Amarasinghe, Kanishka A. "Resonance mode power supplies with power factor correction." Thesis, Loughborough University, 1990. https://dspace.lboro.ac.uk/2134/23672.
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There is an increasing need for AC-DC converters to draw a pure sinusoidal current at near unity power factor from the AC mains. Most conventional power factor correcting systems employ PWM techniques to overcome the poor power factor being presented to the mains. However, the need for smaller and lighter power processing equipment has motivated the use of higher internal conversion frequencies in the past. In this context, resonant converters are becoming a viable alternative to the conventional PWM controlled power supplies. The thesis presents the implementation of active power factor correction in power supplies, using resonance mode techniques. It reviews the PWM power factor correction circuit topologies previously used. The possibility of converting these PWM topologies to resonant mode versions is discussed with a critical assessment as to the suitability of the semiconductor switching devices available today for deployment in these resonant mode supplies. The thesis also provides an overview of the methods used to model active semiconductor devices. The computer modelling is done using the PSpice microcomputer simulation program. The modifications that are needed to the built in MOSFET model in PSpice, when modeling high frequency circuits is discussed. A new two transistor model which replicates the action of a OTO thyristor is also presented. The new model enables the designer to estimate the device parameters with ease by adopting a short calculation and graphical design procedure, based on the manufacturer's data sheets. The need for a converter with a high efficiency, larger power/weight ratio, high input power factor with reduced line current distortion and reduced cost has led to the development of a new resonant mode converter topology, for power processing. The converter presents a near resistive load to the mains thus ensuring a high input power factor, while providing a stabilised de voltage at the output with a small lOOHz ripple. The supply is therefore ideal for preregulation applications. A description of the modes of operation and the analysis of the power circuit are included in the thesis. The possibility of using the converter for low output voltage applications is also discussed. The design of a 300W, 80kHz prototype model of this circuit is presented in the thesis. The design of the isolation transformer and other magnetic components are described in detail. The selection of circuit components and the design and implementation of the variable frequency control loop are also discussed. An evaluation of the experimental and computer simulated results obtained from the prototype model are included in the presentation. The thesis further presents a zero-current switching quasi-resonant flyback circuit topology with power factor correction. The reasons for using this topology for off-line power conversion applications are discussed. The use of a cascoded combination of a bipolar power transistor and two power MOSFETs i~ the configuration has enabled the circuit to process moderate levels of power while simultaneously switching at high frequencies. This fulfils the fundamental precondition for miniaturisation. It also provides a well regulated DC output voltage with a very small ripple while maintaining a high input power factor. The circuit is therefore ideal for use in mobile applications. A preliminary design of the above circuit, its analysis using PSpice, the design of the control circuit, current limiting and overcurrent protection circuitry and the implementation of closed-loop control are all included in the thesis. The experimental results obtained from a bread board model is also presented with an evaluation of the circuit performance. The power factor correction circuit is finally installed in this supply and the overall converter performance is assessed.
2
Xie, Manjing. "Digital Control for Power Factor Correction." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34258.
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This thesis focuses on the study, implementation and improvement of a digital controller for a power factor correction (PFC) converter.
The development of the telecommunications industry and the Internet demands reliable, cost-effective and intelligent power. Nowadays, the telecommunication power systems have output current of up to several kilo amperes, consisting of tens of modules. The high-end server system, which holds over 100 CPUs, consumes tens of kilowatts of power. For mission-critical applications, communication between modules and system controllers is critical for reliability. Information about temperature, current, and the total harmonic distortion (THD) of each module will enable the availability of functions such as dynamic temperature control, fault diagnosis and removal, and adaptive control, and will enhance functions such as current sharing and fault protection. The dominance of analog control at the modular level limits system-module communications. Digital control is well recognized for its communication ability. Digital control will provide the solution to system-module communication for the DC power supply.
The PFC converter is an important stage for the distributed power system (DPS). Its controller is among the most complex with its three-loop structure and multiplier/divider. This thesis studies the design method, implementation and cost effectiveness of digital control for both a PFC converter and for an advanced PFC converter. Also discussed is the influence of digital delay on PFC performance. A cost-effective solution that achieves good performance is provided. The effectiveness of the solution is verified by simulation.
The three level PFC with range switch is well recognized for its high efficiency. The range switch changes the circuit topology according to the input voltage level. Research literature has discussed the optimal control for both range-switch-off and range-switch-on topologies. Realizing optimal analog control requires a complex structure. Until now optimal control for the three-level PFC with analog control has not been achieved. Another disadvantage of the three-level PFC is the output capacitor voltage imbalance. This thesis proposes an active balancing solution to solve this problem.Master of Science
3
Yeh, Thomas. "Analysis of power factor correction converters /." Online version of thesis, 1992. http://hdl.handle.net/1850/11220.
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4
Qian, Jinrong. "Advanced Single-Stage Power Factor Correction Techniques." Diss., Virginia Tech, 1997. http://hdl.handle.net/10919/30773.
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Five new single-stage power factor correction (PFC) techniques are developed for single-phase applications. These converters are: Integrated single-stage PFC converters, voltage source charge pump power factor correction (VS-CPPFC) converters, current source CPPFC converters, combined voltage source current source (VSCS) CPPFC converters, and continuous input current (CIC) CPPFC converters.
Integrated single-stage PFC converters are first developed, which combine the PFC converter with a DC/DC converter into a single-stage converter. DC bus voltage stress at light load for the single-stage PFC converters are analyzed. DC bus voltage feedback concept is proposed to reduce the DC bus voltage stress at light load. The principle of operations of proposed converters are presented, implemented and evaluated. The experimental results verify the theoretical analysis.
VS-CPPFC technique use a capacitor in series with a high frequency voltage source to achieve the PFC function. In this way, the input inductor is eliminated. VS-CPPFC AC/DC converters are developed, and their performance is evaluated. VS-CPPFC electronic ballasts with and without dimming function are also presented. The average lamp current control with duty ratio modulation is developed so that the lamp operates in constant power with a low crest factor over the line variation. The experimental results verify the CPPFC concept.
CS-CPPFC technique employs a capacitor in parallel with a high frequency current source to obtain the PFC function. The unity power factor condition and principle of operation are analyzed. By doing so, the switch has less switching current stress, and deals only with the resonant inductor current. Design considerations and experimental results of the CS-CPPFC electronic ballast are presented.
VSCS-CPPFC technique integrates the VS-CPPFC with the CS-CPPFC converters. The circuit derivation, unity power factor condition and design considerations are presented. The developed VSCS-CPPFC converters has constant lamp operation, low crest factor with a high power factor even without any feedback control.
CIC-CPPFC technique is developed by inserting a small inductor in series with the line rectifier for the conceptual VS-CPPFC, CS-CPPFC and VSCS-CPPFC circuits. The circuit derivation and its unity power factor condition are discussed. The input current can be designed to be continuous, and a small line input filter can be used. The circulating current in the resonant tank and the switching current stress are minimized. The average lamp current control with switching frequency modulation is developed, so the developed electronic ballast operates in constant power, low crest factor. The developed CIC-CPPFC electronic ballast has features of low line input current harmonics, constant lamp power, low crest factor, continuous input current, low DC bus voltage stress, small circulating current and switching current stress over a wide range of line input voltage.Ph. D.
5
Jiang, Yimin. "Development of advanced power factor correction techniques." Diss., Virginia Polytechnic Institute and State University, 1994. http://hdl.handle.net/10919/53609.
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Three novel power factor correction (PFC) techniques are developed for both single-phase and three-phase applications. These techniques have advantages over the conventional approaches with regard to the converter efficiency, power density, cost, and reliability for many applications.
The single-phase parallel PFC (PPFC) technique was established. Different from the conventional two-cascade-stage scheme, the PPFC technique allows 68% of input power to go to the output through only one time high frequency power conversion, but still achieves both unity power factor and tight output regulation. A family of PPFC converters were proposed for different power levels, which are simpler and more efficient than the conventional two-cascade-stage systems. Since isolated boost converters are adopted as the main power stage in some of the PPFC converters, a device based soft-switching technique was proposed for using IGBTs as the main power switches, which ensures the lower cost and higher efficiency benefits of the PPFC technique.
The single-ended boost converter is the most frequently used converter in the single-phase PFC applications. For high power and/or high voltage applications, the major concerns of the conventional boost converter are the inductor volume and weight, and Iosses on the power devices, which will affect converter efficiency, power density, and cost. In this dissertation, a novel three-level boost converter was developed, which can use a much smaller inductor and lower voltage devices than the conventional one, yielding higher power density, higher efficiency, and lower cost.
In three-phase applications, the three-phase boost rectifier is the most popular topology for the PFC purpose. A novel high performance boost PFC rectifier was developed, which provides several superior features than the conventional one with nearly no cost increase. lt inherently provides six-step PWM operation, which is the optimal PWM scheme with no circulating energy, minimum input ripple current, and minimum . switching events. It also greatly reduces the bridge diode reverse recovery loss, which is one of the major switching Iosses in the conventional three-phase boost rectifier. Furthermore, it can adopt very simple soft-switching techniques even with three independent analog controllers to further improve the performance. Several simple soft switched three-phase boost rectifiers have been developed. Besides, the bridge shoot-through problem is virtually eliminated. As a result, these new three-phase boost rectifiers have higher efficiency, higher power density, lower cost, and higher reliability compared with the conventional one.Ph. D.
6
Anand, Aniket. "Power factor correction in switched reluctance motor drives." Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8125.
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Williams, David. "Active power decoupling for a boost power factor correction circuit." Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/59145.
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During AC-DC conversion, the ripple power at the input of the converter must be filtered from the output. This filtering can be easily done by placing a capacitor on the DC bus. For systems with power output of hundreds of Watts or more, this capacitor must be quite high to effectively perform the filtering, and in order to be cost effective, an aluminum electrolytic capacitor (Al e-caps) needs to be used. The lifespan of Al e-caps is notoriously short, so for long lifespan systems, their use is not advisable. Film capacitors have longer lifespans than Al e-caps but are more expensive on a cost per Farad basis. Methods have been proposed to reduce the required capacitance so that film capacitors can be cost effectively used. One of these methods is to use a separate decoupling port in the circuit that can filter the ripple power without the limitation of being connected directly to the DC bus. The first contribution is a method of using an active power decoupling (APD) port with a buck-based circuit that does not require direct measurement of the AC input signal for controlling the ripple power to the port. This APD port requires only two extra switches and some simple signal processing circuitry to generate a reference signal and control the voltage to the APD port capacitor. The second contribution is a design guide for a sliding mode control (SMC) system for the APD port. SMC shows promise as a control system for power electronics circuits and has never been demonstrated on an APD port before. The proposed circuit and control system is used in a 700 Watt AC-DC converter with power factor correction and is compared in simulation to a benchmark converter using a passive capacitor on the DC bus. The capacitance is reduced from 300μF to a 35μF and a 75μF capacitor without any effect on performance as indicated by measures of the voltage ripple, power factor and total harmonic distortion. The capacitance reduction results in a cost savings of $175 on capacitors when using prices that were current at time of publication.Applied Science, Faculty of
Engineering, School of (Okanagan)
Graduate
8
Niezrecki, Christopher. "Power factor correction and power consumption characterization of piezoelectric actuators." Thesis, Virginia Tech, 1992. http://hdl.handle.net/10919/42619.
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A piezoceramic actuator used for structural control behaves electrically as a nearly pure capacitance. When conventional amplifiers are used to drive these actuators, the current and voltage is close to 90 degrees out of phase. This causes the power factor (PF) of the load to be close to zero and results in excessive power requirements. This thesis reports the results of a study of the following question: What effect does applying power factor correction methods to piezoceramic actuators have on their power consumption characteristics? A subproblem we explored was to detennine the qualitative relationship between the power consumption of a piezoceramic actuator and the damping that actuator added to a structure.
To address the subproblem, a feedback control experiment was built which used a ceramic piezoceramic actuator and a strain rate sensor configured to add damping to a cantilevered beam. A disturbance was provided by a shaker attached to the beam. The power consumption of the actuator was detennined by measuring the current and voltage of the signal to the actuator. The energy dissipated in the beam by the feedback control loop was assumed to be modeled by an ideal structural damping model. A model relating structural damping as a function of the apparent power consumed by the actuator was developed, qualitatively verified, and physically justified.
Power factor correction methods were employed by adding an inductor in both parallel to and in series with the piezoceramic actuator. The inductance values were chosen such that each inductor-capacitor (LC) circuit was in resonance at the second natural frequency of the beam.
Implementing the parallel LC circuit reduced the current consumption of the piezoceramic actuator by 75% when compared to the current consumption of the actuator used without an inductor. Implementing the series LC circuit produced a 300% increase in the voltage applied to the actuator compared to the case when no inductor was used. In both cases, employing power factor correction methods corrected the power factor to near unity and reduced the apparent power by 12 dB. A theoretical model of each circuit was developed.
The analytical and empirical results are virtually identical. The results of this study can be used to synthesize circuits to modify piezoceramic actuators, reducing the voltage or current requirements of the amplifiers used to drive those actuatorsMaster of Science
9
Zhang, Jindong. "Advanced Integrated Single-Stage Power Factor Correction Techniques." Diss., Virginia Tech, 2001. http://hdl.handle.net/10919/26480.
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This dissertation presents the in-depth study and innovative solutions of the advanced integrated single-stage power-factor-correction (S2PFC) techniques, which target at the low- to medium-level power supplies, for wide range of applications, from power adapters and computers to various communication equipment.
To limit the undesirable power converter input-current-harmonicâ s impact on the power line and other electronics equipment, stringent current harmonic regulations such as IEC 61000-3-2 have already been enforced. The S2PFC techniques have been proposed and intensively studied, in order to comply these regulations with minimal additional component count and cost.
This dissertation provides a systematic study of the S2PFC input-current-shaping (ICS) mechanism, circuit topology generalization and variation, bulk capacitor voltage stress and switch current stress, converter design and optimization, and evaluation of the state-of-the-art S2PFC techniques with universal-line input.
Besides, this presentation also presents the development of novel S2PFC techniques with a voltage-doubler-rectifier front end to both improve the performance and reduce the cost of S2PFC converters for (international voltage range) universal-line applications. The calculation and experimental results show that the proposed techniques offer a more cost-effective and efficient solution than industriesâ current practice, with universal-line input and converter power level up to 600 W. Finally, further improved technique is also presented with reduced filter inductor size and increased power density.Ph. D.
10
Chan, Weng Hong. "Harmonic reduction and power factor correction in low power supply system." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1445817.
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Tan, Benjamin H. "A Novel Arc Welding Power Supply with Improved Power Factor Correction." DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2199.
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This paper presents the design and development of a novel Arc Welding Power Supply utilizing a modified two-switch forward converter topology. The proposed design improves the power quality by improving power factor to near unity and reducing total harmonic distortion. State space analysis of the proposed circuit showed that the circuit followed a boost-buck input output relationship. Simulation of the circuit was first implemented in LTspice to verify the functionality of the new topology. Hardware implementation of the proposed design was built on a scaled-down prototype for a proof-of-concept of the new topology. The prototype specifications were created for a 5A, 20V output with a 20-24V, 60Hz input. This project demonstrated that the proposed new topology was successful in obtaining a near unity power factor and a total harmonic distortion of less than 2%. Additionally, the prototype followed the simulation and calculations of a boost-buck function while varying duty cycle, and the final measurements aligned well with waveforms from the simulation.
12
Saasaa, Raed. "A single-stage interleaved resonant power factor correction converter." Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/59199.
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Applications requiring DC voltages vary widely, from low power, such as LED lighting, to high power, as in industrial motor drives and battery chargers. Accordingly, a unified power architecture for all applications is not practical for efficiency, size and cost optimization. The use of LED lighting system became popular due to its many advantages. The new outdoor applications such as street and flood lighting require high power (i.e. >200 W) in contrast to the low power existing LED drivers. Generally, the conventional architecture of AC/DC converters consists of two main stages; The first is current-shaping stage to improve PF and the second is to provide isolation and tight regulation over the output voltage. Recently, the research on AC/DC converters has focused on optimizing the converter design to be more reliable and efficient for low and medium power applications. Specifically, techniques have been proposed to eliminate the DC output bus electrolytic capacitor by introducing auxiliary DC/DC converter. On the other hand, the integrated converters were deployed by many researchers to decrease the number of switches, facilitate the controller design, and improve the efficiency. This thesis presents a novel single-stage AC/DC converter that can achieve high power factor with reduced switching losses for semiconductor devices. The topology is derived by integrating the interleaved boost-type PFC and full bridge LLC resonant converters. Due to interleaving at the input, the converter exhibits less input current ripple compared to the existing topologies. Therefore, it is suitable for applications up to approximately 500 W. A detailed analysis of the operation modes is presented. Also, a 350–W prototype is designed to verify the effectiveness of the topology.Applied Science, Faculty of
Engineering, School of (Okanagan)
Graduate
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George, Mark S. "Power factor correction using a boost quasi-resonant converter." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41901.
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A steady-state analysis of a quasi-resonant zero current boost converter is performed in its application to a single-phase power factor correction circuit. The known closed-form expressions are used to design the boost converter and the multiloop control circuit. The operating characteristics are simulated by using PSPICE and are experimentally verified. Considerations for a practical design are based upon hardware operating at a maximum of 1 megahertz, with a 115 VRMS input, 200 VDC and 100 watt output.
Master of Science
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Durrani, Yamin Qaisar. "Analysis of silicon carbide based semiconductor power devices and their application in power factor correction." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2573.
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Recent technological advances have allowed silicon (Si) semiconductor technology to
approach the theoretical limits of the Si material; however, power device requirements for
many applications are at a stage that the present Si-based power devices cannot handle.
The requirements include higher blocking voltages, switching frequencies, efficiency, and
reliability. Material technologies superior to Si are needed for future power device
developments. Silicon Carbide (SiC) based semiconductor devices offer one such
alternative. SiC based power devices exhibit superior properties such as very low
switching losses, fast switching behavior, improved reliability and high temperature
operation capabilities. Power factor correction stage of power supplies is identified as an
area where application of these devices would prove advantageous. In this thesis a high
performance, high efficiency, SiC based power factor correction stage is discussed. The
proposed topology takes advantage of the superior properties of SiC semiconductor based
devices and the reduced number of devices that the dual boost power factor correction
topology requires to achieve high efficiency, small size and better performance at high
temperature. In addition to this analysis of SiC based power devices is carried out to study
their characteristics and performance.
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Clark, Colin William. "Digital control techniques for power quality improvements in power factor correction applications." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/42799.
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The prevalence of standards and recommended practices to meet harmonic current limits has gained, and continues to gain, momentum over recent years. To meet these requirements, power electronic rectification devices are necessitated along with their specialized control techniques. A popular power electronic circuit to obtain low-harmonic input current is the boost power factor correction (PFC) converter, and with the advent of digital control, powerful control techniques to meet these harmonic current limits are possible.
The first contribution is a detailed guide to the conversion of an analog IC-controlled boost PFC converter to a digitally controlled equivalent. Design of the voltage and current sensing networks, compensator, overview of the critical interrupt service routines, and the control implementation in a digital signal processor (DSP) is presented. The existing boost PFC converter modified for digital control is successful, and provides a flexible prototyping test bench for further use.
The second contribution is a novel DSP-based discontinuous conduction mode (DCM) detection method for application to the boost PFC converter. The proposed detection method is computationally simple, and requires little or no modification to existing digitally controlled boost PFC converters using DSPs with on-board comparators. An experimental boost PFC converter verifies the effectiveness of the proposed detection method over traditional zero current detection and DCM detection techniques, enabling advanced control techniques for power quality improvements.
The final contribution is a new adaptive mixed conduction mode (MCM) control technique for the boost PFC converter. This MCM control technique applies the proposed DSP-based DCM detection method to realize higher power factor and decreased total harmonic distortion (THD) over a commercially available analog controller and a conventional digital controller. Using a boost PFC converter operating in MCM with the proposed adaptive control method, THD improvements of up to 4.55% at light loads and power factor improvements of up to 17.4% are provided over the analog and conventional digital controller.
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Barbosa, Peter Mantovanelli. "Three-Phase Power Factor Correction Circuits for Low-Cost Distributed Power Systems." Diss., Virginia Tech, 2002. http://hdl.handle.net/10919/28651.
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Front-end converters with power factor correction (PFC) capability are widely used in distributed power systems (DPSs). Most of the front-end converters are implemented using a two-stage approach, which consists of a PFC stage followed by a DC/DC converter. The purpose of the front-end converter is to regulate the DC output voltage, supply all the load converters connected to the distributed bus, guarantee current sharing, and charge a bank of batteries to provide backup energy when the power grid breaks down.
One of the main concerns of the power supply industry is to obtain a front-end converter with a low-cost PFC stage, while still complying with required harmonic standards, especially for high-power three-phase applications. Having this statement in mind, the main objective of this dissertation is to study front-end converters for DPS applications with PFC to meet harmonic standards, while still maintaining low cost and performance indices.
To realize the many aforementioned objectives, this dissertation is divided into two main parts: (1) two-stage front-end converters suitable for telecom applications, and (2) single-stage low-cost AC/DC converters suitable for mainframe computers and server applications. The use of discontinuous conduction mode (DCM) boost rectifiers is extensively explored to achieve simplicity, while reducing the cost for DPS applications. Interleaving of DCM boost rectifiers is also explored as an alternative approach to further reduce the system cost by reducing the filtering requirements. All the solutions discussed are implemented for 3kW applications, while 6kW is obtained by interleaving two converters.Ph. D.
17
Wall, Simon Robert. "Control of switched-mode power converters." Thesis, University of Cambridge, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.362966.
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Zhang, Jindong. "Study and Improvement of Single-Stage Power Factor Correction Techniques." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/36938.
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This thesis work focuses on the study and improvement of single-stage power factor correction techniques.
The generalized structures of the present pulse-width-modulation (PWM) integrated single-stage power factor correction (PFC) converters are presented. The typical PFC cells in the single-stage PFC converter are identified. After that, the necessary PFC condition is derived and verified to understand the principle of the single-stage PFC converters.
As an example, the continuous current mode (CCM) current source single-stage PFC converter is studied. The circuit intuitions and design consideration of this converter are presented. Also, an improved current source single-stage PFC converter with a low-frequency auxiliary switch is proposed to overcome the problem of the previous converter. Experimental verification shows the improvement is effective.
To evaluate single-stage PFC technique, a comparison study between the current source single-stage and the boost two-stage PFC converters is done in this thesis. It shows that for universal line application, due to the wide bus-capacitor voltage range, single-stage PFC converters have higher component ratings than two-stage PFC converters. This limits the application of single-stage PFC converter. Therefore, an interesting future work will be how to reduce the bus voltage range of single-stage PFC converters.Master of Science
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Zhao, Yiqing. "Single Phase Power Factor Correction Circuit with Wide Output Voltage Range." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/35764.
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The conventional power factor correction circuit has a fixed output voltage. However, in some applications, a PFC circuit with a wide output voltage range is needed. A single phase power factor correction circuit with wide output voltage range is developed in this work.
After a comparison of two main power stage candidates (Buck+Boost and Sepic) in terms of efficiency, complexity, cost and device rating, the buck+boost converter is employed as the variable output PFC power stage. From the loss analysis, this topology has a high efficiency from light load to heavy load.
The control system of the variable output PFC circuit is analyzed and designed. Charge average current sensing scheme has been adopted to sense the input current. The problem of high input harmonic currents at low output voltage is discussed. It is found that the current loop gain and cross over frequency will change greatly when the output voltage changes. To solve this problem, an automatic gain control scheme is proposed and a detailed circuit is designed and added to the current loop.
A modified input current sensing scheme is presented to overcome the problem of an insufficient phase margin of the PFC circuit near the maximum output voltage. The charge average current sensing circuit will be bypassed automatically by a logical circuit when the output voltage is higher than the peak line voltage. Instead, a resistor is used to sense the input current at that condition. Therefore, the phase delay caused by the charge average current sensing circuit is avoided.
The design and analysis are based on a novel air conditioner motor system application. Some detailed design issues are discussed. The experimental results show that the variable output PFC circuit has good performance in the wide output voltage range, under both the Boost mode when the output voltage is high and the Buck+Boost mode when the output voltage is low.Master of Science
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Lord, Edward Michael. "Single-stage power factor correction converter topologies for low power off-line applications." Thesis, University of Edinburgh, 2004. http://hdl.handle.net/1842/15234.
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Since January 2001 it has been necessary for equipment connected to the low voltage public distribution network in Europe and Japan to comply with IEC 61000-3-2. The regulation IEC 61000-3-2 specifies the level of current that can be drawn for particular harmonics. Much equipment today is fitted with a Switch Mode Power Supply (SMPS) at its input to interface between the line voltage and internal low voltage electronics. This SMPS must not only convert the line voltage, but also ensure that the input current to the device meets the IEC regulations. To meet these regulations two methods are normally used, passive filtering using a large filter inductor or a boost converter cascaded with the main DC/DC SMPS converter with isolation. To try and reduce component count, cost and increase efficiency many new single-stage Power Factor Correction (PFC) topologies have been proposed. In a single-stage topology the output voltage regulation and meeting IEC 61000-3-2 are combined into a single power stage. Unfortunately very little is known about the behaviour or performance of these single-stage topologies. In this thesis two of the more promising single-stage topologies, the bi-forward and CS S2PFC converters are investigated further. A new topology using a low frequency switch (LFSPFC) is introduced. The topologies are analysed investigating input current shape and harmonic content, voltage variation on bulk capacitance and component stresses. Simulation in PSpice is used to confirm circuit operation. Four 150W output power experimental circuits were built: bi-forward converter, CS S2PFC converter, passive filtering cascaded with a forward converter and a boost pre-regulator cascaded with a forward converter. The converters operate from universal input voltage and have outputs at 5V and 12V. A 100W test circuit was built for the LFSPFC operating from 230V input voltage and with an output of 5V. Experimental results are presented showing circuit behaviour and performance of the bi-forward, CS S2PFC and LFSPFC converters. The bi-forward and CS S2PFC converters are compared to the passive filter and boost converter cascaded with a forward converter. It is demonstrated that neither of these single-stage topologies is at present a viable replacement for either present method, but the LFSPFC could be a lighter weight and less bulky alternative to passive filtering.
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Gamboa, Gustavo. "REALIZATION OF POWER FACTOR CORRECTION AND MAXIMUM POWER POINT TRACKING FOR LOW POWER WIND TURBINES." Master's thesis, University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4283.
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In recent years, wind energy technology has become one of the top areas of interest for energy harvesting in the power electronics world. This interest has especially peaked recently due to the increasing demand for a reliable source of renewable energy. In a recent study, the American Wind Energy Association (AWEA) ranked the U.S as the leading competitor in wind energy harvesting followed by Germany and Spain. Although the United States is the leading competitor in this area, no one has been able successfully develop an efficient, low-cost AC/DC convertor for low power turbines to be used by the average American consumer. There has been very little research in low power AC/DC converters for low to medium power wind energy turbines for battery charging applications. Due to the low power coefficient of wind turbines, power converters are required to transfer the maximum available power at the highest efficiency. Power factor correction (PFC) and maximum power point tracking (MPPT) algorithms have been proposed for high power wind turbines. These turbines are out of the price range of what a common household can afford. They also occupy a large amount of space, which is not practical for use in one's home. A low cost AC/DC converter with efficient power transfer is needed in order to promote the use of cheaper low power wind turbines. Only MPPT is implemented in most of these low power wind turbine power converters. The concept of power factor correction with MPPT has not been completely adapted just yet. The research conducted involved analyzing the effect of power factor correction and maximum power point tracking algorithm in AC/DC converters for wind turbine applications. Although maximum power to the load is always desired, most converters only take electrical efficiency into consideration. However, not only the electrical efficiency must be considered, but the mechanical energy as well. If the converter is designed to look like a purely resistive load and not a switched load, a wind turbine is able to supply the maximum power with lower conduction loss at the input side due to high current spikes. Two power converters, VIENNA with buck converter and a Buck-boost converter, were designed and experimentally analyzed. A unique approach of controlling the MPPT algorithm through a conductance G for PFC is proposed and applied in the VIENNA topology. On the other hand, the Buck-boost only operates MPPT. With the same wind profile applied for both converters, an increase in power drawn from the input increased when PFC was used even when the power level was low. Both topologies present their own unique advantages. The main advantage for the VIENNA converter is that PFC allowed more power extraction from the turbine, increasing both electrical and mechanical efficiency. The buck-boost converter, on the other hand, presents a very low component count which decreases the overall cost and volume. Therefore, a small, cost-effective converter that maximizes the power transfer from a small power wind turbine to a DC load, can motivate consumers to utilize the power available from the wind.M.S.E.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE
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Ahmed, Saeed. "Controlled on-time power factor correction circuit with input filter." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11072008-063637/.
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Kalpaktsoglou, Dimitrios. "Power factor correction for stand-alone wave energy conversion buoys." Thesis, University of Newcastle Upon Tyne, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.519591.
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Zhou, Chen. "Design and analysis of an active power factor correction circuit." Thesis, Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/53729.
Full textAbstract:
The design of an active-unity power factor correction circuit with variable-hysteresis
control for off-line dc-to-dc switching power supplies is described. Design
equations relating the boost inductor current ripple to the circuit components selection
and circuit performance arc discussed. A computer-aided design program (CADO) is
developed to give the optimal circuit components selection. A 500 watt, 300 volt experimental
circuit is built to verify the simulation and analysis results.
The control-to-output response of the power factor circuit is verified with the experimental
results. Design guidelines for the low-frequency feedback network are presented.
Small-signal closed-loop responses are measured with an experimental power
factor circuit.Master of Science
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Pal, Subarna. "Simulation of current mode control schemes for power factor correction circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0008/MQ36162.pdf.
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Gau, Yu-Jun, and 高鈺鈞. "Low Cost Simple Power Factor Correction." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/5uw96v.
Full textAbstract:
碩士遠東科技大學
電機工程研究所
107
This thesis proposes a low-cost simple power factor correction converter architecture. Since the commercially available power factor correctors are upgraded to 400V without lower voltage, considering the low-voltage equipment can be used, it is proposed to achieve high-efficiency circuits at low cost. This article uses the IC ICE2PCS02 in continuous conduction mode as the correction IC for this power factor corrector. This circuit simulates the boost converter simulation in the case of input 70-130Vac boost to output 200V for three different load cases. At half load, the efficiency can reach 94-95% or more. When it is fully loaded, its efficiency can reach 98-99%, effectively achieving a low-cost and high-efficiency structure.
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Fan, Yang-Dian, and 范揚典. "Comparator Implemented Digital Power Factor Correction Rectifier." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/fe7tu6.
Full textAbstract:
碩士國立高雄科技大學
電機工程系
107
Power factor correction rectifier (PFC) is the front end of most computer power supplies. Due to the climate change, high efficiency over wide load range is highly demanded in PFCs. This drives digital controller to replace analog controller. Analog to digital converters (ADC) are the essential parts for all digital powers. Some previous researches replace the ADC with a comparator and a counter for measuring the DC value of a rippled signal. Comparator based control does not only reduces system cost, but also eliminates the sampling error of the ADC. For those signals with small ripple, the comparator based digital controller injects extra analog ripple on signal feedback for signal sensing. However, in digital PFC, system operation point varies along the line voltage. The fixed analog ripple injection can only be optimized for one operating point. Therefore, a digital ripple injection is introduced in this paper. Instead of using analog circuits to generate analog ripple, a digital to analog converter (DAC) and a low pass filter can generate filtered digital ripple signal as the ripple inject. Based on digital ripple injection, a 500 watt digital PFC is implemented experimentally.
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Dash, Roma. "Power factor correction using parallel boost converter." Thesis, 2011. http://ethesis.nitrkl.ac.in/2462/1/PFC_using_parallel_boost_converter.pdf.
Full textAbstract:
The increased use of power electronic devices has declined the power quality in terms of introduction of harmonics and lowering of power factor.This is due to their non-linear nature of operation. Hence,power factor correction (PFC) is the need of the hour.This thesis informs about the various PFC methods and focusses on PFC using parallel boost converter in particular. A design of the PFC using parallel boost converter employing average mode control in done and the results so obtained are compared with that of a single boost converter and a rectifier circuit without any PFC circuit.
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Behera, Satyasuranjeet, Sibasis Mohapatra, and Monalisa Bisoi. "Automatic power factor correction by microcontroller 8051." Thesis, 2007. http://ethesis.nitrkl.ac.in/4159/1/Automatic_Power_Factor.pdf.
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In the present technological revolution power is very precious. So we need to find out the causes of power loss and improve the power system. Due to industrialization the use of inductive load increases and hence power system losses its efficiency. So we need to improve the power factor with a suitable method. . When ever we are thinking about any programmable devices then the embedded technology comes into fore front. The embedded is now a day very much popular and most the product are developed with Microcontroller based embedded technology.Automatic power factor correction device reads power factor from line voltage and line current by determining the delay in the arrival of the current signal with respect to voltage signal from the function generator with high accuracy by using an internal timer. This time values are then calibrated as phase angle and corresponding power factor. Then the values are displayed in the 2X16 LCD modules. Then the motherboard calculates the compensation requirement and accordingly switches on different capacitor banks. This is developed by using 8051 microcontroller.Automatic power factor correction techniques can be applied to the industries, power systems and also house holds to make them stable and due to that the system becomes stable and efficiency of the system as well as the apparatus increases. The use of microcontroller reduces the costs.
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Yadav, Vinod Kumar. "Power Factor Correction in Ac-Dc System." Thesis, 2017. http://ethesis.nitrkl.ac.in/8938/1/2017_MT_VKYadav.pdf.
Full textAbstract:
With the increase in demand of modern advance power electronics devises,there has been a tremendous stress on the utility power quality. The steady growth of use of electronics equipment in various industries and household application has become a significant problem as per the line current harmonic is concerned. Their adverse effects on the power system are instability problem,the increase in reactive power demand , the neutral current magnitude increase and becomes the cause of overheating of transformers and induction motors, as well as the dreadful conditions of system voltage waveforms. Different nonlinear loads that are responsible for higher input current THD(%) are the bridge rectifiers, florescent lamps ,SMPS devise, Arc furnace electric welding machines etc..In this thesis we deal with power factor correction in AC-DC system (Rectifiers).There is Active and Passive method for PFC which involves use of active and passive elements respectively. Different conventional and nonlinear control schemes are analyzed for the switching for Rectifiers. Our objective is to get a sinusoidal input voltage i.e in phase with the applied source. For this we are dealing with different DC-DC topologies such as forward flyback, boost and interleaved and their adverse effect when they are cascaded with Vienna rectifier, synchronous bridgeless rectifier and a modified Novel AC-DC converter. For this work MATLAB/SIMULINK power system toolbox is used to simulate and RUN the proposed topologies Simulation results are presented and the improvement in the supply current can be seen in the obtained waveform of the different topologies. The power factor nearly equal to unity is obtained almost in all the topologies and Harmonic distortion within the IEC 555-2 norms.
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Huang, Kuan-Ju, and 黃冠儒. "Development of a Digital Meter with Power Factor Correction Correction Capability." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/d8q927.
Full textAbstract:
碩士國立臺北科技大學
自動化科技研究所
105
The thesis proposed a digital meter with power factor correction capability when the measured signal contains harmonic components. By using resistor voltage divider circuit and current clamp, the input voltage and current are transferred to small voltage signals which can be processed by the microprocessor. These voltage and current waveform are digitized through an analog-to-digital convertor (ADC). Fast Fourier Transform (FFT) is applied. The Hanning Window and frequency interpolation algorithm is used to correct the voltage and current signals. As the front-end circuit may introduce phase shift, phase compensation calculation is required. Accurate RMS voltage, RMS current, active power, reactive power, apparent power, power factor and frequency can be calculated. When measured signal contains harmonic components, the THD is calculated and is used to correct the power factor calculation. The final measurement results are displayed on the LCD and transmitted through the UART. Calibration procedure is also developed to simplify the calibration process. All of the calibration parameters are stored in nonvolatile memory.
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Mishra, Pushanjeet, and Abhisek Kumar Panda. "Load balancing and power factor correction in power distribution system." Thesis, 2014. http://ethesis.nitrkl.ac.in/6395/1/E-8.pdf.
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The project presents an approach for load balancing and power factor correction. First we have considered a three phase grounded load system where the supply is a three phase balanced supply. Before balancing the load and correcting the power factor it is necessary to compensate the neutral current. We propose three schemes for neutral current balancing. After that the system becomes equivalent to ungrounded star connected load. Now to carry power factor correction and load balancing we need to convert the load to delta connected load. Hence we carry out star-delta transformation and we carry out our main objective through the proposed methods.
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Kurma, Sai Mallika. "Topological issues in single phase power factor correction." Thesis, 2007. http://ethesis.nitrkl.ac.in/4305/1/Topological_issues_in_single_phase_power.pdf.
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The equipment connected to an electricity distribution network usually needs some kind of power conditioning, typically rectification, which produces a non-sinusoidal line current due to the nonlinear input characteristic. With the steadily increasing use of such equipment, line current harmonics have become a significant problem. Their adverse effects on the power system are well recognized. They include increased magnitudes of neutral currents in three- phase systems, overheating in transformers and induction motors, as well as the degradation of system voltage waveforms. Several international standards now exist, which limit the harmonic content due to line currents of equipment connected to electricity distribution networks. As a result, there is the need for a reduction in line current harmonics, or Power Factor Correction - PFC. There are two types of PFC’s. 1) Passive PFC, 2) Active PFC. The active PFC is further classified into low-frequency and high-frequency active PFC depending on the switching frequency. Different techniques in passive PFC and active PFC are presented here. Among these PFC’s we will get better power factor by using high-frequency active PFC circuit. Any DC-DC converters can be used for this purpose, if a suitable control method is used to shape its input current or if it has inherent PFC properties. The DC-DC converters can operate in Continuous Inductor Current Mode – CICM, where the inductor current never reaches zero during one switching cycle or Discontinuous Inductor Current Mode - DICM, where the inductor current is zero during intervals of the switching cycle. In DICM, the input inductor is no longer a state variable since its state in a given switching cycle is independent on the value in the previous switching cycle. The peak of the inductor current is sampling the line voltage automatically. This property of DICM input circuit can be called “self power factor correction” because no control loop is required from its input side. In CICM, different control techniques are used to control the inductor current. Some of them are (1) peak current control (2) average current control (3) Hysteresis control (4) borderline control. These control techniques specifically developed for PFC boost converters are analyzed. For each control strategy advantages and drawbacks are highlighted and information on available commercial IC's is given. This high frequency switching PFC stage also has drawbacks, such as: it introduces additional losses, thus reducing the overall efficiency; it increases the EMI, due to the highfrequency content of the input current. Some of the EMI requirements are discussed. But the level of high-frequency EMI is much higher with a considerable amount of conduction and switching losses. This highfrequency EMI will be eliminated by introducing an EMI filter in between AC supply and the diode bridge rectifier. The efficiency will be improved by reducing the losses using soft switching techniques such as ‘Zero Voltage Switching’- (ZVS), ‘Zero Voltage Transition’ (ZVT), and ‘Zero Current Switching’- (ZCS). We study circuit techniques to improve the efficiency of the PFC stage by lowering the conduction losses and/or the switching losses. Operation of a ZVT converter will be discussed, in which the switching losses of the auxiliary switch are minimized by using an additional circuit applied to the auxiliary switch. Besides the main switch ZVS turned- on and turned-off, and the auxiliary switch ZCS turned-on and turned-off near ZVS. Since the active switch is turned- on and turned-off softly, the switching losses are reduced and the higher efficiency of the system is achieved.
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Ku, Chen-wei, and 顧振維. "Design of Robust SEPIC Power Factor Correction Circuits." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/x6phvx.
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碩士國立中山大學
電機工程學系研究所
95
This thesis mainly studies the active power factor correction circuit using a new AC/DC Single Ended Primary Inductance Converter (SEPIC). For power factor correction, inductor current is operated in the continuous conduction mode. First of all, the converter is analyzed by state space averaging method. Furthermore, the operational principle of PFC circuit with PI control law is analyzed. A good power factor system is then developed by time-domain and frequency-domain analysis. A classical PFC circuit with PI control law has low power factor when light load. In order to overcome problem, the thesis proposes a SEPIC circuit with robust performance. Compared with circuits using classical PI controller and PFC IC, the proposed system obtains higher power factor under the condition of the same light load.
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Wu, Chen-chia, and 吳振嘉. "Study of Active Power-Factor Correction Controller Circuits." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/74243596431118058324.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
93
This thesis aims at investigating the technologies of the active power-factor correction (PFC) circuit. The system originally in the article is based on a boost converter circuit as the structure, the control method is to adopt the average current mode. We doesn’t only narrate the circuit principle of the systematic circuit in the article but also use the OrCAD PSpice A/D software to simulation. Finally, we implemented make a prototype circuit and verified the proposed method. The experimental result shows that it can reach the goal for the power-factor correction.
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Cheng, Kai-fang, and 鄭凱方. "Design and Modeling of Power Factor Correction Circuits." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/16884200876201526098.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
93
This thesis aims to investigate an active power factor correction (PFC) circuit and its mathematical model, in order to develop a reliable and efficient simulation platform. By using the PI controller, we can control the inductor current and the output voltage of the boost converter. Finally, we constructed the circuit and analyzed the results to verify that our mathematical model is valid.
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Lan, Yi-Meng, and 藍義孟. "CCM Single-Stage Power Factor Correction Electronic Ballast." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/99552950824506979014.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
92
This thesis presents a continuous-current-mode (CCM) single-stage power factor correction (PFC) electronic ballast, which is a combination of a boost-type PFC network and a DC/AC inverter to allow CCM operation for the PFC inductor in the boost-type PFC network. Among the PFC techniques proposed in recent years, in general, the discontinuous-current-mode (DCM) single-stage PFC electronic ballasts have such drawbacks as high electromagnetic interference (EMI), high current stress, and high switching and conduction losses. The PFC capacitor of the developed boost-type PFC network can help the PFC inductor to achieve CCM, thus shaping the input current of the proposed electronic ballast to achieve high power factor (PF). Finally, a 36W rated power electronic ballast prototype circuit is designed and implemented. Experimental results verify the advantages of the proposed ballast; these include the following: the input current harmonics meet the IEC 61000-3-2 Class C Standard, and the ballast offers lower conducted EMI and lower current stress on switches and diodes.
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Ikriannikov, Alexandr. "New Developments in Single Phase Power Factor Correction." Thesis, 2000. https://thesis.library.caltech.edu/6104/1/Ikriannikov_a_2000.pdf.
Full textAbstract:
Power Factor Correction (PFC) is a necessary feature of many AC/DC Power Electronics products. The issues of increasing the value of the Power Factor (PF) and increasing efficiency of transferring the power in such applications motivated this thesis.
Input rectification is needed for the most topologies in AC/DC applications for these topologies to perform however, it is pretty much one of the main causes of distortions and power losses. Diode bridge is also one the hottest components of PFC, which is an important issue in terms of thermal management.
New approach for Power Factor Correction is introduced in the first part. Topologies with bipolar gain characteristics are proposed to be used, naturally providing constant DC output from non-rectified AC input. Practical design of such converter is presented and analyzed, theoretical predictions are confirmed by experimental data; proposed idea of Power Factor Correction is verified.
Another new general approach of Power Factor Correction improvement is introduced in second part. Idea of shifting input line rectification to switching elements of the power stage is proposed for certain topologies and verified on practical example. Key features are analyzed and illustrated by experimental data. This class of converters presents an opportunity for accurate comparison with related conventional topologies, which is included to show the advantages of the new approach.
General advantages and improvements of Power Factor value in bridge-less topologies in comparison to conventional converters are analyzed and illustrated experimentally in the third part of the thesis.
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Wu, Hsiang-Yu, and 伍翔榆. "Battery Balancing Charger with Interleaved Power Factor Correction." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/68157200208396427624.
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碩士國立彰化師範大學
電機工程學系
104
An interleaved battery balancing charger with power factor correction for two series-connected batteries is proposed in this thesis. The developed balancing charger is composed of a two-phase interleaved buckboost converter and a dual-output balancing charging circuit. The interleaved buckboost converter is operated in discontinuous conduction mode for power factor correction. The voltage and current of each battery are sampled and fed back to a micro-controller unit. The dual-output balancing charging circuit would be controlled with constant-current / constant-voltage charging algorithm and according to the state of each battery. Finally, a hardware with rated power 200W and ac input 110V for charging two 12V/22Ah series-connected batteries is constructed. Additionally, a hardware with single phase buckboost converter is also constructed for comparison. From the experimental results, it is seen that the performance of the interleaved topology is better. The efficiency of the proposed converter is up to 93% and each of the two batteries can be well balancing charged.
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Wu, Rong-hui, and 吳榮輝. "DESIGN OF TWO-STAGE BOOST POWER FACTOR CORRECTION." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/84559969850444277906.
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碩士大同大學
電機工程學系(所)
97
ABSTRACT This thesis presents the problem with respect to the dual boost technique of the power factor correction ( PFC ) application. In the PFC a series problem will occur when the PFC is worked in single boost ( only one section_PFC bus is 400V ) even in low mains input, it will then generate a low mains voltage of switching loss on the PFC MOSFET to reduce the efficiency in low mains input . Therefore, In order to prevent this issue happened, we need to change the design concept from single boost to two-stage boost which can improve the efficiency when the input is in low mains voltage for EPA standard application. We knew that if we want to improve the efficiency in low mains voltage that is also passed EPA standard requirement which have to change the design concept to increase low mains voltage efficiency that means as below : Low mains input_90Vac~160Vac : PFC voltage is setting in 250Vdc High mains input_170Vac~264Vac : PFC voltage is setting in 400Vdc
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Che, Lin-Wei, and 林維哲. "Intelligent energy-saving clothes dryerwith power factor correction." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/49166780854980985719.
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碩士崑山科技大學
電機工程研究所
100
The core of this paper is based on intelligent energy-saving clothes dryer with power factor correction. And design the boost power factor correction converters, BLDC motor speed control drive system and temperature control of the drive system. The power supply uses the boost converter structure and adopts average current control method to complete the active power calibration purposes. It meets the regulations of international current harmonics wave. In drying technology, a new energy-saving automatic drying control methods improved from original patent is designed.The microprocessor is used to detect the exhaust temperature gradient for controlling the shutdown of the heater and the motor speed. When the small change of the exhaust temperature gradient is reached, it represents that no more water inside clothes can be evaporated and the clothes has been dry enough, the heater is automatically shut down and steps to end the dryer. At this moment, the motor, which is used to drive the drum and fan, keeps operating, and the fan speed is controlled to drive more the cooler outside air to cool down hot clothes faster. It can also obtain less-wrinkle of clothes and less static electricity on clothes. While the exhaust temperature is close to that of outside air, the dryer will be completely shut down, the clothes will be less-wrinkle because of fast and enough cooling. Thus, the user will not feel hurt taking clothes even right after the dryer stop.And this dryer can obtain energy-saving and carbon-reducing effect,and the above user friendly designs make user more convenient using.While this dryer is used, it does only need to one-touch on the power and without any set-up process. More than that, the user does not worry the wrong time setup resulting in over drying or not-enough drying. It is proved from experiments that the energy-saving effect of this innovative method is 20% high than those of other dryers.
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Wu, Yi-Wei, and 吳亦瑋. "Study of Digital Controller for Power Factor Correction." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/28346693759425565290.
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碩士中原大學
電機工程研究所
100
【Abstract】 Power supply is still based on analog control IC as the main controller, the advantage of a low cost. The circuit is relatively simple. Fast response; but usually only to provide specific control functions, simple user interface, not suitable for operation in the complex power system integration, and control loop compensation is not easy to adjust. In recent years, with the rapid development of digital signal controllers, the digitization of the power system is the trend of the future development of power design, power management, and multi-functional power supply requirements, an increase of more switching power driver IC demand also changed the power supply power supply architecture. Digital power technology has the flexibility of the parameters, programmable, you can use the firmware control mode, the complex power control and management strategies, from the accurate numerical computation of the impact of environmental change, the integration of modular applications in the development of timing, the key is that the demand for power management-oriented integration. In the commercialization of the product development process, the first digitization of the power supply interface, the development of system-oriented power management mechanism, and then gradually internalized to the power supply control IC with in the process control, and finally developed into going digital type loop control. As the power requirements of the new generation of high performance microprocessors, power supply control IC from the traditional single analog control, toward a multi-functional integrated control IC development, such as TI and Infineon launched at the same time with a power factor correction and pulse-width modulation control of the multi-function control IC. I believe in the near future, the application of digital analog IC design technology in the power supply control IC development, will become the development trend of the power supply control IC, power supply control IC toward a digital, programmable, intelligent direction.
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Tsai, Hsien-Yi, and 蔡憲逸. "Novel Soft-Switching Bridgeless Power Factor Correction Circuits." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/84640922552273594209.
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博士國立臺灣大學
電機工程學研究所
99
Power factor correction (PFC) has become almost a must for off-line power applications nowadays. Despite intensive research in the past decade, this is still a hot-research topic among power electronic field because of the “green” push for the future electric power applications. About ten years ago, there was a PFC power-stage configuration named” Bridgeless” reported. In this configuration, the diode bridge conventionally used PFC applications can be removed and therefore resulting in lower conduction power loss for the applications. The main focus of this dissertation is about soft-switching “Bridgeless” PFC (BPFC) circuits which feature improved efficiency. In the dissertation, three classes of soft-switching BPFC circuits are proposed. The first class is a zero-voltage transition BPFC in which an assistant circuit is used to achieve soft switching in the main power switches. However, the assistant switch is still turned off by hard switching. The second class is a zero-voltage zero-current BPFC circuit in which soft switching is achieved not only for the main switches but also for the assistant switch. And the third class is an extension of the first class to a three-phase PFC circuit. Different circuit variations are also proposed to the above three classes. Computer simulations and experimental results are presented in the dissertation. Design guidance is also included. Improvements of efficiencies, compared to conventional hard-switching circuits are in the range of one to two percentage points which is a significant improvement.
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Guo, Jia-Lin, and 郭家菱. "Bridgeless Interleaved Buck Converter for Power Factor Correction." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/6yy57v.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
106
This thesis studies the active power factor correction. In terms of converters, this thesis proposes a novel bridgeless interleaved buck converter for power factor correction, and uses digitalized average current control method to control the AC input voltage in positive half-cycle and negative half-cycle to achieve power factor correction. The interleaved architecture not only controls simplicity, but also can effectively reduce the component current stress at high output power, improve the high current resistance of the power components, the overlarge volume of the inductors, and the overlarge of output capacitors. This thesis actually produces a 480W bridgeless interleaved buck converter to verify whether the analysis and design considerations are reasonable. Unlike most power factor correction converters, which are used in the boost architecture, the bridgeless interleaved buck converter proposed in this thesis can be used in lower voltage applications, can reduce the values of output electrolytic capacitor and reduce the cost, and also because of the interleaved buck architecture, it can be applied to applications with high output power. The feasibility of the proposed architecture is verified by the experimental results in this thesis, and the total harmonic distortion and power factor of the input current can meet the international specifications.
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Routray, Smruti Suman. "Microcontroller Based Automatic Power Factor Correction in Mines." Thesis, 2015. http://ethesis.nitrkl.ac.in/7799/1/2015_MT_Microcontrolar_ROUTRAY.pdf.
Full textAbstract:
With the mining industry moving from traditional manual methods to the advanced mechanised mining, the focus is also shifting to the energy efficiency of the equipment and system being employed. Most of the equipment used in mining like shovel, drill, elevator, continues miner, conveyor, pumps etc. runs on electricity. Electric energy being the only form of energy which can be easily converted to any other form plays a vital role for the growth of any industry. The Power Factor gives an idea about the efficiency of the system to do useful work out of the supplied electric power. A low value of power factor leads to increase is electric losses and also draws penalty by the utility. Significant savings in utility power costs can be realized by keeping up an average monthly power factor close to unity. The work carried out is concerned with developing power factor correction equipment based on embedded system which can automatically monitor the power factor in the mining electrical system and take care of the switching process to maintain a desired level of power factor which fulfils the standard norms. The Automatic Power Factor Correction (APFC) device developed is based on embedded system having 89S52 microcontroller at its core. The voltage and current signal from the system is sampled and taken as input to measure the power factor and if it falls short of the specified value by utility, then the device automatically switch on the capacitor banks to compensate for the reactive power. After employing the correction equipment the targeted power factor of 0.95 is achieved and the increase in power factor varied from 9% to 19% based on the combination of load. There is also a decrease of 1.7% in the total energy consumption due to reduction in load current. The economic analysis for power factor improvement considering the data from a local coal mine suggested the payback period to be around 9 months if the correction equipment is implemented
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Liu, Chih-Wen, and 劉誌文. "The Design and Implementation of a Two-Quadrant Active Clamp Forward Converter with Power-Factor-Correction Converter with Power-Factor-Correction." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/98688362522878433226.
Full textAbstract:
碩士國立高雄應用科技大學
電機工程系
97
This thesis focuses on the analysis and design of a two-quadrant active clamp forward converter with active power factor correction. First, the characteristics of the power factor correction and conventional active clamp forward converter will be analyzed in this thesis, and then an improved two-quadrant active clamp forward converter topology is proposed. The topology will focus on solving the problems that when the main power switch of conventional active clamp forward converter is turned off, it will need to afford higher voltage stress, and that the zero voltage switching conditions between the main switch and auxiliary switch has big difference. Finally, the theory is verified by IsSpice software and a 100W AC-DC power converter is implemented. The maximum efficiency of the two-stage converter is 83%.
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Hsu, Yu-chun, and 許毓群. "Implementation of a Digital DC Power Supply with Power Factor Correction." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/44114013949569299375.
Full textAbstract:
碩士國立臺灣科技大學
電機工程系
96
The thesis implements a digital DC power supply with power factor correction. The hardware circuit includes a power factor correction circuit and a phase-shift full-bridge circuit. In the thesis, a UC3854 is used to control the power factor of the input source. In addition, a TMS320LF2407A is used to execute the closed loop control algorithms. The detailed principles and design methods are included. Finally, a DC power supply with 48V/864W, 0.99 power factor, satisfactory EN-61000-3-2 Standards is implemented. Experimental results can validate the theoretical analysis to show the feasibility and correctness of the thesis.
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Chen, Hsin-Hon, and 陳信宏. "Digital power factor correction circuit of AC/DC converter." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/67968339218317731054.
Full textAbstract:
碩士國立清華大學
電子工程研究所
92
This thesis introduces some type of the power converters and themechanism of power factor correction (PFC) circuits; and present the study and implementation of digital power factor correction circuit that uses TSMCCMOS 0.35 um technology to realize PFC circuit. With the growing of VLSI technology, the development of industry and electronic products all need more reliable, cheap and intelligent power control system. How to control several watts even tens of kilowatts power transformation without consuming too much energy during transforming is the topic for scholars to study and implementation. In the other word, how to use energy efficiently will be an aim to power electronics. PFC circuits play an important role to improve the efficiency and to minimize the power pollution .When people pay attention to environmental protection, some people also care about the pollution about power system. Many countries in Europe and North America make some standards to constrain some power products, IEEE 519 and IEC 1000-3-6 for example. PFC circuit can achieve high power correction factor and minimize the total harmonic distortion, so nowadays many powerproducts include the PFC function in them. Many IC design concepts base on digital and analog circuits , these two types both have advantages and disadvantages. The PFC circuits are also divided into two types---digital and analog. This thesis will compare these two types, and combine some advantages of digital and analog circuits to realize the PFC circuit. Because the majority of the PFC circuit is digital, it still called ‘digital PFC circuit’. Finally, this work uses TSMC CMOS 0.35 um technology to simulate PFC circuit, then the power factor achieves 0.999 and total harmonic distortion achieves 2.09% when full loading.
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Jian, Chih-Yuan, and 簡志遠. "Fuzzy Logic Controller Design for Active Power Factor Correction." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/r4xsbx.
Full textAbstract:
碩士國立臺北科技大學
電機工程系所
99
With the rapid development of electronics industry, the need for switching power converters has increased significantly. Therefore, increasing the energy efficiency of electronic products is a very important topic. Because the electrical equipment has nonlinear power components, it makes unnecessary power consumption. However, the purpose of power factor correction is to make the phase of input current in phase with the input voltage. Then the load will be equivalent to the pure resistive load, and the power only provides real power we need. Power factor correction can be classified as passive and active. The passive power factor correction is to use the passive components to compensate for the phase such as inductors, capacitors, etc. But we cannot arbitrarily change compensation components we need with changes in loading. Therefore, passive power factor correction has its disadvantage. In this thesis, we use active power factor correction to switch elements and compensate for the phase. Because the power conversion circuits are nonlinear systems, we propose a fuzzy logic controller to replace the traditional PI controller. Without detail mathematical derivation of the system, the proposed method will be able to achieve power factor correction and output voltage regulation purposes. After comparing with traditional controller, the transient response of power factor corrector with fuzzy controller is faster than traditional one in the same condition of power factor.
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Chang, Kai-Chi, and 張凱棋. "Design of One-Cycle Control Power Factor Correction IC." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/17593480750445629679.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
96
A one-cycle control based trailing-edge boost type power factor correction IC with instant-switch-current control is proposed in this thesis. It can be utilized to control the front stage of power converter. This control IC is easy to use because only two feedback signals are needed. One is input current and another is output voltage. Multiplier is excluded in this chip. In conventional PFC control chip, the input voltage and load demand are related by using a multiplier. The performance of power factor correction is highly dependent on the precision of multiplier. By using the integrator with reset proposed in one cycle control, the duty ratio can be precisely controlled to lower the total harmonic distortion. Moreover, a level shift circuit is adopted to make this chip work with unipolar supply voltage. For the purpose of better performance, the functions such as leading edge blanking (LEB) and over voltage protection (OVP) are also integrated into the proposed chip. This chip is fabricated with 0.35μm 2P4M 3.3V/5V Mixed Signal CMOS Process.