Academic literature on the topic 'Power HIL simulation'

Abstract Hardware in the Loop (HIL) semi-physical real-time simulation can shorten the research period and complete the harsh working condition test, which is difficult to be carried out on the physical platform. Taking the off-grid Doubly Fed Induction Generator (DFIG) wind power system as the research object, this paper proposes the bottom modelling method of HIL real-time simulation. Using the Hardware Description Language VERILOG, the bottom real-time models of DFIG, converter and load are designed on Field Programmable Gate Array (FPGA), connected with the real controller, and the HIL real-time simulation platform is constructed. The experiments of conventional working conditions and unbalance load are carried out on the HIL platform and the physical platform. The operation speed of the HIL platform reaches 0.48μs. Compared with the physical platform, the error of HIL platform is between 1.17 ~ 3.29% under various working conditions.

Hardware-in-the-loop (HIL) is a common technique used for testing in power electronics. It draws upon FPGAs (field-programmable gate arrays) because they allow for reaching real-time simulation for mid-high switching frequencies. FPGA area and delay are keys to reaching a compromise between performance and accuracy. To minimize area and delay, signal word length (WL) is critical. Furthermore, the input and output’s WL should be carefully chosen because these signals come from ADCs (analog-to-digital converters) or go to DACs (digital-to-analog converters). In other words, the role of ADCs and DACs is the boundary condition when assigning all the signal WLs in an HIL model. This research presents an automatic method for computing the signal WLs in the corresponding model by considering input/output boundary conditions. This automatic method needs a single simulation to decide both the integer and fractional width of every signal. Our method accelerates the process, showing an advantage over manual methods and those requiring multiple simulations. The proposed method is applied to create all the WL assignments to the signals involved in a fixed-point coded buck converter model, which shows its feasibility.

Nowadays, the use of the hardware in the loop (HIL) simulation has gained popularity among researchers all over the world. One of its main applications is the simulation of power electronics converters. However, the equipment designed for this purpose is difficult to acquire for some universities or research centers, so ad-hoc solutions for the implementation of HIL simulation in low-cost hardware for power electronics converters is a novel research topic. However, the information regarding implementation is written at a high technical level and in a specific language that is not easy for non-expert users to understand. In this paper, a systematic methodology using LabVIEW software (LabVIEW 2018) for HIL simulation is shown. A fast and easy implementation of power converter topologies is obtained by means of the differential equations that define each state of the power converter. Five simple steps are considered: designing the converter, modeling the converter, solving the model using a numerical method, programming an off-line simulation of the model using fixed-point representation, and implementing the solution of the model in a Field-Programmable Gate Array (FPGA). This methodology is intended for people with no experience in the use of languages as Very High-Speed Integrated Circuit Hardware Description Language (VHDL) for Real-Time Simulation (RTS) and HIL simulation. In order to prove the methodology’s effectiveness and easiness, two converters were simulated—a buck converter and a three-phase Voltage Source Inverter (VSI)—and compared with the simulation of commercial software (PSIM® v9.0) and a real power converter.

Power electronics medium-voltage (MV) systems must comply with the requirements defined in grid codes. These systems’ compatibility with the standards can be validated by specialized testing equipment: grid simulators. This paper presents a hardware in the loop (HiL) implementation and the simulation results of a MV multiphase DC/DC converter designed for MV DC grid emulation. By using ABB’s reliable, patented power converter hardware topology (US 10978948 B2) and by applying advanced control algorithms, the presented system can be used for special purposes, such as the emulation of fault events in a DC-grid used for the certification of other devices, or for other research goals. The presented concept of a power electronics DC-grid simulator (PEGS-DC) is characterized by high power capability and high voltage quality. In this paper, the general idea of a power electronics grid simulator applied for the testing of MV electrical systems is discussed. Then, details related to the PEGS-DC, such as its hardware topology and the applied modulation method are presented. Subsequently, the HiL setup is described. The main scope of this article focuses on model the description and presenting recorded HiL simulations.