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Dissertations / Theses on the topic 'Power processing'
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1
Gandu, Kondalarao. "Power processing for electrostatic microgenerators." Thesis, Imperial College London, 2011. http://hdl.handle.net/10044/1/6995.
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Microgenerators are electro-mechanical devices which harvest energy from local environmental from such sources as light, heat and vibrations. These devices are used to extend the life-time of wireless sensor network nodes. Vibration-based microgenerators for biomedical applications are investigated in this thesis. In order to optimise the microgenerator system design, a combined electro-mechanical system simulation model of the complete system is required. In this work, a simulation toolkit (known as ICES) has been developed utilising SPICE. The objective is to accurately model end-to-end microgenerator systems. Case-study simulations of electromagnetic and electrostatic microgenerator systems are presented to verify the operation of the toolkit models. Custom semiconductor devices, previously designed for microgenerator use, have also been modelled so that system design and optimisation of complete microgenerator can be accomplished. An analytical framework has been developed to estimate the maximum system effectiveness of an electrostatic microgenerator operating in constant-charge and constant-voltage modes. The calculated system effectiveness values are plotted with respect to microgenerator sizes for different input excitations. Trends in effectiveness are identified and discussed in detail. It was found that when the electrostatic transducer is interfaced with power processing circuit, the parasitic elements of the circuit are reducing the energy generation ability of the transducer by sharing the charge during separation of the capacitor plates. Also, found that in constant-voltage mode the electrostatic microgenerator has a better effectiveness over a large operating range than constant-charge devices. The ICES toolkit was used to perform time-domain simulation of a range of operating points and the simulation results provide verification of the analytical results.
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Jayasooriya, Sriyani Dhammika. "High power ultrasound in meat processing /." [St. Lucia, Qld.], 2005. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe19070.pdf.
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Farag, Emad N. "VLSI low-power digital signal processing." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq22199.pdf.
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Guo, Yan. "Real-time parallel processing for power applications." Thesis, McGill University, 1993. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=41602.
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The thesis describes the design, implementation and applications of two multiprocessor systems. A Multiprocessor Controller and an Extensible Modular Multiprocessor System have been built and have been used to solve problems of real-time digital control and real-time digital simulation in the power electronics and power systems areas.The Multiprocessor Controller, built around three fixed-point digital signal processors(DSPs), has been used in real-time parallel processing to control a voltage-source type pulse-width-modulated power converter. In a pole-placement control strategy with a state observer, the converter has been stabilized with its dc link capacitance reduced by a factor of as much as 120, thus making the converter a potentially practical device for High Voltage direct current transmission.
The Extensible Modular Multiprocessor System consists of modules which can be easily added in a mesh architecture to provide more computing power. Each module consists of one or two autonomous processing units (PUs) and the supporting control/interface circuits. A prototype of three modules (five floating-point DSPs) has been built and used in parallel processing to simulate a small power system with two turbo-generators operating in real time as a Transient Network Analyzer(TNA).
The power system equations are partitioned by using a new method in which the system is modeled as an interconnection of functional blocks. The power system is simulated by an interconnection of DSP modules, with one module simulating one block. The results of elaborate tests demonstrate the correctness of: (a) the new partitioning method, and (b) the design and operation of the Extensible Modular Multiprocessor System. The results further show that the new partitioning method together with the Extensible Modular Multiprocessor System form a promising approach to digitize the Transient Network Analyzer.
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Cid-Pastor, Ángel. "Energy processing by means of power gyrators." Doctoral thesis, Universitat Politècnica de Catalunya, 2005. http://hdl.handle.net/10803/6337.
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En aquesta tesi doctoral es presenta un mètode sistemàtic per a la síntesi de giradors de potència. A partir d'aquest mètode s'han generat i classificat diverses estructures giradores. Cadascun d'aquests giradors, que poden tenir característiques diferents, pot ser útil en diferents aplicacions.Des d'un punt de vista circuital, es tracta d'una estructura de dos ports que es caracteritza per algun d'aquests dos grups d'equacions: 1) I1=gV2, I2=gV1 , 2) V1=rI2, V2=rI1, on I1, V1, i I2, V2 són els valors en contínua corresponents als valors de tensió i corrent als ports d'entrada i sortida respectivament, essent g (r) la conductància (resistència) del girador.
En aquesta tesi, les estructures giradores de potència s'han classificat en funció de com transformen una font d'excitació al port d'entrada en la seva representació dual al port de sortida. Segons aquesta classificació es poden distingir tres tipus de giradors: 1) girador de potència de tipus G, 2) girador de potència de tipus G amb corrent d'entrada controlada i 3) giradors de potència de tipus R. Les categories 1 i 2 són les dues possibles solucions de síntesi de les equacions (1), mentre que la categoria 3 correspon a la solució de síntesi de les equacions (2).
A més a més, no existeixen estudis sistemàtics on basant-se en les equacions de definició s'arribi finalment a una verificació experimental. En aquesta tesi es presenta el disseny i anàlisi dels giradors que s'han presentat. L'anàlisi cobreix exhaustivament l'estudi tant del comportament dinàmic com estàtic dels giradors presentats. Aquests giradors es poden considerar com estructures canòniques per al processat de potència.
A més a més, es presenten algunes funcions bàsiques del processat de potència realitzades amb giradors de potència. Com per exemple: conversió tensió-corrent, corrent-tensió, adaptació d'impedàncies i regulació de tensió.
Les característiques de cada girador depenen no només de la topologia convertidora sinó també del funcionament del control del convertidor. S'han investigat dos tècniques de control: el control en mode lliscant i el control no lineal basat en dinàmica zero. Per tant, les estructures giradores proposades poden treballar tant a freqüència constant com a freqüència variable.
Finalment s'han verificat les previsions teòriques mitjançant simulació i verificació experimental.
In this thesis, a systematic approach to the synthesis of power gyrators is presented. Based on this approach, several gyrator structures can be generated and classified. Each of these gyrators has its own features and is suitable of different applications.
From a circuit standpoint, a power gyrator is a two-port structure characterized by any of the following two set of equations: 1) I1=gV2, I2=gV1 , 2) V1=rI2, V2=rI1, where I1, V1, and I2, V2 are DC values of current and voltage at input and output ports respectively and g ( r ) is the gyrator conductance ( resistance ).
In this thesis, power gyrator structures are classified by the manner they transform an excitation source at the input port into its dual representation at the output port. Based on this classification, there exist three types of power gyrators: 1) power gyrators of type G, 2) power gyrators of type G with controlled input current and 3) power gyrators of type R. Categories 1 and 2 are the two possible synthesis solutions to the set of equations ( 1 ) while category 3 corresponds to the synthesis solution of ( 2 ).
Thus far, no systematic works have been done starting at the definition equations and ending at the experimental verification. In this thesis, the analysis and design for the disclosed power gyrators are presented. The analysis covers exhaustingly the study of both static and dynamic behavior of the reported power gyrators. These power gyrators presented can be considered as canonical structures for power processing.
Thus, some basic power processing functions done by the presented power gyrators are reported. Namely, voltage to current conversion, current to voltage conversion, impedance matching and voltage regulation.
The performance characteristics of a power gyrator depend not only on the circuit topology but also depend on the converter control operation.
Hence, two main control schemes are investigated, namely, sliding-mode control schemes and zero-dynamics-based PWM nonlinear control. Therefore, the proposed gyrator structures can operate indistinctly at constant or at variable switching frequency.
In addition, experimental and computer simulation results of the power gyrators presented are given in order to verify the theoretical predictions.
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Zaidi, Syed Izhar Hussain. "Power Efficient Signal Processing in Reconf0igurable Computing." Thesis, University of Bristol, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.520204.
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Ebrahimian, Mohammad Reza. "Power system operations : state estimation distributed processing /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Ramadass, Yogesh Kumar. "Energy processing circuits for low-power applications." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/63026.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 199-205).
Portable electronics have fueled the rich emergence of new applications including multi-media handsets, ubiquitous smart sensors and actuators, and wearable or implantable biomedical devices. New ultra-low power circuit techniques are constantly being proposed to further improve the energy efficiency of electronic circuits. A critical part of these energy conscious systems are the energy processing and power delivery circuits that interface with the energy sources and provide conditioned voltage and current levels to the load circuits. These energy processing circuits must maintain high efficiency and reduce component count for the final solution to be attractive from an energy, size and cost perspective. The first part of this work focuses on the development of on-chip voltage scalable switched capacitor DC-DC converters in digital CMOS processes. The converters are designed to deliver regulated scalable load voltages from 0.3V up to the battery voltage of 1.2V for ultra-dynamic voltage scaled systems. The efficiency limiting mechanisms of these on-chip DC-DC converters are analyzed and digital circuit techniques are proposed to tackle these losses. Measurement results from 3 test-chips implemented in 0.18pm and 65nm CMOS processes will be provided. The converters are able to maintain >75% efficiency over a wide range of load voltage and power levels while delivering load currents up to 8mA. An embedded switched capacitor DC-DC converter that acts as the power delivery unit in a 65nm subthreshold microcontroller system will be described. The remainder of the thesis deals with energy management circuits for battery-less systems. Harvesting ambient vibrational, light or thermal energy holds much promise in realizing the goal of a self-powered system. The second part of the thesis identifies problems with commonly used interface circuits for piezoelectric vibration energy harvesters and proposes a rectifier design that gives more than 4X improvement in output power extracted from the piezoelectric energy harvester. The rectifier designs are demonstrated with the help of a test-chip built in a 0.35pm CMOS process. The inductor used within the rectifier is shared efficiently with a multitude of DC-DC converters in the energy harvesting chip leading to a compact, cost-efficient solution. The DC-DC converters designed as part of a complete power management solution achieve efficiencies of greater than 85% even in the micro-watt power levels output by the harvester. The final part of the thesis deals with thermal energy harvesters to extract electrical power from body heat. Thermal harvesters in body-worn applications output ultra-low voltages of the order of 10's of milli-volts. This presents extreme challenges to CMOS circuits that are powered by the harvester. The final part of the thesis presents a new startup technique that allows CMOS circuits to interface directly with and extract power out of thermoelectric generators without the need for an external battery, clock or reference generators. The mechanically assisted startup circuit is demonstrated with the help of a test-chip built in a 0.35pm CMOS process and can work from as low as 35mV. This enables load circuits like processors and radios to operate directly of the thermoelectric generator without the aid of a battery. A complete power management solution is provided that can extract electrical power efficiently from the harvester independent of the input voltage conditions. With the help of closed-loop control techniques, the energy processing circuit is able to maintain efficiency over a wide range of load voltage and process variations.
by Yogesh Kumar Ramadass.
Ph.D.
9
Denning, Paul Michael. "High power laser surface processing of hydroxyapatite." Thesis, University of Liverpool, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.399182.
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Nisar, Muhammad Mudassar. "Robust low-power signal processing and communication algorithms." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33872.
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This thesis presents circuit-level techniques for soft error mitigation, low-power design with performance trade-off, and variation-tolerant low-power design. The proposed techniques are divided into two broad categories. First, error compensation techniques, which are used for soft error mitigation and also for low-power operation of linear and non-linear filters. Second, a framework for variation tolerant low-power operation of wireless devices is presented. This framework analyzes the effects of circuit "tuning knobs" such as voltage, frequency, wordlength precision, etc. on system performance, and power efficiency. Process variations are considered as well, and the best operating tuning knob levels are determined, which results in maximum system wide power savings while keeping the system performance within acceptable limits. Different methods are presented for variation-tolerant and power-efficient wireless communication. Techniques are also proposed for application driven low-power operation of the OFDM baseband receiver.
11
Farrant, Luke. "Gallium nitride processing for high power microwave devices." Thesis, Cardiff University, 2005. http://orca.cf.ac.uk/56118/.
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This thesis contains literature reviews relating to inductively coupled plasmas and their use in etching gallium nitride with chlorine based plasmas. The properties of gallium nitride, how these properties make gallium nitride a suitable material for high power microwave transistors and how such transistors will help improve the systems in which they might be used are also reviewed. In this thesis, a novel, non-destructive method of measurement of the conductivity of a semiconductor through measurement of the increase in the bandwidth of the resonant peak of a microwave dielectric resonator when it is brought near a semiconductor wafer is presented. Using this method the conductivity of a thin gallium nitride film is obtained and found to be within the expected range it was found to be very difficult to measure the conductivity of this gallium nitride wafer using a four-point probe, as the film was too thin. Also presented in this thesis are studies of the etch characteristics of gallium nitride and photoresist in mixed boron trichloride and chlorine plasmas generated in two Oxford Instruments inductively coupled plasma etchers (ICP 180 and 380). The ICP 380 was used to etch the mesa isolation of gallium nitride based heteroj unction field effect transistors that were fabricated at Cardiff University. A method of making the angle of the mesa sidewall acute by melting of the photoresist is presented. An acute mesa-sidewall angle facilitated the easy traverse of the mesa edge by the gate metal. Characterisations of ohmic and Schottky contacts that were fabricated as part of the effort to produce a working gallium nitride based heteroj unction field effect transistor are presented and reasons given for the failure of some of the ohmic contacts. The dc characteristics of the best transistor fabricated during the project are presented.
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Xie, Jianping. "The influence of power ultrasound on leather processing." Thesis, University of Northampton, 1998. http://nectar.northampton.ac.uk/2662/.
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The effects of ultrasound (38 kHz, 1.3 W cm2) on the dyeing, fatliquoring and tanning of leather have been investigated and the mechanisms whereby ultrasound influences these processes were elucidated. Compared with a conventional process, ultrasonic dyeing can either shorten the dyeing time by 40-70% or facilitate low temperature dyeing. This remarkable enhancing effect has been attributed mainly to an increased diffusion coefficient (D) of dyestuff in the presence of ultrasound. It was found that sonication is more effective in the initial phases than in the late phases of the dyeing process. Application of ultrasound during the fatliquoring process or simply in the preparation of fatliquors resulted in an increase of leather fat contents (up to 40%), especially in the inner corium layer, indicating an improved penetration. This can be partly attributed to a reduction of particle size by 20-30%. In contrast to dyeing, ultrasound was found to be more effective later rather than earlier in the fatliquoring process. Chromium and aldehyde tanning processes were accelerated only marginally (1 0%) but the mimosa tanning process was speeded up significantly (by up to 100%) by using ultrasound. Leathers tanned in the presence of ultrasound had shrinkage temperatures 3-5°C higher than conventionally processed controls. A more even chromium distribution and less chromium leaching were obtained after using ultrasound. The results showed that ultrasound can increase the dispersion rate and the available tannin content (by 7%) of mimosa, as well as reducing its particle size by 50%. It was also found that ultrasonic treatment can prevent mould from growing on mimosa tanned leathers. It is concluded that ultrasound is more effective in a process which involves a colloidal rather than a true solution system. The prevailing effects of ultrasound on the former processes are to increase the diffusion coefficient and reduce the aggregation. This is due to cavitation
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Xu, Lin. "Data modeling and processing in deregulated power system." Online access for everyone, 2005. http://www.dissertations.wsu.edu/Dissertations/Spring2005/l%5Fxu%5F022805.pdf.
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Farrington, Richard W. "Novel concepts in high-frequency resonant power processing." Diss., This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-05222007-091356/.
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Guha, Majumdar Mrittunjoy. "Quantum information processing using the power-of-SWAP." Thesis, University of Cambridge, 2019. https://www.repository.cam.ac.uk/handle/1810/288005.
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This project is a comprehensive investigation into the application of the exchange interaction, particularly with the realization of the SWAP^1/n quantum operator, in quantum information processing. We study the generation, characterization and application of entanglement in such systems. Given the non-commutativity of neighbouring SWAP^1/n gates, the mathematical study of combinations of these gates is an interesting avenue of research that we have explored, though due to the exponential scaling of the complexity of the problem with the number of qubits in the system, numerical techniques, though good for few-qubit systems, are found to be inefficient for this research problem when we look at systems with higher number of qubits. Since the group of SWAP^1/n operators is found to be isomorphic to the symmetric group Sn, we employ group-theoretic methods to find the relevant invariant subspaces and associated vector-states. Some interesting patterns of states are found including onedimensional invariant subspaces spanned by W-states and the Hamming-weight preserving symmetry of the vectors spanning the various invariant subspaces. We also devise new ways of characterizing entanglement and approach the separability problem by looking at permutation symmetries of subsystems of quantum states. This idea is found to form a bridge with the entanglement characterization tool of Peres-Horodecki's Partial Positive Transpose (PPT), for mixed quantum states. We also look at quantum information taskoriented 'distance' measures of entanglement, besides devising a new entanglement witness in the 'engle'. In terms of applications, we define five different formalisms for quantum computing: the circuit-based model, the encoded qubit model, the cluster-state model, functional quantum computation and the qudit-based model. Later in the thesis, we explore the idea of quantum computing based on decoherence-free subspaces. We also investigate ways of applying the SWAP^1/n in entanglement swapping for quantum repeaters, quantum communication protocols and quantum memory.
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Xu, Kuang Ph D. Massachusetts Institute of Technology. "On the power of centralization in distributed processing." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66480.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 84-85).
In this thesis, we propose and analyze a multi-server model that captures a performance trade-off between centralized and distributed processing. In our model, a fraction p of an available resource is deployed in a centralized manner (e.g., to serve a most-loaded station) while the remaining fraction 1 -p is allocated to local servers that can only serve requests addressed specifically to their respective stations. Using a fluid model approach, we demonstrate a surprising phase transition in the steady-state delay, as p changes: in the limit of a large number of stations, and when any amount of centralization is available (p > 0), the average queue length in steady state scales as log 1/1-p 1/1-[lambda] when the traffic intensity [lambda] goes to 1. This is exponentially smaller than the usual M/M/1-queue delay scaling of 1/1-[lambda], obtained when all resources are fully allocated to local stations (p = 0). This indicates a strong qualitative impact of even a small degree of centralization. We prove convergence to a fluid limit, and characterize both the transient and steady-state behavior of the finite system, in the limit as the number of stations N goes to infinity. We show that the sequence of queue-length processes converges to a unique fluid trajectory (over any finite time interval, as N --> [infinity]), and that this fluid trajectory converges to a unique invariant state vI, for which a simple closedform expression is obtained. We also show that the steady-state distribution of the N-server system concentrates on vI as N goes to infinity.
by Kuang Xu.
S.M.
17
Ludwig, Jeffrey Thomas 1968. "Low power digital filtering using adaptive approximate processing." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/42766.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (p. 167-173).
by Jeffrey Thomas Ludwig.
Ph.D.
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潘淑欣 and Shuk-yan Poon. "A decentralized multi-agent system for restructured power system operation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31219810.
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Young, Chung-Ping. "Digital power metering manifold /." free to MU campus, to others for purchase, 1997. http://wwwlib.umi.com/cr/mo/fullcit?p9842576.
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Yang, Hong-Kui. "Low-power oversampled signal processing for digital radio receivers." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0005/NQ32351.pdf.
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Hodgers, Philip Thomas. "Pre-processing techniques for electromagnetic & power analysis attacks." Thesis, Queen's University Belfast, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.602543.
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The research presented in this thesis has led to several new pre-processing techniques that enhance side-channel analysis of near-field electromagnetic (EM) and power analysis waveforms. Three new power spectral density analysis techniques have been introduced, the sliding window, the overlapping window and the variable window methods. These approaches pre-process the information in the time-shift invariant frequency domain, overcoming issues of misalignment due to acquisition error or random insertion type countermeasures. A new pattern analysis technique, that models the charge and decay profiles of AES power consumption traces, has been shown to defeat a random clocking countermeasure. The individual rounds of the algorithm are identified, enabling the targeted round to be extracted from each trace. A further optimisation is demonstrated using a round separation metric to identify prior rounds where a sufficient power consumption decay has occurred, resulting in a further reduction in the number of traces required. The attack therefore overcomes the effects of the temporal misalignment and round amplitude variation caused by the random clocking countermeasure. The novel application of a DSP implementation of a phase-sensitive detector circuit has enabled the pre-processing of side-channel information to enhance the round patterns of an AES algorithm for the purposes of re-alignment and cryptographic signature extraction. The identification of locations on a device where the encryption signature is more readily visible, leads to a more efficient targeting of attacks in a side-channel cartography attack.
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Law, Victor John. "Radio frequency plasma power spectroscopy for semiconductor device processing." Thesis, University of Ulster, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.413866.
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Tsang, Tony Ka Leong. "Low power weak current processing for weak biomedical applications /." View abstract or full-text, 2008. http://library.ust.hk/cgi/db/thesis.pl?ECED%202008%20TSANG.
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Chang, Arthur Hsu Chen. "Power processing and active protection for photovoltaic energy extraction." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/97330.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 203-206).
Solar photovoltaic power generation is a promising clean and renewable energy technology that can draw upon the planet's most abundant power source - the sun. However, relatively high levelized cost of energy (LCOE), the ratio of the total cost of ownership to the total energy extracted over the lifetime of the generation system, has limited the grid penetration of solar power. Mismatch loss remains an important issue to address in PV systems, and a solar power system can lose as much as 30% of its energy generation capability over a year due to mismatch. Maximum power point tracking (MPPT) using power electronics converters can increase the overall solar energy extraction efficiency and thus reduce the LCOE. Many power electronics solutions have been proposed at the module and submodule levels, which only partially addresses the mismatch problem. However, scaling the existing solutions to finer optimization granularity has been cost-prohibitive. In the first part of this thesis, a new cell-level strategy, termed diffusion charge redistribution (DCR), is proposed to fully recover mismatch loss. The proposed technique processes power by leveraging the intrinsic solar cell capacitance rather than relying on externally added intermediate energy storage in order to drastically reduce to the cost of MPPT while enabling the finest optimization granularity. Moreover, strings balanced by this technique exhibit power versus current curves that are convex, which simplifies the required MPPT algorithm. Cell-level power balancing may also ease the testing and binning criteria during manufacturing, which leads to additional cost savings. Differential power processing (DPP) is a key concept to further improve energy efficiency by minimizing the amount of power conversion. In the second part of this thesis, the concept of differential power processing is introduced to the proposed cell-level power balancing technique by rethinking the string-level power electronics architecture. This enhancement can improve the overall efficiency of DCR by more than 3.5% while permitting the use of a slower DCR switching frequency. It can also be applied to many other cascaded converter architectures to reduce insertion loss. In particular, the proposed differential DCR (dDCR) architecture simultaneously achieves maximum power point tracking without any external passive components at the cell-level, and maintains differential power processing with zero insertion loss. This is accomplished by decoupling the MPPT functional block from the DPP functional block. The new power optimization aims to not only maximize energy extraction from each solar cell but also minimize the amount of processed power. The new multi-variable optimization space for the dDCR topology is evaluated and shown to be convex, which simplifies the required optimization algorithm. The inverter represents a large part of the overall cost and is often the most failure-prone component in a photovoltaic power system. In order to improve the cost and reliability of a grid-tie inverter, switched-capacitor techniques are adopted to reduce the required capacitance and rated voltage of the dc-link capacitor. The proposed switched-capacitor energy buffer can improve capacitor energy utilization by more than four times for a system with a 10% peak-to-peak ripple specification, and enable the use of film or ceramic capacitors to prolong the system lifetime to over a hundred years. The third part of this thesis explores the SC energy buffer design space and examines tradeoffs regarding circuit topology, switching configuration, and control complexity. Practical applications require control schemes capable of handling source and load transients. A two-step control methodology that mitigates undesirable transient responses is proposed and demonstrated in simulation. Finally, dc power system architectures have attracted interest as a means for achieving high overall efficiency and facilitating integration of renewable and distributed energy sources, such as a photovoltaic system. However, to enable widespread adoption of dc systems, the reliability of fault protection and interruption capability is essential. A new dc breaker topology, called the series-connected Z-source circuit breaker, is introduced to minimize the reflected fault current drawn from a source while retaining a common return ground path. Analogous in some respects to an ac thermal-magnetic breaker, the proposed Z-source breaker can be designed for considerations affecting both rate of fault current rise and absolute fault current level. The proposed manual tripping mechanism also enables protection against both instantaneous large surges in current and longer-term over-current conditions.
by Arthur Hsu Chen Chang.
Ph. D.
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Ihlenfeld, Lucas Pioli Rehbein Kürten. "Power transformer passivity enforcement : pre- and post-processing approaches." reponame:Repositório Institucional da UFPR, 2015. http://hdl.handle.net/1884/41195.
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Orientador : Prof. Dr. Gustavo Henrique da Costa OliveiraDissertação (mestrado) - Universidade Federal do Paraná, Setor de Tecnologia, Programa de Pós-Graduação em Engenharia Elétrica. Defesa: Curitiba, 14/09/2015
Inclui referências : f. 86-94
Resumo: Esta dissertação trata, em bases matemáticas, do estudo das técnicas de aferição e imposição da passividade, uma propriedade qualitativa, geral e fundamental de transformadores. Para esse propósito, são propostas duas novas abordagens: uma de perturbação de dados no domínio da frequência, chamada pré-processamento, bem como um novo procedimento de perturbação de parâmetros no domínio do tempo, denominado pós-processamento. Inicialmente, métodos de aferição da passividade são empregados para distinguir sistemas passivos dos não-passivos bem como caracterizar as violações. Verificadas violações de passividade nos dados, usualmente devidas ao processo de medição, estes mesmos dados são perturbados, configurando o pré-processamento, de modo que todas as violações sejam suprimidas. Tal procedimento envolve encontrar matrizes de perturbação que, em cada frequência, atinjam esse objetivo causando, ao mesmo tempo, e em certo sentido, a menor perturbação possível. Os dados já passivos podem ser identificados e um modelo então obtido. Como dados passivos não garantem a obtenção de um modelo passivo, faz-se mister a imposição da passividade ao modelo obtido. Apesar de conduzir a resultados mais precisos, o pré-processamento de dados não é condição sine qua non para obtenção de modelos passivos. O procedimento de pós-processamento _e que, per se, assegura a passividade, permitindo que este seja empregado de forma independente daquele. Por meio de resultados obtidos com dados experimentais, demonstra-se, de forma individual e conjunta, a validade das técnicas ora propostas. Palavras-chave: Transformadores de Potência, Perturbação de dados, Perturbação de Parâmetros , Passivity-Enforcement, Modelagem, Análise de Transitórios.
Abstract: This dissertation addresses the problem concerning the mathematical assessment and enforcement of passivity, a qualitative, general and fundamental property of power transformers. For serving that purpose, two novel approaches are introduced: a pre-processing approach consisting of frequency-domain data perturbation as well as a post-processing one comprising a time-domain parameter perturbation. Initially, passivity assessment methods can be used to distinguish passive systems from non-passive ones and characterize passivity violations. As data can reveal passivity violations owing to the data acquisition process, it is pre-processed so that violations be suppressed. This procedure entails finding a data perturbation matrix that achieves such objective and causes a least possible perturbation, in some sense. Passive data can be identified and a model then extracted. Since passive data does not ensure the extraction of a passive model whatsoever, the employment of passivity enforcement is an indispensable resource for fully guaranteed model passivity. Despite leading to more accurate results, pre-processing is not a sine qua non for obtaining passive models. It is passivity enforcement that per se ensures model passivity, thus allowing post-processing to be used regardless of pre-processing. Underpinned by results achieved upon experimental data, the effectiveness of the methods herein proposed are individually and jointly confirmed. Key-words: Power Transformers, Data Perturbation, Model Parameter Perturbation, Passivity-Enforcement, Modelling, Transient Analysis.
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Ji, Alex. "Algorithms and low-power hardware for image processing applications." Thesis, Massachusetts Institute of Technology, 2018. https://hdl.handle.net/1721.1/121835.
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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018Cataloged from PDF version of thesis.
Includes bibliographical references (pages 69-71).
Image processing has become more important with the ever increasing amount of available image data. This has been accompanied by the development of new algorithms and hardware. However, dedicated hardware is often required to run these algorithms efficiently and conversely, algorithms need to be developed to exploit the benefits of the new hardware. For example, depth cameras have been created to add a new dimension to human-computer interaction. They can benefit applications that can operate on the raw depth data directly, such as breath monitoring. As for new algorithms, convolutional neural networks (CNNs) have become the standard for difficult image processing tasks due to their high accuracy. But to execute them efficiently, we need new hardware to fully exploit the parallelism inherent in these computations. The first part of the thesis presents an algorithm for breath monitoring using a low-resolution time-of-flight camera. It consists of automatic region-of-interest detection, followed by frequency estimation. It can be accurate to within 1 breath per minute, comparing with a respiratory belt as reference. The second part presents a processing element (PE) for a neural network accelerator supporting compressed weights and using a new technique called factored computation. The PE consists of an accumulator array, row decoder, and output combination block. Modifications to the row decoder can allow for reconfigurability of the compressed weight bit-widths. Several common layer operations in CNNs are described and mapped onto the proposed hardware. An energy model of the design is formulated and verified by synthesizing and simulating a basic processing element containing an 8 x 20 accumulator array. Simulations show the proposed design achieves up to 4.5x reduction in the energy per MAC compared to a baseline 16-bit fixed-point MAC unit.
by Alex Ji.
S.M.
S.M. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
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Hicks, William T. "MULTI CHANNEL AC POWER MONITOR USING DIGITAL SIGNAL PROCESSING." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/608376.
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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, CaliforniaThe monitoring of multi phase 400 Hz aircraft power includes monitoring the phase voltages, currents, real powers, and frequency. This paper describes the design of a multi channel card that uses digital signal processing (DSP) to measure these parameters on a cycle by cycle basis. The card measures the average, peak, minimum cycle, and maximum cycle values of these parameters.
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Grey, David John. "Parallel solution of power system linear equations." Thesis, Durham University, 1995. http://etheses.dur.ac.uk/5429/.
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At the heart of many power system computations lies the solution of a large sparse set of linear equations. These equations arise from the modelling of the network and are the cause of a computational bottleneck in power system analysis applications. Efficient sequential techniques have been developed to solve these equations but the solution is still too slow for applications such as real-time dynamic simulation and on-line security analysis. Parallel computing techniques have been explored in the attempt to find faster solutions but the methods developed to date have not efficiently exploited the full power of parallel processing. This thesis considers the solution of the linear network equations encountered in power system computations. Based on the insight provided by the elimination tree, it is proposed that a novel matrix structure is adopted to allow the exploitation of parallelism which exists within the cutset of a typical parallel solution. Using this matrix structure it is possible to reduce the size of the sequential part of the problem and to increase the speed and efficiency of typical LU-based parallel solution. A method for transforming the admittance matrix into the required form is presented along with network partitioning and load balancing techniques. Sequential solution techniques are considered and existing parallel methods are surveyed to determine their strengths and weaknesses. Combining the benefits of existing solutions with the new matrix structure allows an improved LU-based parallel solution to be derived. A simulation of the improved LU solution is used to show the improvements in performance over a standard LU-based solution that result from the adoption of the new techniques. The results of a multiprocessor implementation of the method are presented and the new method is shown to have a better performance than existing methods for distributed memory multiprocessors.
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Liu, Xingsheng. "Processing and Reliability Assessment of Solder Joint Interconnection for Power Chips." Diss., Virginia Tech, 2001. http://hdl.handle.net/10919/26691.
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Circuit assembly and packaging technologies for power electronics have not kept pace with those for digital electronics. Inside those packaged power devices as well as the state-of-the-art power modules, interconnection of power chips is accomplished with wirebonds. Wirebonds in power devices and modules are prone to resistance, noise, parasitic oscillations, fatigue and eventual failure. Furthermore, there has been an increase demand for higher power density and better efficiency for power converters. Power semiconductor suppliers have been concentrating on improving device structure, density, and process technology to lower the on-resistance of MOSFETs and voltage drop of IGBTs. Recent advances made in power semiconductor technology are pushing packaging technology to the limits for performance of these power systems since the resistance and parasitics contribution by the package and the wirebonds are roughly the same as that on the silicon. In recent years, an integrated systems approach to standardizing power electronics components and packaging techniques in the form of power electronics building blocks has emerged as a new concept in the area of power electronics. As a result, it has been envisioned that the packaging of three-dimensional high-density multichip modules (MCMs) can meet the requirement for future power electronics systems. However, the conventional wirebond interconnected power devices are excluded from three-dimensional MCMs because of their large size, limited thermal management, and incompatible processing techniques. On the other hand, advanced solder joint area-array technologies, such as flip-chip technology, has emerged in microelectronics industry due to increased speed, higher packaging density, and performance, improved reliability and low cost these technologies offer. With all these benefits to offer, solder joint area-array technology has yet to be implemented for power electronics packaging. Therefore, the first objective of this study is to design and develop a solder joint area-array interconnection technique for power chips. Solder joint reliability is a major concern for area array technologies and power chip interconnection, thus the second objective of this study is to evaluate solder joint reliability, investigate the fatigue failure behavior of solder joint and improve solder joint reliability by developing a new solder bumping process for improved solder joint geometry, underfilling solder joint with encapsulant and applying flexible substrate in the assembly. The third objective is the implementation of solder joint interconnection technique in developing chip-scale power packages and a three-dimensional integrated power electronics module structure.
Solder joint area array interconnection for power chips has been designed with the considerations of parasitic resistance and inductance reduction, current handling capability, thermal management, reliability improvement and manufacturability. A new solder joint fabrication process, which is able to produce high standoff hourglass-shaped solder joint that consists of an inner cap, middle ball and outer cap, as well as the conventional solder bumping process have been successfully developed for power chips by using stencil printing. This solder bumping technology is compatible with the existing surface-mount assembly operations and potentially low cost. The fabricated solder joints have been characterized for their structure integrity, mechanical strength and electrical performances.
Solder joint reliability has been improved by optimizing solder joint geometry, underfilling flipped power chip and utilizing compliant substrate. Solder joint reliability was evaluated using accelerated temperate cycling and adhesion tests. The interfaces of the triple-stacked solder joints were examined using scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX) for the integrity of the joint. Acoustic microscopy imaging (nondestructive evaluation) was utilized to examine the quality of the bonded interfaces and to detect cracks and other defects before and during accelerated fatigue tests. Adhesion strength of both single bump barrel-shaped and stacked hourglass-shaped solder joints to bonding pads was characterized and analyzed. It was found that stacked hourglass-shaped solder joint have higher fracture stress than barrel-shaped solder joint. This verifies that hourglass-shaped solder joint has lower stress singularity at the interface between the solder bump and the silicon die as well as at the interface between the solder bump and substrate than barrel-shaped solder joint, especially around the corners of the interfaces. Furthermore, the adhesion strength of barrel-shaped solder joint decreases much faster than that of high standoff hourglass-shaped solder joint under temperature cycling, which indicates that the latter has high reliability than the former. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Solder joint geometry, underfilling and substrate flexibility were proved to affect solder joint reliability. The effects of solder joint shape and standoff height on reliability have been systematically studied experimentally for the first time. Our experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. The fatigue lifetime of high standoff hourglass-shaped solder joint is improved mainly by prolonged crack propagation time, with slight improvement in crack initiation time. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time. Underfilling and flexible substrate improved the lifetime of both barrel and hourglass-shaped solder joints. The effect of underfill on solder joint reliability is well known in microelectronics packaging field. However, for the first time, it is reported in this study that flex substrate could improve solder joint reliability. It has been found that flex substrate bucks during temperature cycling and thus reduces thermal strain in solder joints, which in turn improves solder joint fatigue lifetime.
Chip scale packaging can enable a few very important concepts and advantages in power electronics packaging. It offers high silicon to package footprint ratio, provides a known good die solution to power chips, improves electrical as well as thermal performance and creates an opportunity for power component standardization. Two kinds of chip-scale power packages have been developed in this research. One is called cavity down flip chip on flex; the other is termed Die Dimensional Ball Grid Array (D2BGA). Both utilize solder joint as chip-level interconnection. Electrical tests show that the VCE(sat) of the high speed IGBT chip-scale packages is improved by 20% to 30% by eliminating the device¡¯s wirebonds and other external interconnections, such as leadframe. Double-sided cooling is realized in these CSPs. Temperature cycling test shows that the CSPs are reliable.
Integrated power electronics modules (IPEMs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. We have developed a three-dimensional approach, termed flip chip on flex (FCOF), for packaging high-performance IPEMs. The new concept is based on the use of solder joint (D2BGA chip scale package), not bonding wires, to interconnect power devices. This packaging approach has the potential to produce modules having superior electrical and thermal performance and improved reliability. We have demonstrated the feasibility of this approach by constructing half-bridge converters (consisting of two IGBTs, two power diodes, and a simple gate driver circuitry) which have been successfully tested at power levels over 30 kW. Switching tests have shown that parasitic inductance of the FCOF module has been reduced by 40% to 50% over conventional wire bond power modules. Better thermal management can be achieved in this three-dimensional power module structure. Compared with the state-of-the-art half-bridge power modules, the volume of the half-bridge FCOF power module is reduced by at least 65%. Reliability test shows that this flip chip on flex power module structure is potentially more reliable than wire bond power module.Ph. D.
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Harrison, Paul Martin. "Industrial thin film processing applications of high peak power, high average power Nd:YAG laser systems." Thesis, Heriot-Watt University, 2012. http://hdl.handle.net/10399/2613.
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Three high speed thin film patterning applications have been investigated using a high average power, high peak power laser system. Throughout this work the spatial intensity profile of the laser output was tailored to produce more efficient results. The first application involved the development of rapid laser patterning of an indium tin oxide layer on a glass substrate in order to generate transparent electrodes for a flat panel display. This work showed that the stitch line that occurs in-between adjacent laser pulses was formed by redeposition of material via the plume generated by the second, slightly overlapping pulse which is deposited within the region of overlap, an area which has an increased surface temperature at that time. The second application, laser edge deletion for thin film solar photo-voltaic panels, was an investigation of whether dual wavelength processing was able to avoid introducing micro-cracks into the soda-lime glass substrate. The third application was an examination of high speed removal of an aluminium coating from a stainless steel substrate which demonstrated that the layer could be adequately removed but required a series of highly overlapped pulses.
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Wisell, David. "Measurement Techniques for Characterization of Power Amplifiers." Doctoral thesis, Stockholm : KTH School of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4566.
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Mehta, Mehul. "Power control for a mobile satellite system." Thesis, University of Southampton, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.245306.
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Kampfe, Sara Katherine. "Processing and Conversion of Algae to Bioethanol." W&M ScholarWorks, 2010. https://scholarworks.wm.edu/etd/1539626902.
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Næss, Hallvard. "A programmable DSP for low-power, low-complexity baseband processing." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2006. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9439.
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Software defined radio (SDR) is an emerging trend of radio technology. The idea is basically to move software as close to the antenna of a radio system as possible, to improve flexibility, adaptability and time-to-market. This thesis covers the description of a DSP architecture especially optimized for modulation / demodulation algorithms of low-complexity, low-power radio standards. The DSP allows software processing of these algorithms, making SDR possible. To make the DSP competitive to traditional ASIC modems, tough constraints are given for area and power consumption. Estimates done to indicate the power consumption, area and computational power of the DSP, shows that a software implementation of the studied physical layer should be possible within the given constraints.
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Henry, Michael Brewer. "Power Reduction of Digital Signal Processing Systems using Subthreshold Operation." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/33691.
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Over the past couple decades, the capabilities of battery-powered electronics has expanded dramatically. What started out as large bulky 2-way radios, wristwatches, and simple pacemakers, has evolved into pocket sized smart-phones, digital cameras, person digital assistants, and implantable biomedical chips that can restore hearing and prevent heart attacks. With this increase in complexity comes an increase in the amount of processing, which runs on a limited energy source such as a battery or scavenged energy. It is therefore desirable to make the hardware as energy efficient as possible. Many battery-powered systems require digital signal processing, which often makes up a large portion of the total energy consumption. The digital signal processing of a battery-powered system is therefore a good target for power reduction techniques. One method of reducing the power consumption of digital signal processing is to operate the circuit in the subthreshold region, where the supply voltage is lower than the threshold voltage of the transistors. Subthreshold operation greatly reduces the power and energy consumption, but also decreases the maximum operating frequency. Many digital signal processing applications have real-time throughput requirements, so various architectural level techniques, such as pipelining and parallelism, must be used in order to achieve the required performance.
This thesis investigates the use of parallelization and subthreshold operation to lower the power consumption of digital signal processing applications, while still meeting throughput requirements. Using an off the shelf fast fourier transform architecture, it will be shown that through parallelization and subthreshold operation, a 70 \% reduction in power consumption can be achieved, all while matching the performance of a nominal voltage single core architecture. Even better results can be obtained when an architecture is specifically designed for subthreshold operation. A novel Discrete Wavelet Transform architecture is presented that is designed to eliminate the need for memory banks, and a power reduction of 26x is achieved compared to a reference nominal voltage architecture that uses memory banks. Issues such as serial to parallel data distribution, dynamic throughput scaling, and memory usage are also explored in this thesis. Finally, voltage scaling greatly increases the design space, so power and timing analysis can be very slow due long SPICE simulation times. A simulation framework is presented that can characterize subthreshold circuits accurately using only fast gate level design automation tools.
Master of Science
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Bauer, Ralph Aaron. "Inorganic membranes for power generation and oxygen production." The Ohio State University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1556889103215598.
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Tsai, Men-Shen. "Intelligent systems for distribution operational planning and alarm processing in power systems /." Thesis, Connect to this title online; UW restricted, 1993. http://hdl.handle.net/1773/6106.
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Zhong, Shan. "Measurement calibration/tuning & topology processing in power system state estimation." Texas A&M University, 2003. http://hdl.handle.net/1969.1/1595.
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State estimation plays an important role in modern power systems. The errors in the telemetered measurements and the connectivity information of the network will greatly contaminate the estimated system state. This dissertation provides solutions to suppress the influences of these errors.
A two-stage state estimation algorithm has been utilized in topology error identification in the past decade. Chapter II discusses the implementation of this algorithm. A concise substation model is defined for this purpose. A friendly user interface that incorporates the two-stage algorithm into the conventional state estimator is developed.
The performances of the two-stage state estimation algorithms rely on accurate determination of suspect substations. A comprehensive identification procedure is described in chapter III. In order to evaluate the proposed procedure, a topology error library is created. Several identification methods are comparatively tested using this library.
A remote measurement calibration method is presented in chapter IV. The un-calibrated quantities can be related to the true values by the characteristic functions. The conventional state estimation algorithm is modified to include the parameters of these functions. Hence they can be estimated along with the system state variables and used to calibrate the measurements. The measurements taken at different time instants are utilized to minimize the influence of the random errors.
A method for auto tuning of measurement weights in state estimation is described in chapter V. Two alternative ways to estimate the measurement random error variances are discussed. They are both tested on simulation data generated based on IEEE systems. Their performances are compared. A comprehensive solution, which contains an initialization process and a recursively updating process, is presented.
Chapter VI investigates the errors introduced in the positive sequence state estimation due to the usual assumptions of having fully balanced bus loads/generations and continuously transposed transmission lines. Several tests are conducted using different assumptions regarding the availability of single and multi-phase measurements. It is demonstrated that incomplete metering of three-phase system quantities may lead to significant errors in the positive sequence state estimates for certain cases. A novel sequence domain three-phase state estimation algorithm is proposed to solve this problem.
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Zhang, Hai Bo. "High-frequency switching parallel processing topology for AC uninterruptible power supply." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ40215.pdf.
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Saab, Sami James. "Design of digital filters for low-power digital signal processing applications." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0001/MQ41376.pdf.
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Cosgrave, Joseph Anthony. "Acoustic-optic monitoring of electrical power equipment using chromatic signal processing." Thesis, University of Liverpool, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.263845.
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Bandyopadhyay, Abhishek. "Matrix transform imager architecture for on-chip low-power image processing." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-08192004-133909/unrestricted/bandyopadhyay%5Fabhishek%5F200412%5Fphd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.Smith, Mark, Committee Member ; DeWeerth, Steve, Committee Member ; Jackson, Joel, Committee Member ; David Anderson, Committee Member ; Hasler, Paul, Committee Chair. Includes bibliographical references.
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Wu, Yang. "Improved measurement placement and topology processing in power system state estimation." [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-1925.
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Ogweno, Austin Juma. "Power efficient, event driven data acquisition and processing using asynchronous techniques." Thesis, University of Newcastle upon Tyne, 2018. http://hdl.handle.net/10443/4121.
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Data acquisition systems used in remote environmental monitoring equipment and biological sensor nodes rely on limited energy supply soured from either energy harvesters or battery to perform their functions. Among the building blocks of these systems are power hungry Analogue to Digital Converters and Digital Signal Processors which acquire and process samples at predetermined rates regardless of the monitored signal's behavior. In this work we investigate power efficient event driven data acquisition and processing techniques by implementing an asynchronous ADC and an event driven power gated Finite Impulse Response (FIR) filter. We present an event driven single slope ADC capable of generating asynchronous digital samples based on the input signal's rate of change. It utilizes a rate of change detection circuit known as the slope detector to determine at what point the input signal is to be sampled. After a sample has been obtained it's absolute voltage value is time encoded and passed on to a Time to Digital Converter (TDC) as part of a pulse stream. The resulting digital samples generated by the TDC are produced at a rate that exhibits the same rate of change profile as that of the input signal. The ADC is realized in 0.35mm CMOS process, covers a silicon area of 340mm by 218mm and consumes power based on the input signal's frequency. The samples from the ADC are asynchronous in nature and exhibit random time periods between adjacent samples. In order to process such asynchronous samples we present a FIR filter that is able to successfully operate on the samples and produce the desired result. The filter also poses the ability to turn itself off in-between samples that have longer sample periods in effect saving power in the process.
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Caione, Carlo <1984>. "Ultra-low power WSNs: distributed signal processing and dynamic resource management." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2013. http://amsdottorato.unibo.it/5397/.
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This thesis presents several data processing and compression techniques capable of addressing the strict requirements of wireless sensor networks. After introducing a general overview of sensor networks, the energy problem is introduced, dividing the different energy reduction approaches according to the different subsystem they try to optimize.
To manage the complexity brought by these techniques, a quick overview of the most common middlewares for WSNs is given, describing in detail SPINE2, a framework for data processing in the node environment.
The focus is then shifted on the in-network aggregation techniques, used to reduce data sent by the network nodes trying to prolong the network lifetime as long as possible. Among the several techniques, the most promising approach is the Compressive Sensing (CS). To investigate this technique, a practical implementation of the algorithm is compared against a simpler aggregation scheme, deriving a mixed algorithm able to successfully reduce the power consumption.
The analysis moves from compression implemented on single nodes to CS for signal ensembles, trying to exploit the correlations among sensors and nodes to improve compression and reconstruction quality.
The two main techniques for signal ensembles, Distributed CS (DCS) and Kronecker CS (KCS), are introduced and compared against a common set of data gathered by real deployments. The best trade-off between reconstruction quality and power consumption is then investigated.
The usage of CS is also addressed when the signal of interest is sampled at a Sub-Nyquist rate, evaluating the reconstruction performance.
Finally the group sparsity CS (GS-CS) is compared to another well-known technique for reconstruction of signals from an highly sub-sampled version. These two frameworks are compared again against a real data-set and an insightful analysis of the trade-off between reconstruction quality and lifetime is given.
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Clarke, Jonathan A. "High-level power optimisation for digital signal processing in reconfigurable logic." Thesis, Imperial College London, 2008. http://hdl.handle.net/10044/1/4407.
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This thesis is concerned with the optimisation of Digital Signal Processing (DSP) algorithm implementations on reconfigurable hardware via the selection of appropriate word-lengths for the signals in these algorithms, in order to minimise system power consumption. Whilst existing word-length optimisation work has concentrated on the minimisation of the area of algorithm implementations, this work introduces the rst set of power consumption models that can be evaluated quickly enough to be used within the search of the enormous design space of multiple word-length optimisation problems. These models achieve their speed by estimating both the power consumed within the arithmetic components of an algorithm and the power in the routing wires that connect these components, using only a high-level description of the algorithm itself. Trading o a small reduction in power model accuracy for a large increase in speed is one of the major contributions of this thesis. In addition to the work on power consumption modelling, this thesis also develops a new technique for selecting the appropriate word-lengths for an algorithm implementation in order to minimise its cost in terms of power (or some other metric for which models are available). The method developed is able to provide tight lower and upper bounds on the optimal cost that can be obtained for a particular word-length optimisation problem and can, as a result, nd provably near-optimal solutions to word-length optimisation problems without resorting to an NP-hard search of the design space. Finally the costs of systems optimised via the proposed technique are compared to those obtainable by word-length optimisation for minimisation of other metrics (such as logic area) and the results compared, providing greater insight into the nature of wordlength optimisation problems and the extent of the improvements obtainable by them.
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Oubrahim, Zakarya. "On electric grid power quality monitoring using parametric signal processing techniques." Thesis, Brest, 2017. http://www.theses.fr/2017BRES0102/document.
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Cette thèse porte sur la surveillance des perturbations de la qualité de l’énergie d’un réseau électrique via des techniques paramétriques de traitement du signal. Pour élaborer nos algorithmes de traitement du signal, nous avons traité les problèmes d’estimation des différentes grandeurs du réseau électrique triphasé et de classification des perturbations de la qualité d'énergie. Pour ce qui est du problème d’estimation, nous avons développé une technique statistique basée sur le maximum de vraisemblance. La technique proposée exploite la nature multidimensionnelle des signaux électriques. Elle utilise un algorithme d’optimisation pour minimiser la fonction de vraisemblance. L’algorithme utilisé permet d’améliorer les performances d’estimation tout en étant d’une faible complexité calculatoire en comparaison aux algorithmes classiques. Une analyse plus poussée de l’estimateur proposé a été effectuée. Plus précisément, ses performances sont évaluées sous un environnement incluant entre autres la pollution harmonique et interharmonique et le bruit. Les performances sont également comparées aux exigences de la norme IEEE C37.118.2011. La problématique de classification dans les réseaux électriques triphasés a plus particulièrement concerné les perturbations que sont les creux de tension et les surtensions. La technique de classification proposée consiste globalement en deux étapes : 1) une pré-classification du signal dans l’une des 4 préclasses établis et en 2) une classification du type de perturbation à l’aide de l’estimation des composants symétriques.Les performances du classificateur proposé ont été évaluées, entre autres, pour différentes nombre de cycles, de SNR et de THD. L’estimateur et le classificateur proposés ont été validés en simulation et en utilisant les données d’un réseau électrique réel du DOE/EPRI National Database of Power System Events. Les résultats obtenus illustrent clairement l’efficacité des algorithmes proposés quand à leur utilisation comme outil de surveillance de la qualité d’énergieThis thesis deals with electric grid monitoring of power quality (PQ) disturbances using parametric signal processing techniques. The first contribution is devoted to the parametric spectral estimation approach for signal parameter extraction. The proposed approach exploits the multidimensional nature of the electrical signals.For spectral estimation, it uses an optimization algorithm to minimize the likelihood function. In particular, this algorithm allows to improve the estimation accuracy and has lower computational complexity than classical algorithms. An in-depth analysis of the proposed estimator has been performed. Specifically, the estimator performances are evaluated under noisy, harmonic, interharmonic, and off-nominal frequency environment. These performances are also compared with the requirements of the IEEE Standard C37.118.2011. The achieved results have shown that the proposed approach is an attractive choice for PQ measurement devices such as phasor measurement units (PMUs). The second contribution deals with the classification of power quality disturbances in three-phase power systems. Specifically, this approach focuses on voltage sag and swell signatures. The proposed classification approach is based on two main steps: 1) the signal pre-classification into one of 4 pre-classes and 2) the signature type classification using the estimate of the symmetrical components. The classifier performances have been evaluated for different data length, signal to noise ratio, interharmonic, and total harmonic distortion. The proposed estimator and classifier are validated using real power system data obtained from the DOE/EPRI National Database of Power System Events. The achieved simulations and experimental results clearly illustrate the effectiveness of the proposed techniques for PQ monitoring purpose
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Othman, Mohd Ridzal. "DSP-based active power filter." Thesis, Loughborough University, 1998. https://dspace.lboro.ac.uk/2134/6966.
Full textAbstract:
Harmonics in systems are conventionally suppressed using passive tuned filters, which have practical limitations in terms of the overall cost, size and performance, and these are particularly unsatisfactory when large number of harmonics are involved Active power filtering is an alternative approach in which the filter injects suitable compensation currents to cancel the harmonic currents, usually through the use of power electronic converters. This type of filter does not exhibit the drawbacks normally associated with its passive counterpart, and a large number of harmonics can be compensated by a single unit without incurring additional cost or performance degradation. This thesis investigates an active power filter configuration incorporating instantaneous reactive power theory to calculate the compensation currents. Since the original equations for determining the reference compensation currents are defined in two imaginary phases, considerable computation time is necessary to transform them from the real three-phase values. The novel approach described in the thesis minimises the required computation time by calculating the equations directly in terms of the phase values i. e. three-phase currents and voltages. Furthermore, by utilising a sufficiently fast digital signal processor ( DSP ) to perform the calculation, real-time compensation can be achieved with greater accuracy. The results obtained show that the proposed approach leads to further harmonic suppression in both the current and voltage waveforms compared to the original approach, due to considerable reduction in the computation time of the reference compensation currents.
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Yoo, Heejong. "Low-Power Audio Input Enhancement for Portable Devices." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6821.
Full textAbstract:
With the development of VLSI and wireless communication
technology, portable devices such as personal digital assistants
(PDAs), pocket PCs, and mobile phones have gained a lot of
popularity. Many such devices incorporate a speech recognition
engine, enabling users to interact with the devices using
voice-driven commands and text-to-speech synthesis.
The power consumption of DSP microprocessors has been
consistently decreasing by half about every 18 months, following
Gene's law. The capacity of signal processing, however, is still
significantly constrained by the limited power budget of these
portable devices. In addition, analog-to-digital (A/D) converters
can also limit the signal processing of portable devices. Many
systems require very high-resolution and high-performance A/D
converters, which often consume a large fraction of the limited
power budget of portable devices.
The proposed research develops a low-power audio signal
enhancement system that combines programmable analog signal
processing and traditional digital signal processing. By
utilizing analog signal processing based on floating-gate
transistor technology, the power consumption of the overall
system as well as the complexity of the A/D converters can be
reduced significantly. The system can be used as a front end of
portable devices in which enhancement of audio signal quality
plays a critical role in automatic speech recognition systems on
portable devices. The proposed system performs background audio
noise suppression in a continuous-time domain using analog
computing elements and acoustic echo cancellation in a
discrete-time domain using an FPGA.
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Ali, Ali Abbas. "Theory and assessment of an improved power spectral density estimator." Thesis, Cranfield University, 1990. http://dspace.lib.cranfield.ac.uk/handle/1826/4639.
Full textAbstract:
This thesis is concerned with the processing of time
domain signals received by a single sensor. An example of
such signals is the radar return, which is used in one way
or another to estimate the power spectral density a
frequency representation of the power of the signal in
order that we can pick up and track the moving targets.
since the POWER SPECTRAL DENSITY ESTIMATION is a fundamental
tool in digital signal processing, the theory of the
different approaches to PSDE is given in the Literature
review chapter.
The aim of this research is to develop a technique for
the Power Spectral Density Estimation (PSDE) of multiple
signals in white noise, which has high resolution capability
and less frequency estimation errors. Hence, the various
techniques mentioned above are tested for their detection,
resolution capabilities and performance.
Finally the different parameters affecting the resolution
and detection capabilities of the Eigen Vector Decomposition
Techniques (EVDT) for PSDE are studied in some depth.