Relevant bibliographies by topics / Power supply circuits

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Power supply circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Power supply circuits"

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He, Guo, Chao Jie Zhang, Guang Hui Chang, and Shu Hai Liang. "Testing Analog Circuits by PCA of Power Supply Current." Applied Mechanics and Materials 157-158 (February 2012): 641–45. http://dx.doi.org/10.4028/www.scientific.net/amm.157-158.641.

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A method using principal component analysis (PCA) of dynamic power supply current was proposed for testing of analog circuits in this paper. The basic model of the proposed method and the general rule for analog fault detection were described in detail. At first, the principal component model of fault-free circuits was constructed. Then the circuits-under-test was compared with the principal component model to calculate the statistic for fault detection. The features of power supply current in both time and frequency domain were combined by PCA, and it could overcome the difficulty to determine threshold by empirical knowledge. The proposed method was applied to detect faults of the signal filtering and amplifying circuit, which is used in the ultrasonic liquid-level sensor. The results show that the power supply current contains information about the circuit’s faults, and can be used for fault detection of analog circuits by analyzing this signal.
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LEHMANN, TORSTEN, HOSUNG CHUN, and YUANYUAN YANG. "POWER SAVING CIRCUIT DESIGN TECHNIQUES FOR IMPLANTABLE NEURO-STIMULATORS." Journal of Circuits, Systems and Computers 21, no. 06 (October 2012): 1240016. http://dx.doi.org/10.1142/s0218126612400166.

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Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. Second, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. A variation of this include passive charge recovery for further power reduction. In combination, significant implant power consumption reduction is achieved.
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N, Vengadeswari, and Priscilla Whitin. "Review a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power." International Journal of Engineering & Technology 7, no. 3.1 (August 4, 2018): 27. http://dx.doi.org/10.14419/ijet.v7i3.1.16790.

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In most case, charge pump circuit is designed based on capacitor, where voltage is increased at each stage depending on each stage voltage gain. Major elements are all charge pumps circuits one is Pumping capacitors and diode connected MOS.To increases pumping efficiency is very higher for each stage of charge pump circuits. Pumping efficiency are limiting by two parameters one is parasitic capacitance and threshold voltage. The power dissipated from the circuit can be increased by attain of leakage current .To resist this leakage in the circuits the supply voltage is major concern. To reduce the leakage with the help of power gating technique .Charge pump circuits are to be designed and verified by using tanner t-spice tools.
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Varetsky, Yuriy. "Overvoltages on power filters under energizing industrial power system transformer." Energy engineering and control systems 6, no. 2 (2020): 97–103. http://dx.doi.org/10.23939/jeecs2020.02.097.

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The practice of operating industrial power supply systems containing filter circuits has shown that filter tuning can have a significant impact on filter performance. On the basis of simulations of a real power supply system carried out by the Matlab / Simulink package, the results of a study of the impact of filter manufacturing tolerances on the filter transients under transformer energizing are presented. The most severe transients are observed for filter circuits in the power supply systems of electric arc furnaces due to frequently repeated operating energizing furnace transformers. This article summarizes the analysis of overvoltages on capacitors and reactors for various configurations of the filter circuit, arising during energizing the arc furnace transformer, taking into account the possible detuning of the filters.
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D., Vaithiyanathan, Megha Singh Kurmi, Alok Kumar Mishra, and Britto Pari J. "Performance analysis of multi-scaling voltage level shifter for low-power applications." World Journal of Engineering 17, no. 6 (August 17, 2020): 803–9. http://dx.doi.org/10.1108/wje-02-2020-0043.

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Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.
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Badalyan, N. P., D. P. Andrianov, A. A. Mitrofanov, E. A. Chashchin, S. A. Balashova, and G. V. Maslakova. "Power flows in multi-junction power supply circuits." MATEC Web of Conferences 336 (2021): 01008. http://dx.doi.org/10.1051/matecconf/202133601008.

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The article discusses a methodology that allows for an accurate calculation of the parameters of electrical equipment from the point of view of optimizing the power supply system. Taking into account the characteristics of transients processes makes it possible to select equipment in maximum load modes. Modeling of power flows caused by changes in the load of consumers is carried out on the example of calculating the power supply circuit of five junctions. It is shown that it is possible to change the direction of flows of transmitted electric power at certain ratios of parameters in individual elements of the circuit. Purpose of research: to show the possibility of changing the picture of the transmitted capacities by the elements of the power supply system, depending on consumer loads.
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Cao, Ruiping, and Jianping Hu. "Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits." Journal of Electrical and Computer Engineering 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/836019.

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In high-speed applications, MOS current mode logic (MCML) is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP). However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML) circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.
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Caselli, Michele, Marco Ronchi, and Andrea Boni. "Power Management Circuits for Low-Power RF Energy Harvesters." Journal of Low Power Electronics and Applications 10, no. 3 (September 19, 2020): 29. http://dx.doi.org/10.3390/jlpea10030029.

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The paper describes the design and implementation of power management circuits for RF energy harvesters suitable for integration in wireless sensor nodes. In particular, we report the power management circuits used to provide the voltage supply of an integrated temperature sensor with analog-to-digital converter. A DC-DC boost converter is used to transfer efficiently the energy harvested from a generic radio-frequency rectifier into a charge reservoir, whereas a linear regulator scales the voltage supply to a suitable value for a sensing and conversion circuit. Implemented in a 65 nm CMOS technology, the power management system achieves a measured overall efficiency of 20%, with an available power of 4.5 μW at the DC-DC converter input. The system can sustain a temperature measurement rate of one sample/s with an RF input power of −28 dBm, making it compatible with the power levels available in generic outdoor environments.
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Gramatikov, Pavlin, Roumen Nedkov, and Doino Petkov. "Secondary power systems for videometric complex "Fregat"." Aerospace Research in Bulgaria 30 (2018): 134–42. http://dx.doi.org/10.3897/arb.v30.e11.

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The power supply for the video-spectrometric complex (VSC) "Fregat" is being considered. This secondary power supply systems have the following functions: Reception and switching of the voltages; Protection from overload and short circuit in the internal circuits and the exit circuits; Transformation of primary voltage in stabilized secondary voltages; Galvanically untethered secondary circuits by primary and Hull; Protection of the users from the electromagnetic noises; Provision of "Cold" and "Hot" reserve, etc. A set of technical documentation and test-measuring equipment for testing were created. Four sets of Secondary Power Systems for "Fregat" are designed and implemented for two flights to planet Mars.
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Deng, An-Chang. "Power Estimation and Power Noise Analysis for CMOS Circuits." Journal of Circuits, Systems and Computers 07, no. 01 (February 1997): 17–30. http://dx.doi.org/10.1142/s0218126697000036.

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Power consumption is a primary concern for today's IC designers. However, determining an IC's power consumption is a difficult task, as consumption varies according to input stimulus conditions. This paper will focus on (1) the principal phenomena involved in the power consumption of CMOS circuits, (2) a brief survey of power estimation techniques, and (3) the effect of power-supply noise on circuit performance plus possible solutions to this problem.
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Dissertations / Theses on the topic "Power supply circuits"

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Ramadass, Yogesh Kumar. "An energy optimal power supply for digital circuits." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37922.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (p. 96-98).
The energy efficiency of digital circuits continues to be a major factor in determining the size and weight of battery-operated electronics. Integration of more functionality in a single system has made battery longevity a major problem. Operating circuits at their minimum energy operating voltage (MEP) has been proposed as a solution for energy critical applications where performance is not a key constraint. This thesis explores the sensitivity of the MEP to operating conditions and motivates the need for continuous minimum energy tracking based on the energy savings possible. A circuit that can dynamically track the MEP of a digital circuit with varying load conditions and temperature is presented. A low power, voltage scalable DC-DC converter is also embedded within the chip. The proposed minimum energy tracking algorithm uses a novel approach to sense the energy consumed per operation. The energy sensing circuitry does not use high-resolution Analog-to-Digital converters or high gain amplifiers. The energy estimate is used in a slope tracking algorithm to track the minimum energy operating voltage. The minimum energy tracking loop along with a low-voltage DC-DC converter and test circuitry were fabricated in a 65nm CMOS process.
(cont.) The circuits are powered from an external 1.2V supply. The digital test circuitry was capable of operation at voltages as low as 0.25V. The tracking of the minimum energy operating voltage with change in workload and temperature was observed. The DC-DC converter was able to deliver load voltages between 0.25V and 0.7V with an efficiency > 78% at load power levels of the order of 1 0.1W and above.
by Yogesh Kumar Ramadass.
S.M.
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O'Toole, Vincent. "A novel high frequency power supply for use in welding applications." Thesis, University of Liverpool, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.293140.

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Tate, D. "A microprocessor controlled error switching inverter used in the uninterruptible power supply environment." Thesis, University of Bath, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.275883.

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Choi, Jinseong. "Modeling of power supply noise in large chips using the finite difference time domain method." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/14977.

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Salem, Jebreel Mohamed Muftah. "A Reliable CMOS Receiver for Power Line Communications in Integrated Circuits." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/30942.

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Power line communications (PLC) in integrated circuits (ICs) was proposed by Dr. Dong S. Haâ group in 2005. Their goal was to utilize the power distribution network for data communications as well as delivery of power, so that the routing overhead can be avoided and the number of pins in the chip can be reduced. Dr. Haâ s group demonstrated through measurements the existence of pass-bands in the power distribution networks and the feasibility of power line communications in ICs. Several PLC receivers were developed to recover data superimposed on the power lines of an IC. This thesis research investigated a new PLC receiver to improve shortcomings of previous PLC receivers, specifically to improve the reliability while reducing power dissipation.

The proposed PLC system adopts an amplitude shift keying (ASK) modulation to transmit and detect data through power distribution networks. The proposed PLC receiver consists of three main sub-blocks. The first sub-block is a level shifter, which lowers the offset voltage of the supply voltage to approximately 0.5VDD. The second sub-block is a signal extractor, which detects a data signal superimposed on the power line. The signal extractor is a differential amplifier, in which one input is connected through an RC low-pass filter. The DC voltage of the data signal varies in accordance with the supply voltage fluctuations and droop. The low-pass filter intends to pass only the DC term of the data signal. Since the DC voltage is common for both inputs of the differential amplifier, it is removed from the data signal through the common mode rejection of the differential amplifier. Therefore, the signal extractor can mitigate supply voltage fluctuations and droops. The last sub-block is the logic restorer, which converts the differential signal to a logic value based on a Schmitt trigger. The hysteresis of the Schmitt trigger improves the noise immunity of the receiver.

The proposed PLC receiver is designed and fabricated in CMOS 0.18 µm technology under the supply voltage of 1.8 V. Measurement results of the three sub-blocks and the entire PLC receiver are presented and compared with simulation results. The data rate for the measurements is set to 10.0 Mbps, and the ASK modulation scheme adopts VDD (= 1.8 V) for logic 0 and 90 mV above VDD for logic 1. The measurements show that the PLC receiver can tolerate the supply voltage drop by 0.423 V or 23.0%. The power dissipation for the receiver is 3.2 mW under 1.8 V supply. The core area of the receiver is 72.2 µm x 74.9 µm.
Master of Science

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Kim, Hyun Sung. "Statistical static timing analysis considering the impact of power supply noise in VLSI circuits." [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-1902.

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Dhillon, Yuvraj Singh. "Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6935.

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Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters is expected to gain in significance. Furthermore, the design complexity continues to increase rapidly due to the tremendous increase in number of components (gates/transistors) on an IC every technology generation. This research describes an efficient and general CAD framework for the optimization of critical circuit characteristics such as power consumption and soft-error tolerance under delay constraints with supply/threshold voltages and/or gate sizes as variables. A general technique called Delay-Assignment-Variation (DAV) based optimization was formulated for the delay-constrained optimization of directed acyclic graphs. Exact mathematical conditions on the supply and threshold voltages of circuit modules were developed that lead to minimum overall dynamic and static power consumption of the circuit under delay constraints. A DAV search based method was used to obtain the optimal supply and threshold voltages that minimized power consumption. To handle the complexity of design of reliable, low-power circuits at the gate level, a hierarchical application of DAV based optimization was explored. The effectiveness of the hierarchical approach in reducing circuit power and unreliability, while being highly efficient is demonstrated. The usage of the technique for improving upon already optimized designs is described. An accurate and efficient model for analyzing the soft-error tolerance of CMOS circuits is also developed.
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Dicken, James. "Power extraction circuits for piezoelectric energy harvesters and time series data in water supply systems." Thesis, Imperial College London, 2013. http://hdl.handle.net/10044/1/17841.

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This thesis investigates two fundamental technological challenges that prevent water utilities from deploying infrastructure monitoring apparatus with high spatial and temporal resolution: providing sufficient power for sensor nodes by increasing the power output from a vibration-driven energy harvester based on piezoelectric transduction, and the processing and storage of large volumes of data resulting from the increased level of pressure and flow rate monitoring. Piezoelectric energy harvesting from flow-induced vibrations within a water main represents a potential source of power to supply a sensor node capable of taking high- frequency measurements. A main factor limiting the amount of power from a piezoelectric device is the damping force that can be achieved. Electronic interface circuits can modify this damping in order to increase the power output to a reasonable level. A unified analytical framework was developed to compare circuits able to do this in terms of their power output. A new circuit is presented that out-performs existing circuits by a factor of 2, which is verified experimentally. The second problem concerns the management of large data sets arising from resolving challenges with the provision of power to sensor devices. The ability to process large data volumes is limited by the throughput of storage devices. For scientists to execute queries in a timely manner, query execution must be performant. The large volume of data that must be gathered to extract information from historic trends mandates a scalable approach. A scalable, durable storage and query execution framework is presented that is able to significantly improve the execution time of user-defined queries. A prototype database was implemented and validated on a cluster of commodity servers using live data gathered from a London pumping station and transmission mains. Benchmark results and reliability tests are included that demonstrate a significant improvement in performance over a traditional database architecture for a range of frequently-used operations, with many queries returning results near-instantaneously.
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Abebe, K. D. "Modelling and implementation of PMW-fed asynchronous machines." Thesis, University of Strathclyde, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.382322.

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Sane, Hemant. "Power supply noise analysis for 3D ICs using through-silicon-vias." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33875.

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3D design is being recognized widely as the next BIG thing in system integration. However, design and analysis tools for 3D are still in infancy stage. Power supply noise analysis is one of the critical aspects of a design. Hence, the area of noise analysis for 3D designs is a key area for future development. The following research presents a new parasitic RLC modeling technique for 3D chips containing TSVs as well as a novel optimization algorithm for power-ground network of a 3D chip with the aim of minimizing noise in the network. The following work also looks into an existing commercial IR drop analysis tool and presents a way to modify it with the aim of handling 3D designs containing TSVs.
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Books on the topic "Power supply circuits"

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Brown, Marty. Practical switching power supply design. San Diego: Academic Press, 1990.

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Simplified design of micropower and battery circuits. Boston: Butterworth-Heinemann, 1996.

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Wu, Keng C. Transistor circuits for spacecraft power system. Norwell, Mass: Kluwer Academic Publishers, 2003.

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Wu, Keng C. Transistor circuits for spacecraft power system. Norwell, Mass: Kluwer Academic Publishers, 2003.

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Gordon, Bloom, ed. Modern DC-to-DC switchmode power converter circuits. New York: Van Nostrand Reinhold Co., 1985.

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Power hybrid circuit design and manufacture. New York: M. Dekker, 1996.

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Sturman, John C. High-voltage, high-power, solid-state remote power controllers for aerospace applications. [Washington, D.C.]: National Aeronautics and Space Administration, Scientific and Technical Information Branch, 1985.

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Sturman, John C. High-voltage, high-power, solid-state remote power controllers for aerospace applications. [Washington, D.C.]: National Aeronautics and Space Administration, Scientific and Technical Information Branch, 1985.

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Sturman, John C. High-voltage, high-power, solid-state remote power controllers for aerospace applications. [Washington, D.C.]: National Aeronautics and Space Administration, Scientific and Technical Information Branch, 1985.

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Mezhiba, Andrey V. Power distribution networks in high speed integrated circuits. Boston, MA: Kluwer Academic Publishers, 2003.

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Book chapters on the topic "Power supply circuits"

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Zeng, Gengsheng Lawrence, and Megan Zeng. "DC Power Supply and Multimeters." In Electric Circuits, 9–16. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-60515-5_2.

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Gumhalter, Hans. "Basic Circuits and Process Control." In Power Supply in Telecommunications, 129–43. Berlin, Heidelberg: Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/978-3-642-78403-3_7.

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Fischer, Jürgen, Ettore Amirante, Agnese Bargagli-Stoffi, Philip Teichmann, Dominik Gruber, and Doris Schmitt-Landsiedel. "Power Supply Net for Adiabatic Circuits." In Lecture Notes in Computer Science, 413–22. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30205-6_43.

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Pal, Ajit. "Supply Voltage Scaling for Low Power." In Low-Power VLSI Circuits and Systems, 175–212. New Delhi: Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-1937-8_7.

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Jonsson, Bengt E. "Design of Power Supply Wires." In Switched-Current Signal Processing and A/D Conversion Circuits, 91–96. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4757-6648-6_6.

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Safari, Leila, Giuseppe Ferri, Shahram Minaei, and Vincenzo Stornelli. "CMIA Based on Op-Amp Power Supply Current Sensing Technique." In Analog Circuits and Signal Processing, 15–28. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-01343-1_2.

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Staveren, A., J. Velzen, C. J. M. Verhoeven, and A. H. M. Roermund. "An Integratable Second-Order Compensated Bandgap Reference for 1V Supply." In Low-Voltage Low-Power Analog Integrated Circuits, 69–81. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2283-6_6.

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Kim, Seokjoong, and Matthew R. Guthaus. "SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture." In VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 181–95. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-45073-0_10.

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Pan, Zhongliang, and Ling Chen. "Using Binary Decision Diagram for Test Generation of Power Supply Noise in Digital Circuits." In Advances in Mechanical and Electronic Engineering, 253–58. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-31528-2_41.

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Ritchie, G. J. "Power supply regulators." In Transistor Circuit Techniques, 177–203. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4899-6890-6_9.

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Conference papers on the topic "Power supply circuits"

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Wenck, Justin, Rajeevan Amirtharajah, Jamie Collier, and Jeff Siebert. "AC Power Supply Circuits for Energy Harvesting." In 2007 IEEE Symposium on VLSI Circuits. IEEE, 2007. http://dx.doi.org/10.1109/vlsic.2007.4342779.

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Zhou, Yong, and Ka Nang Leung. "Power supply circuits for energy harvesting applications." In 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2017. http://dx.doi.org/10.1109/edssc.2017.8126575.

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Charania, Tasreen, Pierce Chuang, Ajoy Opal, and Manoj Sachdev. "Analysis of power supply noise mitigation circuits." In 2011 24th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE). IEEE, 2011. http://dx.doi.org/10.1109/ccece.2011.6030663.

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Jianchun, He, Jia Lixin, and Liu Sheng. "Power Supply Noise Analysis in DSM Circuits." In 2007 International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications. IEEE, 2007. http://dx.doi.org/10.1109/mape.2007.4393544.

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Maloney, T. J., and S. Dabral. "Novel clamp circuits for IC power supply protection." In Proceedings of 17th Annual Electrical Overstress/Electrostatic Discharge Symposium. IEEE, 1995. http://dx.doi.org/10.1109/eosesd.1995.478262.

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Sheikh, Farhana, Andreas Kuehlmann, and Kurt Keutzer. "Minimum-power retiming for dual-supply CMOS circuits." In the 8th ACM/IEEE international workshop. New York, New York, USA: ACM Press, 2002. http://dx.doi.org/10.1145/589411.589422.

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Drumea, Andrei, and Robert Alexandru Dobre. "Analysis of power supply circuits for electroluminescent panels." In Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies 2016, edited by Marian Vladescu, Razvan Tamas, and Ionica Cristea. SPIE, 2016. http://dx.doi.org/10.1117/12.2246102.

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Pathak, Divya, and Ioannis Savidis. "Power supply voltage detection and clamping circuit for 3-D integrated circuits." In 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2014. http://dx.doi.org/10.1109/s3s.2014.7028202.

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9

Hirose, Tetsuya, Tetsuya Asai, and Yoshihito Amemiya. "Power Supply Circuits for Ultralow-Power Subthreshold CMOS Smart Sensor LSIs." In 2006 International Symposium on Intelligent Signal Processing and Communications. IEEE, 2006. http://dx.doi.org/10.1109/ispacs.2006.364719.

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Gaboriault, M. T. "The global market for power supply and power management integrated circuits." In APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285). IEEE, 1999. http://dx.doi.org/10.1109/apec.1999.749487.

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