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Ramadass, Yogesh Kumar. "An energy optimal power supply for digital circuits." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37922.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 96-98).
The energy efficiency of digital circuits continues to be a major factor in determining the size and weight of battery-operated electronics. Integration of more functionality in a single system has made battery longevity a major problem. Operating circuits at their minimum energy operating voltage (MEP) has been proposed as a solution for energy critical applications where performance is not a key constraint. This thesis explores the sensitivity of the MEP to operating conditions and motivates the need for continuous minimum energy tracking based on the energy savings possible. A circuit that can dynamically track the MEP of a digital circuit with varying load conditions and temperature is presented. A low power, voltage scalable DC-DC converter is also embedded within the chip. The proposed minimum energy tracking algorithm uses a novel approach to sense the energy consumed per operation. The energy sensing circuitry does not use high-resolution Analog-to-Digital converters or high gain amplifiers. The energy estimate is used in a slope tracking algorithm to track the minimum energy operating voltage. The minimum energy tracking loop along with a low-voltage DC-DC converter and test circuitry were fabricated in a 65nm CMOS process.
(cont.) The circuits are powered from an external 1.2V supply. The digital test circuitry was capable of operation at voltages as low as 0.25V. The tracking of the minimum energy operating voltage with change in workload and temperature was observed. The DC-DC converter was able to deliver load voltages between 0.25V and 0.7V with an efficiency > 78% at load power levels of the order of 1 0.1W and above.
by Yogesh Kumar Ramadass.
S.M.
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O'Toole, Vincent. "A novel high frequency power supply for use in welding applications." Thesis, University of Liverpool, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.293140.
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Tate, D. "A microprocessor controlled error switching inverter used in the uninterruptible power supply environment." Thesis, University of Bath, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.275883.
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Choi, Jinseong. "Modeling of power supply noise in large chips using the finite difference time domain method." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/14977.
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Salem, Jebreel Mohamed Muftah. "A Reliable CMOS Receiver for Power Line Communications in Integrated Circuits." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/30942.
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Power line communications (PLC) in integrated circuits (ICs) was proposed by Dr. Dong S. Haâ group in 2005. Their goal was to utilize the power distribution network for data communications as well as delivery of power, so that the routing overhead can be avoided and the number of pins in the chip can be reduced. Dr. Haâ s group demonstrated through measurements the existence of pass-bands in the power distribution networks and the feasibility of power line communications in ICs. Several PLC receivers were developed to recover data superimposed on the power lines of an IC. This thesis research investigated a new PLC receiver to improve shortcomings of previous PLC receivers, specifically to improve the reliability while reducing power dissipation. The proposed PLC system adopts an amplitude shift keying (ASK) modulation to transmit and detect data through power distribution networks. The proposed PLC receiver consists of three main sub-blocks. The first sub-block is a level shifter, which lowers the offset voltage of the supply voltage to approximately 0.5VDD. The second sub-block is a signal extractor, which detects a data signal superimposed on the power line. The signal extractor is a differential amplifier, in which one input is connected through an RC low-pass filter. The DC voltage of the data signal varies in accordance with the supply voltage fluctuations and droop. The low-pass filter intends to pass only the DC term of the data signal. Since the DC voltage is common for both inputs of the differential amplifier, it is removed from the data signal through the common mode rejection of the differential amplifier. Therefore, the signal extractor can mitigate supply voltage fluctuations and droops. The last sub-block is the logic restorer, which converts the differential signal to a logic value based on a Schmitt trigger. The hysteresis of the Schmitt trigger improves the noise immunity of the receiver.
The proposed PLC receiver is designed and fabricated in CMOS 0.18 µm technology under the supply voltage of 1.8 V. Measurement results of the three sub-blocks and the entire PLC receiver are presented and compared with simulation results. The data rate for the measurements is set to 10.0 Mbps, and the ASK modulation scheme adopts VDD (= 1.8 V) for logic 0 and 90 mV above VDD for logic 1. The measurements show that the PLC receiver can tolerate the supply voltage drop by 0.423 V or 23.0%. The power dissipation for the receiver is 3.2 mW under 1.8 V supply. The core area of the receiver is 72.2 µm x 74.9 µm.
Master of Science
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Kim, Hyun Sung. "Statistical static timing analysis considering the impact of power supply noise in VLSI circuits." [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-1902.
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Dhillon, Yuvraj Singh. "Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6935.
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Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters is expected to gain in significance. Furthermore, the design complexity continues to increase rapidly due to the tremendous increase in number of components (gates/transistors) on an IC every technology generation. This research describes an efficient and general CAD framework for the optimization of critical circuit characteristics such as power consumption and soft-error tolerance under delay constraints with supply/threshold voltages and/or gate sizes as variables.
A general technique called Delay-Assignment-Variation (DAV) based optimization was formulated for the delay-constrained optimization of directed acyclic graphs. Exact mathematical conditions on the supply and threshold voltages of circuit modules were developed that lead to minimum overall dynamic and static power consumption of the circuit under delay constraints. A DAV search based method was used to obtain the optimal supply and threshold voltages that minimized power consumption.
To handle the complexity of design of reliable, low-power circuits at the gate level, a hierarchical application of DAV based optimization was explored. The effectiveness of the hierarchical approach in reducing circuit power and unreliability, while being highly efficient is demonstrated. The usage of the technique for improving upon already optimized designs is described. An accurate and efficient model for analyzing the soft-error tolerance of CMOS circuits is also developed.
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Dicken, James. "Power extraction circuits for piezoelectric energy harvesters and time series data in water supply systems." Thesis, Imperial College London, 2013. http://hdl.handle.net/10044/1/17841.
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This thesis investigates two fundamental technological challenges that prevent water utilities from deploying infrastructure monitoring apparatus with high spatial and temporal resolution: providing sufficient power for sensor nodes by increasing the power output from a vibration-driven energy harvester based on piezoelectric transduction, and the processing and storage of large volumes of data resulting from the increased level of pressure and flow rate monitoring. Piezoelectric energy harvesting from flow-induced vibrations within a water main represents a potential source of power to supply a sensor node capable of taking high- frequency measurements. A main factor limiting the amount of power from a piezoelectric device is the damping force that can be achieved. Electronic interface circuits can modify this damping in order to increase the power output to a reasonable level. A unified analytical framework was developed to compare circuits able to do this in terms of their power output. A new circuit is presented that out-performs existing circuits by a factor of 2, which is verified experimentally. The second problem concerns the management of large data sets arising from resolving challenges with the provision of power to sensor devices. The ability to process large data volumes is limited by the throughput of storage devices. For scientists to execute queries in a timely manner, query execution must be performant. The large volume of data that must be gathered to extract information from historic trends mandates a scalable approach. A scalable, durable storage and query execution framework is presented that is able to significantly improve the execution time of user-defined queries. A prototype database was implemented and validated on a cluster of commodity servers using live data gathered from a London pumping station and transmission mains. Benchmark results and reliability tests are included that demonstrate a significant improvement in performance over a traditional database architecture for a range of frequently-used operations, with many queries returning results near-instantaneously.
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Abebe, K. D. "Modelling and implementation of PMW-fed asynchronous machines." Thesis, University of Strathclyde, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.382322.
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Sane, Hemant. "Power supply noise analysis for 3D ICs using through-silicon-vias." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33875.
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3D design is being recognized widely as the next BIG thing in system integration. However, design and analysis tools for 3D are still in infancy stage. Power supply noise analysis is one of the critical aspects of a design. Hence, the area of noise analysis for 3D designs is a key area for future development. The following research presents a new parasitic RLC modeling technique for 3D chips containing TSVs as well as a novel optimization algorithm for power-ground network of a 3D chip with the aim of minimizing noise in the network. The following work also looks into an existing commercial IR drop analysis tool and presents a way to modify it with the aim of handling 3D designs containing TSVs.
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A'Ain, Abu Khari Bin. "Power supply voltage control testing technique as a novel electrical test strategy for analogue integrated circuits." Thesis, Lancaster University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337370.
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Ng, Chik-wai, and 吳植偉. "Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45896926.
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Kaya, Ibrahim. "A Switch Mode Power Supply For Producing Half Wave Sine Output." Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/12609781/index.pdf.
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In this thesisanalysis, design and implementation of a DC-DC converter with active clamp forward topology is presented. The main objective of this thesis is generating a rectified sinusoidal voltage at the output of the converter. This is accomplished by changing the reference signal of the converter. The converter output is applied to an inverter circuit in order to obtain sinusoidal waveform. The zero crossing points of the converter is detected and the inverter drive signals are generated in order to obtain sinusoidal waveform from the output of the converter. Next, the operation of the DC-DC converter and sinusoidal output inverter coupled performance is investigated with resistive and inductive loads to find out how the proposed topology performs. The design is implemented with an experimental set-up and steady state and dynamic performance of the designed power supply is tested. Finally an evaluation of how better performance can be obtained from this kind of arrangement to obtain a sinusoidal output inverted is thoroughly discussed
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Healy, Michael Benjamin. "Physical design for performance and thermal and power-supply reliability in modern 2D and 3D microarchitectures." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37093.
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The main objective of this research is to examine the performance, power noise, and thermal trade-offs in modern traditional (2D) and three-dimensionally-integrated (3D) architectures and to present design automation tools and physical design methodologies that enable higher reliability while maintaining microarchitectural performance for these systems. Five main research topics that support this goal are included. The first topic focuses on thermal reliability. The second, third, and fourth, topics examine power-supply noise. The final topic presents a set of physical design and analysis methodologies used to produce a 3D design that was sent for fabrication in March of 2010.
The first section of this dissertation details a microarchitectural floorplanning algorithm that enables the user to choose and adjust the trade-off between microarchitectural performance and general operating temperature in both 2D and 3D systems, which is a major determinant of overall reliability and chip lifetime. Simulation results demonstrate that the algorithm performs as expected and successfully provides the user with the desired trade-off. The first section also presents a thermal-aware microarchitectural floorplanning algorithm designed to help reduce the operating temperature of the cores in the unique environment present within multi-core processors. Heat-coupling between neighboring cores is considered during the optimization process to provide floorplans that result in lower maximum temperature.
The second section explores power-supply noise in processors caused by fine-grained clock-gating and describes a floorplanning algorithm created to work with an active noise-canceling clock-gating controller. Simulation results show that combining these two techniques results in lower power-supply noise with minimal processor performance impact. The third section turns to future 3D systems with a large number of stacked active layers (many-tier systems) and examines power-supply delivery challenges in these systems. Parasitic resistance, capacitance, and inductance are calculated for the 3D vias, and the results of scaling various parameters in the power-supply-network design are presented. Several techniques for reducing power-supply-network noise in these many-tier systems are explored. The fourth section describes a layout-level analysis of a novel power distribution through-silicon-via topology and it's effect on IR-drop and dynamic noise. Simulations show that both types of power-supply noise can be reduced by more than 20\% in systems with non-uniform per-tier power dissipation when using the proposed topology.
The final section explains the physical design and analysis techniques used to produce the layouts for 3D-MAPS, a 64-core 3D-stacked memory-on-processor system targeted at demonstration of large memory bandwidth using 3D connections. The 3D-aware physical design flow utilizing non-3D-aware commercial tools is detailed, along with the techniques and add-ons that were developed to enable this process.
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Hietakangas, S. (Simo). "Design methods and considerations of supply modulated switched RF power amplifiers." Doctoral thesis, Oulun yliopisto, 2012. http://urn.fi/urn:isbn:9789514298363.
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Abstract This thesis studies the design methods and properties of supply-modulated switch-mode radio frequency power amplifiers. Besides simulation based studies and theory review, two amplifiers were designed: a discrete MESFET class E amplifier (0.5 W at 1 GHz), and an integrated pHEMT class E-1 amplifier (2.0 W at 1.6 GHz) with an on-chip resonator. The existing design methods of the resonant output network of switching amplifiers were reviewed and some extensions on the handling of nonlinear capacitances were proposed. The effects of varying supply voltage were studied and suggestions were given to minimize Vdd / AM and Vdd / PM distortion in supply modulated amplifiers. The implementation of the bias feed was also discussed resulting in proposing a combination of a short transmission line and a small inductor, which provides both fast supply modulation and little effect on harmonic impedances. The main contributions are related to the study of the input impedance of a class E power amplifier, where the effects of supply dependent input impedance and timing skew generated by injected harmonic distortion were analyzed. The stabilization of the amplifier was also discussed. Based on the findings, a push-pull class E amplifier with extra cross-coupled feedback capacitors and second harmonic traps at the gates appears to be a very good starting point for a further studyTiivistelmä Tämä väitöstyö käsittelee radiotaajuuksilla toimivien käyttöjännitemoduloitujen kytkintehovahvistimien ominaisuuksia ja suunnittelumenetelmiä. Suunnittelumenetelmiin liittyvän katsauksen ja simulaatioihin perustuvan tutkimusten lisäksi kaksi vahvistinta toteutettiin väitöstutkimuksen aikana: diskreettikomponentein toteutettu E-luokan vahvistin (MESFET, 0.5 W ja 1 GHz) ja integroituna piirinä toteutettu käänteinen E-luokan vahvistin (pHEMT, 2.0 W ja 1.6 GHz), jonka lähdön resonaattoripiiri sisällytettiin integroituun piiriin. Kytkinvahvistimien suunnittelumenetelmiä verrattiin ja kehitettiin edelleen siten, että suunnitteluvaiheessa voidaan ottaa huomioon esim. transistoripiirin takaisinkytkennässä olevan kapasitanssin epälineaarisuus. Työssä tutkittiin myös käyttöjännitemodulaation vaikutusta kytkinvahvistimien toimintaan, ja tutkimuksen tuloksena annettiin muutamia ehdotuksia käyttöjänniteriippuvan amplitudi- (Vdd / AM) ja vaihemodulaation (Vdd / PM) vähentämiseksi. Lähdön biasointipiirin toteutukseen suositeltiin pienen kelan ja siirtolinjan yhdistelmää. Yhdistelmän avulla pyritään maksimoimaan modulaationopeus ja minimoimaan vaikutukset harmonisiin impedansseihin. Pääkohtina väitöksessä ovat E-luokan kytkinvahvistimesta saadut tutkimus- ja mittaushavainnot käyttöjännitteen funktiona muuttuvasta transistorin tuloimpedanssista sekä suurikokoisen transistorin tuloissa tapahtuvan, säröytymisen aiheuttaman tulosignaalien ajoitusvirheen analyysi. Näiden lisäksi vahvistimen stabiilisuuteen kiinnitettiin huomiota. Saatujen havaintojen perusteella voimme todeta, että push-pull -tyyppinen E-luokan vahvistin olisi mielenkiintoinen valinta jatkotutkimuksille
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Ohn, Sungjae. "Circuits and Modulation Schemes to Achieve High Power-Density in SiC Grid-connected Converters." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/89550.
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The emergence of silicon-carbide (SiC) devices has been a 'game changer' in the field of power electronics. With desirable material properties such as low-loss characteristics, high blocking voltage, and high junction temperature operation, they are expected to drastically increase the power density of power electronics systems. Recent state-of-the-art designs show the power density over 17 ; however, certain factors limit the power density to increase beyond this limit. In this dissertation, three key factors are selected to increase the power density of SiC-based grid-connected three-phase converters. Throughout this dissertation, the techniques and strategies to increase the power density of SiC three-phase converters were investigated.
Firstly, a magnetic integration method was introduced for the coupled inductors in the interleaved three-phase converters. Due to limited current-capacity compared to the silicon insulated-gate bipolar transistors (Si-IGBTs), discrete SiC devices or SiC modules, operate in parallel to handle a large current. When three-phase inverters are paralleled, interleaving can be used, and coupled inductors are employed to limit the circulating current. In Chapter 2, the conventional integration method was extended to integrate three coupled inductors into two; one for differential-mode circulating current and the other for common-mode circulating current. By comparing with prior research work, a 20% reduction in size and weight is demonstrated.
From Chapter 3 to Chapter 5, a full-SiC uninterruptible power supply (UPS) was investigated. With the high switching frequency and fast switching dynamics of SiC devices, strategies on electromagnetic inference become more important, compared to Si-IGBT based inverters. Chapter 3 focuses on a common-mode equivalent circuit model for a topology and pulse width modulation (PWM) scheme selection, to set a noise mitigation strategy in the design phase. A three terminal common-mode electromagnetic interference (EMI) model is proposed, which predicts the impact of the dc-dc stage and a large battery-rack on the output CM noise. Based on the model, severe deterioration of noise by the dc-dc stage and battery-rack can be predicted. Special attention was paid on the selection of the dc-dc stage's topology and the PWM scheme to minimize the impact. With the mitigation strategy, a maximum 16 dB reduction on CM EMI can be achieved for a wide frequency range.
In Chapter 4, an active PWM scheme for a full-SiC three-level back-to-back converter was proposed. The PWM scheme targets the size reduction of two key components: dc-link capacitors and a common-mode EMI filter. The increase in switching frequency calls for a large common-mode EMI filter, and dc-link capacitors in the three-level topology may take a considerable portion in the total volume. To reduce the common-mode noise emission, different combinations of the voltage vectors are investigated to generate center-aligned single pulse common-mode voltage. By such an alignment of common-mode voltage with different vector combinations, noise cancellation between the rectifier and the inverter can be maximally utilized, while the balancing of neutral point voltage can be achieved by the transition between the combinations. Also, to reduce the size of the dc-link capacitor for the three-level back-to-back converter, a compensation algorithm for neutral point voltage unbalance was developed for both differential-mode voltage and the common-mode voltage of the ac-ac stage. The experimental results show a 4 dB reduction on CM EMI, which leads to a 30% reduction on the required CM inductance value. When a 10% variation of neutral point voltage can be handled, the dc-link capacitance can be reduced by 56%.
In Chapter 5, a 20 kW full-SiC UPS prototype was built to demonstrate a possible size-reduction with the proposed PWM scheme, as well as a selection of topologies and PWM schemes based on the model. The power density and efficiency are compared with the state-of-the-art Si-IGBT based UPSs.
Chapter 6 seeks to improve power density by a change in a modulation method. Triangular conduction mode (TCM) operation of the three-level full-SiC inverter was investigated. The switching loss of SiC devices is reported to be concentrated on the turn-on instant. With zero-voltage turn-on of all switches, the switching frequency of a three-level three-phase SiC inverter can be drastically increased, compared to the hard-switching operation. This contributes to the size-reduction of the filter inductors and EMI filters. Based on the design to achieve a 99% peak efficiency, a comparison was made with a full-SiC three-level inverter, operating in continuous conduction mode (CCM), to verify the benefit of the soft switching scheme on the power density. A design procedure for an LCL filter of paralleled TCM inverters was developed. With 3.5 times high switching frequency, the total weight of the filter stage of the TCM inverter can be reduced by 15%, compared to that of the CCM inverter.
Throughout this dissertation, techniques for size reduction of key components are introduced, including coupled inductors in parallel inverters, an EMI filter, dc-link capacitors, and the main boost inductor. From Chapter 2 to 5, the physical size or required value of these key components could be reduced by 20% to 56% by different schemes such as magnetic integration, EMI mitigation strategy through modeling, and an active PWM scheme. An optimization result for a full-SiC UPS showed a 40% decrease in the total volume, compared to the state-of-the-art Si-IGBT solution. Soft-switching modulation for SiC-based three-phase inverters can bring a significant increase in the switching frequency and has the potential to enhance power-density notably. A three-level three-phase full-SiC 40 kW PV inverter with TCM operation contributed to a 15% reduction on the filter weight.Doctor of Philosophy
The power density of a power electronics system is regarded as an indicator of technological advances. The higher the power density of the power supply, the more power it can generate with the given volume and weight. The size requirement on power electronics has been driven towards tighter limits, as the dependency on electric energy increases with the electrification of transportation and the emergence of grid-connected renewable energy sources. However, the efficiency of a power electronics system is an essential factor and is regarded as a trade-off with the power density. The size of power electronics systems is largely impacted by its magnetic components for filtering, as well as its cooling system, such as a heatsink. Once the switching frequency of power semiconductors is increased to lower the burden on filtering, more loss is generated from filters and semiconductors, thus enlarging the size of the cooling system. Therefore, considering the efficiency has to be maintained at a reasonable value, the power density of Si-based converters appears to be saturated. With the emergence of wide-bandgap devices such as silicon carbide (SiC) or gallium nitride (GaN), the switching frequency of power devices can be significantly increased. This is a result of superior material properties, compared to Si-based power semiconductors. For grid-connected applications, SiC devices are adopted, due to the limitations of voltage ratings in GaN devices. Before commercial SiC devices were available, the power density of SiC- based three-phase inverters was expected to go over 20 𝑘𝑊 𝑑𝑚3 ⁄ . However, the state-of-the art designs shows the power density around 3 ~ 4 𝑘𝑊 𝑑𝑚3 ⁄ , and at most 17 𝑘𝑊 𝑑𝑚3 ⁄ . The SiC devices could increase the power density, but they have not reached the level expected. The adoption of SiC devices with faster switching was not a panacea for power density improvement. This dissertation starts with an analysis of the factors that prevent power density improvement of SiC-based, grid-connected, three-phase inverters. Three factors were identified: a limited increase in the switching frequency, large high-frequency noise generation to be filtered, and smaller but still significant magnetic components. Using a generic design procedure for three-phase inverters, each chapter seeks to frame a strategy and develop techniques to enhance the power density. For smaller magnetic components, a magnetic integration scheme is proposed for paralleled ac-dc converters. To reduce the size of the noise filter, an accurate modeling approach was taken to predict the noise phenomena during the design phase. Also, a modulation scheme to minimize the noise generation of the ac-ac stage is proposed. The validity of the proposed technique was verified by a full-SiC three-phase uninterruptible power supply with optimized hardware design. Lastly, the benefit of soft-switching modulation, which leads to a significant increase in switching frequency, was analyzed. The hardware optimization procedure was developed and compared to hard-switched three-phase inverters.
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Loikkanen, M. (Mikko). "Design and compensation of high performance class AB amplifiers." Doctoral thesis, University of Oulu, 2010. http://urn.fi/urn:isbn:9789514261770.
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Class A and class AB operational amplifiers are an essential part of a mixed- signal chip, where they are used as active filter sub-blocks, compensators, reference current generators and voltage buffers, to name just a few of many applications. For analog circuits such as operational amplifiers a mixed-signal chip is a very unfriendly operating environment, where the power supply is often corrupted by high current switching circuits. In addition, power supply voltages for analog blocks are shrinking, because of the deployment of new battery technologies and fine line length integrated circuit processes, which can reduce the amplifier dynamic range a problem requiring supply insensitive low voltage compatible amplifier topologies and other analog blocks.
The aims of this thesis were to further develop the low voltage compatible class AB amplifier topologies published earlier by other authors, to improve their bandwidth efficiency by means of re-examining two- and three-stage amplifier compensation techniques and to find solutions for enhancing the high frequency power supply noise rejection performance of class A and class AB amplifiers without degrading their signal path stability.
The class AB amplifier cores presented here improve the amplifier’s power supply noise insensitivity at high frequencies and increase bandwidth efficiency when compared to the commonly used two-stage Miller compensated amplifier, enabling the construction of better buffers and more power-efficient and reliable low voltage mixed signal chips.
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Groves, James O. "Small signal analysis of nonlinear systems with periodic operating trajectories." Diss., This resource online, 1995. http://scholar.lib.vt.edu/theses/available/etd-06062008-162614/.
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Grobler, Frederik Antonie. "The development of harmonic content and quality of electricity supply measuring system incorporating scada processing." Thesis, Bloemfontein : Central University of Technology, Free State, 2005. http://hdl.handle.net/11462/61.
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Thesis (D.Tech (Engineering Electrical)) - Central University of Technology, Free State, 2005When Thomas Edison invented his carbon filament lamp in 1879, gas shares fell overnight. A committee of inquiry was set up to examine the future possibilities of the new method of lighting, and had reached the conclusion that electric light in the home was fanciful and absurd. Today electric light burns in practically every house in the civilised world, with many great advances in the production and use of electricity and electric power supplied by various utilities. The objective of the electric utility to deliver pure sinusoidal voltage at fairly constant magnitude throughout their system is complicated by the fact that there are currently loads on the system that produce harmonic voltages, which result in distorted voltages and currents that can adversely impact on the system performance in different ways. Because the numbers of harmonic producing loads have increased over the years, it has become necessary to address their influence, when making any additions or changes to an installation. Quality of supply measurements have long been used to characterise non-linearity on the power system, and have traditionally been measured with expensive portable analysers. A potentially faster, more integrated, and more flexible solution to measure the harmonics with a Supervisory System is accomplished by this research. Any script which aspired to cover in full detail the whole field of a subject so enormous as techniques to measure the quality of electricity supply on a SCADA system, would hardly be practical in less than a few volumes. The pretensions of this research are both modest and of a more immediate value to the reader.
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Loayza, Ramirez Jorge Miguel. "Study and characterization of electrical overstress aggressors on integrated circuits and robustness optimization of electrostatic discharge protection devices." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEI044.
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Cette thèse de doctorat s’inscrit dans la thématique de la fiabilité des circuits intégrés dans l’industrie de la microélectronique. Un circuit intégré peut être exposé à des agresseurs électriques potentiellement dangereux pendant toute sa durée de vie. Idéalement, les circuits devraient pouvoir encaisser ces excès d’énergie sans perdre leur fonctionnalité. En réalité, des défaillances peuvent être observées lors de tests de qualification ou en application finale. Il est donc dans l’intérêt des fabricants de réduire ces défaillances. Actuellement, il existe des circuits de protection sur puce conçus pour dévier l’énergie de ces agresseurs à l’écart des composants fragiles. Le terme anglophone Electrical Overstress (EOS) englobe tous les agresseurs électriques qui dépassent une limite au-delà de laquelle les composants peuvent être détruits. La définition de ce terme est traitée en détail dans la thèse. L’objectif de cette thèse est de comprendre le statut du sujet des EOS dans l’industrie. On propose ensuite une nouvelle méthodologie de caractérisation de circuits pour quantifier leur robustesse face à des formes d’onde représentatives présélectionnées. On propose également des solutions de circuits de protection sur puce que ce soit au niveau de nouveaux composants actifs ou au niveau de la conception des circuits électroniques de protection. Par exemple on propose un nouveau composant basé sur le thyristor qui a la capacité de s’éteindre même si la tension d’alimentation est présente sur l’anode. Une autre proposition est de désactiver les circuits de protection face aux décharges électrostatiques lorsque les puces sont dans un environnement où l’on est sur ou ces agresseurs ne présentent plus de danger. Finalement, des perspectives du travail de thèse sont citéesThis Ph.D. thesis concerns reliability issues in the microelectronics industry for the most advanced technology nodes. In particular, the Electrical OverStress (EOS) issue is studied. Reducing EOS failures in Integrated Circuits (ICs) is becoming more and more important. However, the EOS topic is very complex and involves many different causes, viewpoints, definitions and approaches. In this context, a complete analysis of the current status of the EOS issue is carried out. Then, the Ph.D. objectives can be defined in a clear way. In particular, robustness increase of on-chip protection structures and IC characterization against EOS-like aggressors are two of the main goals. In order to understand and quantify the behavior of ICs against these aggressors, a dedicated EOS test bench is put in place along with the definition of a characterization methodology. A full characterization and comparison is performed on two different Electro- Static Discharge (ESD) power supply clamps. After identifying the potential weaknesses of the promising Silicon-Controlled Rectifier (SCR) device, a new SCR-based device with a turn-off capability is proposed and studied thanks to 3-D Technology Computer-Aided Design (TCAD)simulation. Triggering and turn-off behaviors are studied, as well as its optimization. Finally, three different approaches are proposed for improving the robustness of the IC onchip protection circuits. They are characterized thanks to the EOS test bench which allows identifying their assets as well as their points of improvement
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Lalgudi, Subramanian N. "Transient simulation of power-supply noise in irregular on-chip power distribution networks using latency insertion method, and causal transient simulation of interconnects characterized by band-limited data and terminated by arbitrary terminations." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22561.
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Zussa, Loic. "Étude des techniques d'injection de fautes par violation de contraintes temporelles permettant la cryptanalyse physique de circuits sécurisés." Thesis, Saint-Etienne, EMSE, 2014. http://www.theses.fr/2014EMSE0757/document.
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Si un algorithme cryptographique peut être mathématiquement sûr, son implémentation matérielle quant à elle est souvent la cible de nombreuses attaques. Cette thèse porte sur l'étude des mécanismes d'injection de fautes pouvant permettre une cryptanalyse physique des circuits sécurisés et sur la conception de contre-mesures matérielles pour empêcher ces attaques.Dans un premier temps une mise en pratique d'injection de fautes sur une implémentation matérielle de l'AES a été menée à l'aide d'attaques physiques : variations statiques et dynamiques de la tension, de la fréquence, de la température et de l'environnement électromagnétique. La comparaison des fautes injectées nous a permis de conclure que ces différentes attaques partagent un mécanisme d'injection identique : la violation de contraintes temporelles.La conception et l'implémentation d'un voltmètre intégré nous a permis d'observer les perturbations internes dues aux attaques par variations transitoires de la tension. Ces observations ont permis une meilleure compréhension du mécanisme d'injection de fautes associé et une amélioration de la précision temporelle de ces injections.Ensuite, un détecteur a été implémenté et son efficacité face à des attaques électromagnétiques a été étudiée. Du fait de la localité spatiale de ces attaques, la zone effectivement protégée par le détecteur est limitée. Une implémentation de plusieurs détecteurs a été suggérée.Enfin, un nouveau chemin d'attaque exploitant la sensibilité du détecteur a été proposé et validé expérimentalementEven if a cryptographic algortihm could be mathematically secure, its physical implementation could be targeted by several attacks. This thesis focus on time-based fault injection mechanisms used for physical cryptanalysis of secure circuits.First, practical fault injections have been performed on a hardware AES implementation using non-invasive attacks : static and dynamic variations of the power supply voltage, frequency, temperature and electromagnetic environement. Then a comparison of these obtained faults led us to conclude that these different injection means share a common injection mecanism : timing constraints violations.An on-chip voltmeter has been designed and implemented to observe internal disturbences due to voltage glitchs. These observations led to a better understanding of the fault injection mecanism and to a better temporal accuracy.Then, a contermeasure has been designed and its effectiveness against electromagnetic attacks has been studied. Because of the electromagnetic pulses local effects, the aera effectively protected by the countermeasure is limited. The implementation of several countermeasures has been considered in order to extend the protected aera.Finally, a new attack path using the countermeasure detection threshold variations has been proposed and experimentaly validated. This attack exploit the electrical coupling between the AES and the coutnermeasure. Because of this coupling the countermeasure sensitivity variations are related to data handled by the AES
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Jeanniot, Nicolas. "Conception et optimisation d'une alimentation-horloge et d'un réseau de distribution pour la logique adiabatique." Thesis, Montpellier, 2018. http://www.theses.fr/2018MONTS068/document.
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La densité de puissance est devenue la principale préoccupation lorsqu'un circuit numérique est conçu. Comme pour tous les systèmes embarqués, chaque nouvelle génération de système numérique a plus d'applications que la précédente et exige en fin de compte une plus grande densité de puissance. C'est pourquoi de nombreux chercheurs et concepteurs industriels se sont penchés sur de nouvelles méthodes de réduction de la consommation énergétique des circuits numériques. La logique adiabatique est un style de conception prometteur qui peut réduire la dissipation d'énergie dynamique. La logique adiabatique est différente de la logique conventionnelle en deux principaux points : 1) l’alimentation d’une porte logique adiabatique est un signal à 4 phases, et 2) l’énergie stockée dans la porte est récupérée. Afin de respecter ces principes, la logique adiabatique nécessite une alimentation spéciale. Étant donné que l’objectif d’une telle alimentation est d’agir comme une horloge, elle est appelée alimentation-horloge. L'objectif de cette thèse est de concevoir et d'optimiser une alimentation-horloge ainsi que son réseau de distribution. Cette thèse a été financée par l'Agence Nationale pour la Recherche, ANR, avec le projet ADIANEMS2 (numéro de subvention : ANR-15-CE24-0013)Power density has become the primary concern when a digital core is designed. As in any embedded systems, each new digital core generation has more applications than the previous one and ultimately demands more power density. This is why many researchers and industrial designers have been looking into novel methods for reducing power consumption of digital circuit. Adiabatic logic is a promising design style, which can reduce the dynamic energy dissipation. Adiabatic logic is different than conventional logic in two main points: 1) adiabatic gate are charged with a 4-phase power signal, and 2) the energy, which is stored in the gate, is recovered. In order to fulfill these principles, the adiabatic logic needs a special power supply. As the purpose of such supply is to act as a clock also, it is referred as power-clock supply. The aim of this thesis is to design and optimize a power-clock supply and its delivery network. This thesis has been funded by the French National Research Agency, ANR, with the project ADIANEMS2 (Grant number: ANR-15-CE24-0013)
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Arntzen, Chris. "THE BICYCLE-POWERED SMARTPHONE CHARGER." DigitalCommons@CalPoly, 2013. https://digitalcommons.calpoly.edu/theses/1008.
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This thesis entails the design and fabrication of a smartphone charger that is powered by a bicycle dynamo hub. In addition to the design and validation of the charger prototype, this thesis involves the testing and characterization of the dynamo hub power source, the design and construction of specialized test equipment, and the design and prototyping of a handlebar-mounted case for the smartphone and charging electronics. With the intention of making the device a commercial product, price, aesthetics, and marketability are of importance to the design. An appropriate description of the charger circuit is a microcontroller-based energy management system, tailored to meet strict power demands of current smartphones. The system incorporates a switched-mode power supply, lithium polymer battery, microcontroller, and specialized protection circuitry. Prototype testing confirms that the circuit meets the charging requirements of the smartphone at bicycle speeds ranging from 7 miles per hour to as high as 55 miles per hour.
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Saint-Laurent, Martin. "Modeling and Analysis of High-Frequency Microprocessor Clocking Networks." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7271.
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Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems.
The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.
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Halaš, Rostislav. "Odstraňovač zubního kamene." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219252.
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Tato práce se zabývá návrhem ultrazvukového odstraňovače zubního kamene pracujícím na frekvenci 27 kHz s maximální intenzitou ultrazvuku 5W/cm2. Popisuje mechanismus vzniku zubního kamene, důsledky na zdraví a metody jeho odstraňování. Zaměřuje se na principy odstraňování s využitím ultrazvukového vlnění. Dále je sestaveno funkční a blokové schéma. Na základě těchto znalostí je proveden návrh a výpočet jednotlivých částí aplikátoru. Výkonové a napěťové poměry jsou vypočítány od aplikačního hrotu směrem ke generátoru. V neposlední řadě je popsán návrh obvodů buzení měniče i kontrolních obvodů. Schémata jsou doplněna výkresy desek plošných spojů a soupiskou součástek.
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Siddique, Nafiul Alam. "Spare Block Cache Architecture to Enable Low-Voltage Operation." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/216.
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Power consumption is a major concern for modern processors. Voltage scaling is one of the most effective mechanisms to reduce power consumption. However, voltage scaling is limited by large memory structures, such as caches, where many cells can fail at low voltage operation. As a result, voltage scaling is limited by a minimum voltage (Vccmin), below which the processor may not operate reliably. Researchers have proposed architectural mechanisms, error detection and correction techniques, and circuit solutions to allow the cache to operate reliably at low voltages. Architectural solutions reduce cache capacity at low voltages at the expense of logic complexity. Circuit solutions change the SRAM cell organization and have the disadvantage of reducing the cache capacity (for the same area) even when the system runs at a high voltage. Error detection and correction mechanisms use Error Correction Codes (ECC) codes to keep the cache operation reliable at low voltage, but have the disadvantage of increasing cache access time. In this thesis, we propose a novel architectural technique that uses spare cache blocks to back up a set-associative cache at low voltage. In our mechanism, we perform memory tests at low voltage to detect errors in all cache lines and tag them as faulty or fault-free. We have designed shifter and adder circuits for our architecture, and evaluated our design using the SimpleScalar simulator. We constructed a fault model for our design to find the cache set failure probability at low voltage. Our evaluation shows that, at 485mV, our designed cache operates with an equivalent bit failure probability to a conventional cache operating at 782mV. We have compared instructions per cycle (IPC), miss rates, and cache accesses of our design with a conventional cache operating at nominal voltage. We have also compared our cache performance with a cache using the previously proposed Bit-Fix mechanism. Our result show that our designed spare cache mechanism is 15% more area efficient compared to Bit-Fix. Our proposed approach provides a significant improvement in power and EPI (energy per instruction) over a conventional cache and Bit-Fix, at the expense of having lower performance at high voltage.
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Madrigal, Ruben E. (Ruben Esteban). "Custom power supply interface for teaching circuit design." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91842.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.Cataloged from PDF version of thesis.
Includes bibliographical references (page 53).
This thesis discusses the design and implementation of a custom power supply interface for the Pioneer mobile robot used in MIT's 6.01 course, "Introduction to Electrical Engineering and Computer Science." The interface is a printed circuit board that provides bipolar voltage rails of +7VDC and -7VDC, expanding on its predecessor, which only provides a unipolar voltage rail of +1OVDC. The board is mounted internally to the robot and can power the student breadboard circuits via the bipolar voltage rails. This redesigned power supply interface will help the course staff teach students about circuit design in a much simpler context and allow students to focus more on engineering different circuits rather than spending time on tangential problems.
by Ruben E. Madrigal.
M. Eng.
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Kammerer, Marion Kornelia. "LTCC modules for power supply and IF circuitry in RF amplifiers /." Aachen : Shaker, 2007. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=016470518&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.
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Poure, Philippe. "Contribution à l'étude du filtrage dynamique d'un réseau électrique à l'aide d'une machine synchrone commandée par les grandeurs rotoriques." Vandoeuvre-les-Nancy, INPL, 1995. http://www.theses.fr/1995INPL004N.
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Le développement de l'électronique de puissance est à l’origine de la pollution harmonique croissante des réseaux électriques. Les méthodes classiques de filtrage actif, série et parallèle, sont abondamment étudiées dans la littérature. Dans cette thèse, nous nous intéressons à une autre solution mettant en œuvre une machine synchrone dans le but de bénéficier du gain obtenu lors de la commande de la machine par les grandeurs rotoriques. Une étude analytique du filtrage d'harmoniques à l'aide d'une telle machine est d'abord présentée. Deux cas sont envisagés: soit la machine constitue la source du réseau, soit il s'agit d'une machine auxiliaire destinée au filtrage. C’est ce deuxième mode d'utilisation qui est ensuite développé dans le cas d'une machine destinée à filtrer un harmonique particulier. On montre qu'un filtre LC bouchon pour le régime fondamental est nécessaire. Cette solution conduit à un gain important. La simulation du système complet, constitué du réseau, du filtre bouchon, de la charge polluante et de la machine est envisagée. En boucle ouverte et en boucle fermée, les résultats de l'étude analytique sont confirmés. La robustesse du système vis à vis des valeurs des paramètres de la machine est également étudiée
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Zhou, Chen. "Design and analysis of an active power factor correction circuit." Thesis, Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/53729.
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The design of an active-unity power factor correction circuit with variable-hysteresis
control for off-line dc-to-dc switching power supplies is described. Design
equations relating the boost inductor current ripple to the circuit components selection
and circuit performance arc discussed. A computer-aided design program (CADO) is
developed to give the optimal circuit components selection. A 500 watt, 300 volt experimental
circuit is built to verify the simulation and analysis results.
The control-to-output response of the power factor circuit is verified with the experimental
results. Design guidelines for the low-frequency feedback network are presented.
Small-signal closed-loop responses are measured with an experimental power
factor circuit.Master of Science
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Diril, Abdulkadir Utku. "Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6929.
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Technology scaling trends lead to shrinking of the individual elements like transistors and wires in digital systems. The main driving force behind this is cutting the cost of the systems while the systems are filled with extra functionalities. This is the reason why a 3 GHz Intel processor now is priced less than what a 50MHz processor was priced 10 years ago. As in most cases, this comes with a price. This price is the complex design process and problems that stem from the reduction in physical dimensions.
As the transistors became smaller in size and the systems became faster, issues like power consumption, signal integrity, soft error tolerance, and testing became serious challenges. There is an increasing demand to put CAD tools in the design flow to address these issues at every step of the design process. First part of this research investigates circuit level techniques to reduce power consumption in digital systems. In second part, improving soft error tolerance of digital systems is considered as a trade off problem between power and reliability and a power aware dynamic soft error tolerance control strategy is developed.
The objective of this research is to provide CAD tools and circuit design techniques to optimize power consumption and to increase soft error tolerance of digital circuits. Multiple supply and threshold voltages are used to reduce power consumption. Variable supply and threshold voltages are used together with variable capacitances to develop a dynamic soft error tolerance control scheme.
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Zhu, Xingyu. "Design and evaluation of a battery power supply for a mobile XRF measurement system." Thesis, Mittuniversitetet, Institutionen för elektronikkonstruktion, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-41880.
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X-ray fluorescence is a fast, non-destructive method to measure substances. This method can be used to detect elements in an environmental sample for elemental analysis. Commercially available XRF units exists, but their scope of application is limited. In the university lab, a more generalized XRF setup is available. At present, the environmental samples can only be sampled and brought into the laboratory for testing. During the sample transport, some changes may occur in the sample. At the same time, in the laboratory test, the sample parameters in the current environment cannot be obtained in real time. So we consider the design of a battery power supply. At the same time, there are different ways to reduce power consumption. This paper considers usability and reduction of power consumption in various aspects to bring the X-ray source and spectrometer to the environment for element detection. We have to choose the battery to achieve the best length of operating time. The system design includes the selection of a DC/DC converter boost regulator to adjust the battery output to meet the input voltage requirements of the X-ray source and of the X-ray spectrometer.
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Kammerer, Marion K. [Verfasser]. "LTCC modules for power supply and IF circuitry in RF amplifiers / Marion K Kammerer." Aachen : Shaker, 2007. http://d-nb.info/1163610364/34.
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Terres, Marco Antonio de Souza Madeira. "Arquiteturas de conversores de tensão para circuitos com múltiplas tensões de alimentação ajustadas de forma dinâmica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/141259.
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Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MDSV, é alto. Uma vez que isso causa aumento da área total e altera a temporização do chip. Com base nisso, esse trabalho propõem adicionar um caminho alternativo para a corrente, desviando e desligando os conversores de tensão enquanto eles não são necessários. Cabe salientar que alguns conversores de tensão ficam sem utilidade por causa da característica dinâmica dos circuitos contruídos usando MDSV. Com isso, neste trabalho é proposta uma nova construção para os conversores de tensão utilizados em conjunto com o MDSV. Nas simulações elétricas, os circuitos contendo essa nova construção apresentaram redução no tempo de propagação de até 13%, em comparação aos circuitos tradicionalmente utilizados para conversão de tensão. Além da redução no tempo de atraso, foram alcançadas reduções no consumo de potência na ordem de 14%.Some techniques have been created with the purpose of reducing power consumption, among them the Multiple Dynamic Supply Voltage (MDSV). This technique aims to reduce the dynamic consumption using at least three different supply voltages inside the chip. Therefore, it is necessary that special protection circuits to be added to the chip. Level shifter aims to increase or decrease the voltage level of the input signal. The cost of introducing the voltage converters in circuits using the MDSV technique is high. As this causes increased total area and changes the timing of the chip. Based on this, this paper proposes to add an alternate path for current, deflecting off and the voltage converters as they are not required. It should be noted that some voltage converters are useless because of the dynamic characteristic of contruidos circuits using MDSV. Thus, this work proposes a new construction for the voltage converters used in conjunction with MDSV. In electric simulations, the circuit containing this new construction decreased to 13% in the propagation time in comparison to the circuits traditionally used for voltage conversion. In addition to reducing the delay time, reductions were achieved in the power consumption on the order of 14%.
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Walpole, Mark Edward. "Intrinsically Safe (IS) Active Power Supplies." Queensland University of Technology, 2003. http://eprints.qut.edu.au/15896/.
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Intrinsically safe (IS) active power supplies subjected to certain transient load conditions can deliver power to a circuit at significantly higher levels than indicated on their nameplate ratings. During a transient load such as an intermittent short-circuit, energy is transferred from the power supply to the short-circuit and an electrical arc may form when the short-circuit is applied or removed. This poses a spark ignition risk as energy is transferred from the arc to the surrounding atmosphere. Currently various International and Australian Standards define the performance requirements for IS electrical apparatus. A duly accredited laboratory is required to establish the intrinsic safety compliance of an apparatus with the Standards. It involves an assessment of the apparatus and may include testing. The assessment of the apparatus determines adequate segregation, separation, construction, and selection of components. The tests performed on the apparatus include a temperature rise test and in some cases, the sparking potential of the circuit is tested using the spark test apparatus (STA). Testing the sparking potential of active power supplies to establish compliance adds significantly to the time and costs involved in establishing compliance. A new alternative assessment method is proposed in this report to augment or replace the testing phase of the compliance certification process for active power supplies. The proposed alternative assessment method (PAAM) is derived from a determination of the steady-state and transient output characteristics of the active power supply under consideration. Parameters such as peak output current, time constant of peak current decay, and the output voltages at these times are measured from the circuit's output characteristics. These measurements can subsequently be used to derive the topology and component values of an equivalent circuit. The resulting equivalent circuit is then considered like a linear power supply and the sparking potential can be determined using existing assessment methods. This thesis investigates in detail the equivalent circuit of a number of direct current (DC) active power supplies whose transient output characteristics exhibit predominantly capacitive behaviour. The results of the PAAM using the equivalent circuit are then compared with results achieved using the current testing procedure with a STA. A small sample of active power supplies is used to generate data from which a relationship between the current testing procedure and the PAAM can be established. The PAAM developed in this research project can be used as a pre-compliance check by designers, manufacturers, or IS testing stations. A failure of this test would indicate that the active power supply's sparking energy is not low enough to be regarded as intrinsically safe. The PAAM requires fewer resources to establish a result than the STA. The benefits of a simplified spark ignition test would flow on from designers and manufacturers to end users.
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Llanos, Roger Vicente Caputo. "Voltage scaling interfaces for multi-voltage digital systems." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/159617.
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Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação.Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.
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Benedik, Christopher. "Modeling and Minimization of Integrated Circuit Packaging Parasitics at Radio Frequencies." Wright State University / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=wright1376605018.
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Ghossein, Layal. "Alimentation de circuit de commande rapprochée « Gate-drive » pour nouveaux convertisseurs de puissance haute tension." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI016.
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Le transport d’énergie par des lignes HVDC constitue le principal réseau de transmission d’énergie électrique du futur. Les convertisseurs de puissance (par exemple de type MMC) qui constitueront ce réseau devront être capables de gérer des tensions de l’ordre de centaines de kilovolts ce qui rend critique l’alimentation des dispositifs de contrôle (gate-drive) de ces convertisseurs. Il est nécessaire de concevoir des solutions qui garantissent l’alimentation de ces gate-drives avec une isolation.Pour ce faire, un circuit basé sur le principe du flyback et utilisant un JFET normalement passant a été développé. Il est placé en parallèle d’un condensateur typiquement connecté aux bornes d’un bras d’onduleur. Il permet d’alimenter le dispositif de puissance dès qu’une faible tension est appliquée à son entrée. Cette fonction est assurée grâce au caractère normalement passant du JFET. Pour le prototype développé, la tension du bras est de 2 kV. La tension de sortie est régulée à 24 V. De nos jours, des JFET normalement passants avec une tenue en tension supérieure à 2 kV n’existent pas sur le marché. Donc, pour supporter les tensions mises en jeu dans le circuit, une mise en série de JFET SiC normalement passants commandés par un MOSFET Si a été réalisée (montage « super-cascode »). Le circuit développé est capable de fournir 20 W pour alimenter des gate-drives à des potentiels flottants. Le rendement obtenu est proche de 60 %. Aussi, le problème d’isolation est résolu par cette solution d’auto-alimentationHVDC power transmission is the future of the electrical energy transmission network. The power converters (e.g. MMC) used in this network will be able to cope with voltages of hundreds of kV, making the power supply of the gate-drive devices in these converters challenging. It is then necessary to design solutions that guarantee the power supply of these gate-drives, while providing high voltage isolation. To do this, a circuit, based on the flyback principle, was developed. It is placed in parallel with a capacitor typically connected to a half-bridge circuit. It has an auto-start feature. This allows to supply the gate-drive as soon as a low voltage is applied to the input of the self-supply system. This is obtained by taking advantage of the normally-ON character of the JFET. In our prototype, the input voltage is 2 kV. High voltage JFETs of 2 kV and higher breakdown voltages are not yet available on the market. So, to achieve this high voltage capacity, a series of Normally-ON SiC JFETs controlled by a low voltage Si MOSFET (Super-cascode circuit) is used in the circuit. The developed circuit is able to supply 20 W at different floating potentials with output voltage regulated at 24 V and an efficiency close to 60%. The isolation problem is then solved using this solution
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Novák, Matyáš. "Návrh hardwaru řídící jednotky dieselového vstřikovacího systémuu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-241161.
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This master’s thesis deals with the basic design of diesel injection control unit hardware. There is a description of the whole blocks of Motorpal Common Rail diesel injection system in the introduction. Next are described requirement of control unit hardware. In the following are descriptions of parts, which was choosed for adjustment. The second part of thesis describes the whole design of control unit wiring diagram. There is described each block in detail in this part. Next part describes component placement on printed circuit board. The conclusion of thesis compare designed version of control unit with elderly versions.
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Labouré, Eric. "Contribution à l'étude des perturbations conduites dans les alimentations continu-continu isolées." Cachan, Ecole normale supérieure, 1995. http://www.theses.fr/1995DENS0010.
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Ce travail s'inscrit dans une démarche générale de réduction des perturbations électromagnétiques émises par les équipements électriques. Il s'agit d'étudier les perturbations conduites générées par les convertisseurs statiques haute fréquence moyenne puissance dans l'optique de réaliser un outil d'aide a la conception prenant en compte ces phénomènes. Notre étude utilise comme support deux alimentations continu-continu isolées (alimentation flyback et alimentation forward) représentatives des problèmes rencontres. Après un bref rappel sur les normes et sur les équipements correspondants, un capteur de courant adapte a l'étude des perturbations électromagnétiques dans les convertisseurs statiques est présenté. Un des objectifs de l'étude est de pouvoir prédéterminer par simulation le niveau de perturbations d'un convertisseur. Pour cela, il est nécessaire de disposer d'un modèle électrique pour chacun des ensembles qui le constitue. Les modèles développés dans ce document concernent le transformateur et les composants a semi-conducteur (diode et igbt). Afin que ces modèles soient simples et facilement intégrables a un logiciel de simulation de type circuit, des modèles comportementaux issus de la littérature sont utilises. Notre travail consiste à adapter ces modèles à notre étude, c'est à dire à obtenir une bonne représentation des composants dans la bande de fréquence 10khz-30mhz. Le comportement des alimentations flyback et forward est alors analyse, essentiellement par simulation. A partir d'un schéma élémentaire (composants idéaux) de l'alimentation, les différents éléments parasites sont ajoutes étape par étape. L'analyse des modifications observées dans le domaine temporel et fréquentiel permet de cerner les diverses origines des perturbations. Cette démarche est reprise avec l'introduction d'un écrêteur puis d'un calc non dissipatif. Les résultats obtenus par simulation sont compares aux résultats expérimentaux afin de valider l'ensemble de l'étude (modèles et résultats d'analyse). Enfin, divers moyens de reduction des perturbations sont analyses. Tout d'abord deux moyens de reduction a la source sont proposes. Puis diverses solutions de reduction des couplages sont présentées. Finalement, le filtrage est abordé et les diverses cellules usuelles sont étudiées et comparées
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Al-Baidhani, Humam A. "Design and Implementation of Simplified Sliding-Mode Control of PWM DC-DC Converters for CCM." Wright State University / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1590930594283361.
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Štaud, Stanislav. "Spínaný rezonanční zdroj." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219119.
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This thesis deals with desing of serial resonant converter with regulation output voltage in full bridge configuration like alternative power switching converter with pulse width modulation. The thesis includes analysis of serial resonant converter, desing power transformer, driving circuits. The thesis concludes with the functional converter and complete technical documentation.
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Pár, Lukáš. "DC/DC měnič s transformátorem 24 V / 350 V / 100 VA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-401972.
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This diploma thesis deals with design of DC/DC converter which will be used in one-phase inverter powered from batteries. Required parameters are output power of 100 W, input voltage of 24 V and output voltage of 350 V. In the first part is briefly discussed used topology of flyback converter. In the next part is designed impulse transformer with a request to design impulse transformer as small as possible. Thesis continues with draft of power components placed on primary and secondary side of converter. In this thesis is part about limitation of voltage overshoot at turn off transistor. Next part of this thesis deals with the design of control circuits using an integrated circuit from the UC384x family. Thesis continues with the production and debugging of the converter. At the end of this thesis are measurements confirming the correctness of the proposed design.
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Vaculík, Josef. "Svářečka pro obloukové svařovaní se spínaným zdrojem." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-218834.
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This diplom thesis theoretically deals about principle of pulse welding current source. Work explains operation principle of the single acting transmit converter used in realized construction and mention the others examples of converters types. Goal of the work is design individual parts of source : input filter, pulse transformer, output inductor and power semiconductors components. Thesis also contains description of the regulation circuitry of the converter, auxiliary power supply and pre-driver for power transistors. If everything will be all right prototype of the source will be assembled and measured. Results will be compared with theoretical assumptions.
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Dvořák, Petr. "Dvojčinný kvazirezonanční DC/DC měnič s transformátorem." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-412973.
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This diploma thesis deals with analysis of function and subsequent construction of a quasi-resonant DC / DC converter 300 V / 50 V for an output of about 1.5 kW. The aim of this work is to test and describe the behavior of an experimental converter at various operating parameters. In the theoretical part, resonant circuits are described, as well as our connection of the resonant converter. Based on the used topology and the simulated behavior of the converter, the individual components of the power circuit and its control and excitation circuit are designed in Chapters 4 and 5. The sixth chapter deals with the construction and testing of the converter, including a description of its behavior. The last chapter contains technical documentation.
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Li, Bo. "Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00782429.
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Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédictive: il introduit une nouvelle variable de contrôle qui est la position de la largeur d'impulsion permettant de contrôler de façon simultanée le courant dans l'inductance et la tension de sortie. La solution permet une dynamique très rapide en transitoire, aussi bien pour la variation de la charge que pour les changements de tension de référence. Les résultats expérimentaux sur FPGA vérifient les performances de ce contrôleur jusqu'à la fréquence de découpage de 4MHz. Un contrôleur numérique nécessite une modulation numérique de largeur d'impulsion (DPWM). L'approche Sigma-Delta de la DPWM est un bon candidat en ce qui concerne le compromis entre la complexité et les performances. Un guide de conception d'étage Sigma-Delta pour le DPWM est présenté. Une architecture améliorée de traditionnelles 1-1 MASH Sigma-Delta DPWM est synthétisée sans détérioration de la stabilité en boucle fermée ainsi qu'en préservant un coût raisonnable en ressources matérielles. Les résultats expérimentaux sur FPGA vérifient les performances des DPWM proposées en régimes stationnaire et transitoire. Deux ASICs sont portés en CMOS 0,35µm: le contrôleur en tri-mode pour le convertisseur abaisseur de tension et la commande par mode de glissement pour les convertisseurs abaisseur et élévateur de tension. Les bancs de test sont conçus pour conduire à un modèle d'évaluation de consommation énergétique. Pour le contrôleur en tri-mode, la consommation de puissance mesurée est seulement de 24,56mW/MHz lorsque le ratio de temps en régime de repos (stand-by) est 0,7. Les consommations de puissance de command par mode de glissement pour les convertisseurs abaisseur et élévateur de tension sont respectivement de 4,46mW/MHz et 4,79mW/MHz. En utilisant le modèle de puissance, une consommation de la puissance estimée inférieure à 1mW/MHz est envisageable dans des technologies CMOS plus avancées. Comparé aux contrôlés homologues analogiques de l'état de l'art, les prototypes ASICs illustrent la possibilité d'atteindre un rendement comparable pour les applications de faible et de moyen puissance mais avec l'avantage d'une meilleure précision et une meilleure flexibilité.
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Delaine, Johan. "Alimentation haute fréquence à base de composants de puisance en Nitrure de Gallium." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT012/document.
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Le projet de cette thèse est de réaliser un convertisseur DC/DC isolé à haute fréquence de découpage basé sur la mise en œuvre de composants en GaN. Le but est d'augmenter très fortement les densité de puissance commutées par rapport aux solutions actuelles. Cette thèse mets en oeuvre les composants GaN afin de déterminer les meilleurs conditions de fonctionnement possible. Une fois les points critiques mis en avant, on étudie les structures de circuit de commande adapté pour les HEMT GaN d'EPC et un circuit intégré pour la commande est étudié et mis en oeuvre. Le layout global de la carte a un rôle important en termes d'intégration et d'optimisation CEM, il est donc discuté et des règles de routage sont proposées. Enfin, on étudie plusieurs structures de puissance et on les met en oeuvre pour vérifier le bon fonctionnement et le respect du cahier des chargesThis study consist in the development of a high frequency insulated DC/DC converter based on GaN power devices. The goal is to increase significantly the power density in comparison with actual converter solutions. This thesis evaluate the GaN components performances to determine the best working conditions. Once the critical points highlighted, gate circuit topologies suitable for EPC GaN HEMT are studied and an integrated IC is designed and implemented. The overall layout of the card has an important role in terms of integration and EMC optimization, so it is discussed and routing rules are proposed. Finally, we study several power structures and implement them to verify proper operation and their compliance with specifications
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Matejov, Michal. "Pasivní PFC filtry pro spínané napájecí zdroje." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217598.
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This work deals with theory of switched power sources. There is description of the ways for connection and their practice purposes. In the next parts there are defined requirements on input supply circuit for these sources, especially for the form of output current. There are mentioned the basic connecting methods of PFC circuits and these methods modify the output current to meet the requirements of specification ČSN EN 61000- 3- 2. In the next parts there are shown simulations of PFC circuits made by Pspice application. Further is the basic description of sources construction for the sources which were used for testing and measuring. The final part deals with evaluation of the measuring on the chosen computer’s source. It compares between the manufacturer’s solutions and PFC circuit made by ourselves.
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Ptáček, Karel. "Vysokonapěťové struktury pro galvanickou iziolaci v integrovaných obvodech." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-417477.
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Tato dizertační práce představuje novou techniku laterární rezonanční vazby, která je využita v návrhu galvanicky izolovaného posouvače úrovně, který je následně implementován v 800 V půlmůstkovém kontroléru pro průmyslové aplikace. Ve srovnání s tradičními galvanickými izolátory jsou výrobní náklady tohoto řešení nižší. Pro aplikace vyžadující vyšší úroveň galvanické izolace je popsán následný vývoj galvanicky izolovaného posouvače úrovně, který využívá pouze jeden galvanicky oddělený posouvač úrovní pro komunikaci v obou směrech, což výrazně snižuje plochu struktury izolátoru. Jako součást následného návrhu je představen galvanický izolátor který je schopen přenášet analogovou hodnotu napětí. Analogový izolátor byl testován v reálné aplikaci síťového spínaného zdroje jako náhrada standardního optočlenu. Tato konstrukce umožňuje integraci primárních a sekundárních obvodů v jednom pouzdře, což umožní snížit složitost a cenu spínaného zdroje.